Kill Ratio Calculation for In line Yield Prediction

Alfonso Lorenzo', David Oter, Sergio Cruceta, Juan Francisco Valtuefla, Gerardo Gonzalez and
Carlos Mata.

Lucent Technologies Microelectronics, Tres Cantos, 28760 Madrid, Spain

ABSTRACT
The search for better yields in IC manufacturing calls for a smarter use of the vast amount of data that can be generated
by a world class production line. In this scenario, in-line inspection processes produce thousands of wafer maps, number of
defects, defect type and pictures every day. A step forward is to correlate these with the other big data-generator area: test.
In this paper, we present how these data can be put together and correlated to obtain a very useful yield predicting tool. This
correlation will first allow us to calculate the kill ratio, i.e. the probability for a defect of a certain size in a certain layer to
kill the die. Then we will use that number to estimate the cosmetic yield that a wafer will have.
Keywords: in-line inspections, defects, yield, kill ratio, yield prediction

1. INTRODUCTION
In all the mature IC fabs in the world, the main way to keep on increasing productivity and decreasing costs is yield
improvement13. Yield improvement is usually driven from two different sides at the same time. First is the in line
inspections, where wafers are scanned by different optical tools4 looking for particles, residues and all kind of defects that
can make the IC malfunction. On the other side, end-of-line engineers analyze the actual yield of the wafers and identify the
failing cause (Failure Mechanism Analysis or FMA), thus giving place to corrective actions that will lead to further yield
improvement5.

Both approaches are necessary for an effective and fast yield enhancement. Nevertheless they have been far away from
each other for a long time. Their procedures were independent and many times the same job was done twice.

The strength of in-line inspection is the ability to detect, identify and stop problems as soon as they appear. This fast
reaction saves a lot of money and makes the investment in expensive inspection tools completely worthy. Nowadays all fabs
are very interested about this strategy and develop smart and effective inspection policies. The amount of data generated in
different in-line inspections is huge. Usually, all these data are filtered by engineers or operators and soon forgotten, and
only a very small fraction of them are taken into account.
FMA engineers handle actual data of all chips that fail in a wafer, so they can really discern where there is a problem
and how important it is. An alarm from this group has to be considered as a very important one, and a reaction is usually
expected. The problem is that the alarm comes with some days/weeks of delay.
The optimum approach to yield improvement is to combine both sources of data67. The correlation of inspection and
probe data is helping many fabs to track problems and work out solutions for baseline yield losses. The big amount of data
allows the use of statistical correlations to obtain truly results and adds a very useful value to in line data. , as well as a
quicker reaction to crisis.
In this paper, we will show which data can be used for correlations, how the data are related and which information we
can get from them. We will present how can we use that information to improve the quality of the inspection data and how
we can help to improve yield. Finally, some real examples will be shown to prove the utility of this tool.

For further information, please contact author at all @lucent.com

Part of the EUROPTO Conference on Yield, Reliability, and Failure Analysis

258

in Microelectronic Manufacturing Edinburgh, Scotland May 1999

SPIE Vol. 3743. 0277-786X/99/$ 10.00

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2. KILL RATIO CALCULATION

2.1. Data collection
The calculation of the kill ratio parameters needs the collection of different kind of data: in-line data and probe data. Inline data come from the different optical inspection that we have set across the routing. The tools that are used for these
inspections are KLA 2132. This is the best tool for this analysis since it can find all kind of defects that can appear on a
wafer: particles, extra pattern, residues, missing pattern, etc. In addition, it is one of the few systems that can give an idea of
the size of each defect. Another advantage is that the location of the defects is extremely precise. This will help afterwards
to substract previous layer defects.

Usually8, a sample of all wafer is inspected at different levels during the fabrication. This information is stored in a
database for later processing. Every inspection is intended to find defects that were produced in the last few processing
steps, but all the time, defects from previous layers are detected. Thus, we are in a situation in which there is a lot of
redundant information.
To avoid this, a defect substraction is strongly recommended. Defects having coordinates that match with other defect
found in a previous inspection are flagged as carry-overs, while the ones that don't match at all (within a range of tolerance)
are considered as added defects. Only the latter ones are used for the calculation. In the database, together with the location
and size of the defects, we include the layer to which it belongs. A history of every die is then obtained, where we can see
how many defects it has, how big they are and where they have been added.
The other source of information is probe data. Every wafer is probed after the fabrication and we know the performance
of each die, whether it works or fails. The failing category is a useful piece of information, but we do ignore it for the sake
of simplicity. So, the only information we extract from probe data will be "good" or "bad" die.

Once the data are collected, we need to match both of them. This can be a problem because usually, in-line inspection
and probe data have different ways of defining the position of the die on the wafers. An algorithm has been developed to
compare both maps and check if they properly match.

2.2. Kill Ratio and Baseline Yield

The Kill Ratio can now be calculated. We first disregard all chips that have more than one defect. This is to avoid the
influence of a defect in the kill ratio of the others. The kill ratio is then calculated as the proportion of die having only one
defect that fail, over the total number of die with one defect. This can be displayed in the following formula:

KR = bad chips with one defect I (bad chips with one defect + good chips with one defect)
However, this simple calculation can lead us to inaccurate values due to the fact that not all the bad die are explained
with a defect-induced (hereafter, cosmetic) failure. There can be several mechanisms that cause a malfunction of the device
and are produced by a process marginality, wrong implant doses, incorrect gate width and many others. There can also exist
design-related issues responsible for a part of the yield loss.
In a mature production line, all these problems are usually faced in a different way. The number of failures assigned to
these factors are very much reduced and are considered as a baseline. No matter how important they can be for the yield,
they are undesirable for our correlation. To prevent from this error contribution, we need to calculate the "baseline yield"
for each wafer as explained in the following expression:

BY = bad chips with NO defect I (bad chips with NO defect + good chips with NO defect)
The baseline yield has to be calculated for each wafer, because it only depends on the history of that particular wafer and
the way it has been processed since the beginning. The final value for the kill ratio will be obtained by eliminating the
percentage of chips that would die with or without a defect (baseline yield).
Considering and calculating the baseline yield for all wafers has some advantages that we can summarize as follows:

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wafers having low yield because of non-cosmetic reasons can be removed from the kill ratio calculation

we can monitor the non-cosmetic percentage of the yield loss

the kill ratio obtained is only due to cosmetic defects, so it can be confidently apply to support in-line inspection

data.
As we already mentioned, the kill ratio calculation is just the proportion of two populations. It is obvious that the more
data we use, the more reliable the results will be. For that reason, a cumulative number of die is used to calculate the kill
ratio. When a new wafer is probed, the information is added to the existing probed wafers and the kill ratio is recalculated.
Our experience is that, for the first 100 die, some variations in the cumulative kill ratio are obtained. From there on, the kill
ratio becomes stable and reaches the final value.

2.3. Results
The output of this calculation should be a value of the kill ratio per defect size, inspection layer and design rule. As an
example, figure 1 shows the kill ratios obtained from real data in our Lucent plant in Madrid (Spain) for 0.35 design rule
wafers. The defect size has been grouped into various bins from 0.5 microns, the last one being for defects of more than 6
microns.

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Figure 1. Kill Ratios per size and layer. Data from Lucent plant in Madrid.

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(6,..)

The growing tendency of all layers indicate that the calculation has been done in a consistentway. The absolute value of
the kill ratios might not be exact, but, at least, we have a first indication about the killing potential of agiven size in a given
level. If we look at these curves in detail, we can also extract more information about the sensitivity of the differentlayers to
the cosmetic defects. For instance, back-end layers exhibit a higher slope for large defects than front-end layers. There is
also a spread of kill ratios for the smallest sizes: early layers have low values and while more advanced layers have a higher
value. This shows an increasing influence of these defects as the chip is being built.

In a logic fab like ours, a big issue is the diversity of devices that are simultaneously being made. Obviously, these
devices present a huge variety of designs and compactness making the same type of defect have different kill ratios in each.
For that reason, a calculation has to be performed for each device to get the maximum confidence out of it. Theproblem is
that the amount of data per device is not enough to have good statistics. As a starting point, the kill ratio is calculated for all
devices with the same design rule and also for the main big runners. Further work is currently in progress to avoid this
situation.
Another set of kill ratios has to be calculated if the design rules changes. In figure 2, we show the effect of dropping the
design rule from 0.35 to 0.3 microns. An increase in most of the size bins has occurred, in agreement with the higher
number of transistors in the device and the smaller critical distances. This result proved that all the approaches used for the
calculation are valid.

Finally, we should comment on another utility of these results which does not look into the yield itself. Atypical kill
ratio graph, like the one in Figure 1, is a valid reference to check the sensitivity of the inspection tools. Inspection engineers
need to know if their tools are able to detect what is actually killing the chips, so that the alarms thatare generated in line

are useful. In our case, since the data obtained are not erratic and the values reach as high as 50 to 60 percent of killing
potential, we are pretty confident that the inspections are correctly set. However there is always room for improvement in
sensitivity.

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3. YIELD PREDICTION
After the kill ratio values have been obtained, they can be used in multiple applications. For us, a key use of these
numbers should be the prediction of yield for wafers that are still being processed. The kill ratios plus the number, size and
location of the defects can be translated into "expected percentage of dead die" . Every chip in a wafer will have, after an
inspection process, a probability of loosing functionality. This probability is based on the defects found in that chip and the
calculated kill ratio for that specific device, layer and defect size. In case there is more than one defect in the chip, the kill
ratio is added to have a global dying probability for the whole die. This addition is useful in case of cluster defects such as
scratches.

The yield prediction is the answer to the main questions of every yield engineer: how damaged is the wafer I just
inspected?, which defect should I work in to improve yield the most? These, and many other issues can be addressed using
the kill ratios to estimate the yield losses as wafers are inspected. Initially, we developed several reports to help yield
enhancement engineers in their daily and future job:
-

Trend chart of percentage of dead chips

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Analysis of wafer yield loss

3.1. Trend chart for the percentage of dead chips

The well-known graphs in which the defect density is plotted for every wafer have been transformed into a new chart
with the percentage of estimated dead die. This is very useful to set up scrap criteria, i.e. the convenience of stopping a
wafer and throwing it away because its yield will be poor. This kind of decisions can save a lot of money and they need to
be very carefully considered.

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Figure 3. Predicted yield chart at gate etch level.

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Usually, scrapping criteria are not clearly established, and that decision depends on the engineer's experience. A long
time and efforts need to be dedicated to come up with a solution for the bad wafer. Yield prediction is just another tool that
can be used to scrap wafers in a more consistent way. Although it needs to be checked by an expert, it will save time and
will make the decisions more objective.
In Figure 3, the percentage of expected dead chips is depicted for the wafers inspected at gate etch level. A limit can be
established to alert from wafers with a high percentage of bad die, according to yield and customer requirements. This chart
is more sensitive to yield than the standard defect density chart, because it combines size of defects, number of defects per
die, kill ratio and percentage of affected die. Thus, we believe that it can be a good tool to take yield-based decisions in-line.

3.2. Top 10 issues

This pareto is intended for prioritizing the engineer efforts in the problems that really affect yield. Every week, this plot
S automatically generated with the data from the last seven days. We group all wafers inspected at each level, estimate the
percentage of dead chips per wafer and calculate the average of them all. The output is a pareto in which the first bar is the
layer that is causing the highest yield loss during the last week, as can be seen in Figure 4a.
In the y-axis, the percentage of lost die, in average, is represented. Thus, we can estimate the yield improvement that can
be obtained if we work on removing the defects in that specific layer. Engineers work can be easily converted into chips
saved and yield improvement. Managers can use this tool to focus their people in some projects based on estimated yield
impact.

An additional graph is also provided to support the previous one. It consists of a historical chart of the average
percentage of dead die for the last weeks. This is very important, because it gives an idea of the evolution of the yield loss
contribution of every level. The number of weeks in the top first positions can also drive engineers to work on the associated
processes. Figure 4b shows an example of this particular plot.
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Figure 4a. Top 10 yield losing layers

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Figure 4b. Yield loss evolution at metal 1 level

Another important use of this data is the possibility of predicting the yield impact of a process change or a tool crisis. By
monitoring the defect density increase or decrease and converting it into percentage of dead die, we can estimate the shift in
yield some weeks in advance. This has been proved to be efficient as it will be explained later on in a case study.

We can also go further in the yield prediction. A usual information required by the product engineers in order to load a
fab with wafers of a specific device, is the expected yield. Different approaches have been developed to try to get a number
indicating the top yield that can be achieved in the present conditions. The yield prediction tool that we are introducing in
this paper is able to account for this need quite precisely. Knowing the design rule, the device and the current defect density
per defect size at this time, a cosmetic yield loss can be predicted for wafers to be processed in the near future.

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3.3. Wafer yield loss analysis

In many occasions, it can be of use to have information about the yield loss of a single wafer. In a wafer basis, some
reports are also available, showing all the data than can be calculated from in-line and probe data of that wafer. The first
report is a pareto with the yield loss contributors. At a glance, anyone can see the cosmetic information condensed in a
single plot that also gives the estimated dead chips at each layer. The final test yield can then be compared with these data to
check if the low yield can be explained with a particle problem or there is something else. The yield loss pareto for a
specific wafer is displayed in Figure 5.
Wafer maps can also be viewed. For a specific wafer, every
chip has a dying probability which is shown in a colored scale. If
the wafer has already been tested, the result can also be seen as
the chips are labeled good or bad. This allows to see if there is a

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good correlation between the in-line prediction and the actual

probe data. Obviously, since the kill ratio calculation is just a
statistical analysis, the more chips the wafer has, the better the

agreement will be. In Figure 6a, a wafer map is displayed,

showing this correlation. Figure 6b shows the same data in a
histogram format. In each bar, the number of good and bad die is

differentiated by color (dark or light). The bars mean the

estimated probability for the chip to fail.
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complete and the error in the prediction is lower. Therefore, this
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analysis tool requires a smart sampling plan, in which the wafers must be are inspected in all layers.

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4. CASE STUDIES
4.1. Process change at metal etch
As it was mentioned before, the in/line data can be viewed with a new perspective when complemented with the kill
ratio information. In this case, we will show an example in which the impact of a process change can be foreseen a week in
advance.

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The situation was such that a big yield loss was occurring due to problems in the metal etch tools. A high number of
defects were causing shorts between the metal lines with a big impact in yield. The use of the yield prediction tool,
advanced a yield improvement of about 4% if those defects were removed, as shown in Figure 7a.

A great effort was dedicated to that specific process and engineers came up with a solution. The defect density decreased
considerably and that information was translated into percentage of good die per wafer (see Figure 7b). By the time when
the change was done, we had a value of the predicted yield improvement. Ten days after, probe data confirmed the shiftin
yield., proving the ability of this tool to predict the future yield.

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4.2. Scrapping wafers in an more objective way

The procedure of scrapping bad wafers is now strongly supported by the in-line yield prediction. As it was explained
above, a yield loss graph is generated on the fly including all the wafers that are inspected. The kill ratioare used to estimate

the probability for a chip to

be killed by a defect.

KLA map

In a quick view, the

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the case when the value is too
high (out of control),

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not wrong (false defects in

the inspection, special nonkiller defects, etc.). Then, the

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Figure 8. Example of a low yield wafer detected in-line
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5. CONCLUSIONS
In-line data and probed data need to be very closely correlated. Yield improvement in a modern fab requires giving some
sense to the huge amount of data generated every day. Kill ratios are a simple way to obtain a lot of information from data

that is already available. The kill ratio calculation is a statistical approach that becomes reliable as far many data are
involved. In our case, considering the single chip as a unit independent from its wafer has helped to achieve good and
consistent results.

Subtracting the baseline yield from the calculation has turned into a tremendous noise reduction. Eliminating low
yielding wafers keeps the kill ratios stable with time and independent from crisis and excursions. In addition, the actual
cosmetic yield can be obtained. The yield prediction is then based on in/line data and defect reduction projects can be
monitored through this tool.
More important than the kill ratios themselves is the yield prediction utilities that derived from them. Scrapping criteria,

future yield trend charts, top ten priorities, wafer yield loss analysis and many others can help yield enhancement
organizations in their daily work. The case studies that have been explained, are just few examples of the advantages that
this tool can bring into a fab.
Nevertheless, we have proved that the best results will be obtained if an intelligent sampling is implemented in the inline inspections. Accurate and meaningful results require the use of adder defects. Thus, the same wafer has to be inspected
in every layer across the routing. On the other hand the whole wafer should be inspected. Sampling strategies that reduce the
inspected wafer surface lead to poorer statistical results. Finally, a wafer should have all the possible inspection performed
in order to optimize the prior level substraction (adders defects).

6. ACKNOWLEDGEMENTS
The authors would like to thank Jos Lopez and Jos Angel Peinador for their initial ideas and Marga Espino and Javier
Castao for continuous help and support. Thanks should also be given to Kathleen Terryll for her final supervision of the
manuscript.

7, REFERENCES
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P.Prator, "SEMATECH develops Software for Yield Enhancement, Defect Tracking" , Solid State Technology, pp
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4. R. Ceton, R. Goodner, F. Lee, P. Wang, "Comparison of Patterned Wafer Defect Detection Tools for General Inline Monitors", IEEE SEMI Adv. Semicon. Manuf. Conference, pp 92-99, 1996.

5. M. Recio, A. Fernndez, V. Martin, M.J. Pemn, G. Gonzalez, JR. Hoyer, S. Whitlock, D. James and M. Hansen,

"Advanced Software System for Yield Improvement in Manufacturing Fab", Proceedings on SPIE 1996
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6. M. Effron, "Integrated Yield Management: A Systematic Approach to Yield M;anagement", IEEE SEMI Adv.
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7. K. Zinke, R. Spencer, D. Freeman, "The Effectiveness of Defect to Yield Correlation", IEEE SEMI Adv. Semicon.
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8. M. McIntyre, R. Nurani, R. Akella, "Key Considerations in the Development of Defect Sampling Methodologies",
IEEE SEMI Adv. Semicon. Manuf. Conference, pp 8 1-85, 1996.
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