PENTIUM

Features:
Data bus: 64 Bit; Address bus: 32 Bit
It has Superscalar Architecture (1 Floating point processor and 2 integer
processors (U & V)).
Fast Numeric coprocessor, 5 times faster than 80486 numeric coprocessor
Dual integer processor (U & V) that often allows 2 instructions per clock.
Data cache: 8KB & Instruction cache: 8KB
Dynamic branch prediction logic allows efficient execution of programs
Two modes of operation: Real & Protected
Architecture:
The Pentium processor is a complex machine with many interlocking parts. It mainly
consists of two integer pipelines, the U pipeline and V pipeline. These pipelines are
responsible for executing 80x86 instructions. A floating point unit is included on the chip
to execute floating point instructions. Thus the Pentium can execute three instructions in
one clock cycle.

The Pentium communicates with the outside world via a 32-bit address and 64-bit data
bus. The bus unit is capable of performing burst read and writes of 32 bytes to memory,
and through bus cycle pipelining, allows two bus cycles in progress simultaneously.
A 8KB instruction cache is used to provide quick access to frequently used instructions.
When a instruction is not found in instruction cache, it is read memory (RAM) though
external data bus and a copy is place into the instruction cache to fetch instructions as
fast as possible. The prefetch buffers maintain a copy of next 32 bytes of prefetched

code and can be loaded from the cache in a single clock cycle due to the 256-bit wide
data output of the instruction cache.

Special Pentium Registers:

A new control register CR4 is added to the existing CR0 to CR3 registers. In addition to
this few more bits are defined CR0 and CR3 registers.
3
1

3
0

2
9

2
8

2
7

2
6

2
5

2
4

2
3

2
2

2
1

2
0

1
9

1
8

1
7

1
6

1
5

1
4

1
3

1
2

1
1

1
0

M
C
E

Page Directory base

D
E

T
S
D

P
V
I

V
M
E

CR
4

P
E

CR
3
CR
2
CR
1
CR
0

P
S
E
P
C
D

P
W
T

E
T

T
S

Page fault linear address

Reserved
P
G

C
D

N
W

A
M

W
P

N
E

E
M

M
P

There are two events associated with the cache.

Write through: Write through is a storage method in which data is written into the
cache and the corresponding main memory location at the same time. The cached data
allows for fast retrieval on demand, while the same data in main memory ensures that
nothing will get lost if a crash, power failure, or other system disruption occurs. Although
write through minimizes the risk of data loss, every write operation must be done twice,
and this redundancy takes time. The active application program must wait until each
block of data has been written into both the main memory and the cache before starting
the next operation. The "data insurance" therefore comes at the expense of system
speed. Write through is the preferred method of data storage in applications where data
loss cannot be tolerated, such as banking and medical device control.
Write back: In less critical applications, and especially when data volume is large, an
alternative method called write back accelerates system performance because updates
are normally written exclusively to the cache, and are backed up in the main memory
only at specified intervals or under certain conditions.
CD (Cache Disable): controls the internal cache. If CD=1, the cache gets disabled.
NW (Not write-through): selects the mode of operation of the data cache. If NW=1,
the data cache is inhibited from cache write through.
AM (Alignment mask): enables alignment checking when set.
WP (Write protect): Write protect protects user level pages against supervisor level
write operations. When WP = 1, the supervisor can write to user level segments.
NE (Numeric error): Numeric error enables standard numeric coprocessor error
detection. If NE = 1, the FERR pin becomes active for a numeric coprocessor error. If NE
= 0, any coprocessor error is ignored.
VME (Virtual mode extension): enables support for the virtual interrupt flag in
protected mode. If VME =0, virtual interrupt support is disabled.

PVI (Protected mode virtual interrupt): enables support for the virtual interrupt flag
in protected mode.
TSD (Time stamp disable): controls the RDTSC instruction.
Note: Time stamping is the process of counting the processor cycles since the reset.
DE (Debugging extension): enables I/O breakpoint debugging extensions when set.
PSE (Page size extension): enables 4M-byte memory pages when set.
MCE (Machine check enable): enables the machine checking interrupt ( is a type of
computer hardware error that occurs when a computers CPU detects a hardware
problem). Microsoft Windows displays the error using the blue screen of death containing
the error message

EFLAG:
Three new bits are added to the existing bits of EFLAG of 80486.
3
1

3
0

2
9

2
8

2
7

2
6

2
5

2
4

RESERVED

2
3

2
2

2
1

2
0

1
9

1
8

1
7

V V
I
A
I I C
D
P F

1
6

V
M

1
5

1
4

1
3

R
N
0
F
T

1
2

IO
PL

1
1

1
0

O D I T S Z
A
P
0
0
F F F F F F
F
F

C
F

VIF (Virtual interrupt flag): It can be modified by STI and CLI instructions when the
processor operates in virtual 8086 mode.
VIP (Virtual interrupt pending): It is set by an external device to indicate that it
service.
ID (Identification flag): It is used to test for the CPUID instruction. If a programmer can
set or reset the ID falg, the processor supports the CPUID instruction.