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Evaluation of NOC Using Tightly Coupled Router Architecture: Bharati B. Sayankar, Pankaj Agrawal
Evaluation of NOC Using Tightly Coupled Router Architecture: Bharati B. Sayankar, Pankaj Agrawal
e-ISSN: 2278-0661,p-ISSN: 2278-8727, Volume 18, Issue 1, Ver. II (Jan Feb. 2016), PP 01-05
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Abstract: One of the most important role in many core system is played by Network on Chip (NoC).
Researchers are recently focusing on the design and optimization of NoC. In this paper we describe the
architecture of a tightly coupled NoC router. To improve the network performance the router uses the on-chip
storage and to improve the use of on-chip resource and information, several optimizations are introduced. In
theory this design can save 9.3% chip area. The experiment shows that the latency can be reduced to 75% by
the process of optimization on the ejection process and energy consumption by 31.5% in heavy traffic load
network. Under different buffer depth, it can also improve latency by 20% and energy consumption by 25%.
The experimentally results also prove that this tightly coupled router architecture can achieve better
performance in the large scale network.
Keywords: virtual cut through, wormhole ,latency, deadlock
I.
Introduction
NoC i.e. Network-on-chip connects a large number of cores in network style, it was first raised in 2001.
It provides parallel communication to the cores. It has two characteristics; firstly, during transmission the data
latency between any two cores is variable according to congestion conditions. In on-chip conditions it is
unacceptable if some data is delayed for a long time. Second characteristic is that frequent communication
between cores leads to heavy load or heavy wire load which brings high power dissipation. The basic function
unit in on-chip network is router. A basic router consists of a buffer, routing logic, arbiter and crossbar. The
received packet or flit are stored in buffer, it dependents on the flow control pattern. To reduce energy
consumption and area the most direct method is to reduce buffer size. But for the most popular wormhole router,
insufficient buffer leads to high latency. Therefore the mechanics of latency reduction should be carefully
designed in wormhole router. In this paper we will discuss about different routing mechanisms and select the
best one to make better use of the on-chip processes.
II.
Proposed System
Wormhole Network
Wormhole routing is a system of simple flow control in NoC. It is based on fixed links, in the absence
of blocking it takes message latency almost independent of the intermediate distance. In this network packets are
broken down into small packets called flits. The header flit is the first flit, it consist of all the information about
the packet`s route i.e. the destination address. It also sets up the routing behavior for all subsequent flits
associated with the packet. The head flit i.e. the first flit is followed by more body flits that contain the actual
pay load of data. To close the connections between two nodes, the final flit i.e. the tail flit performs the function
of book keeping. The data flits are blocked behind blocking the header occupying all the channels and the
DOI: 10.9790/0661-18110105
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Virtual Cut-Through
A message arriving at an intermediate node is immediately forwarded to the next node on the path
without buffering, provided that a channel to the next node is available. This is referred to as the cut-through
operation. When the header arrives with the destination information a cut through can be performed at the
intermediate node. If cut-through are established between all intermediate nodes then a circuit is established to
the destination. If the request outgoing channel is unavailable the message header is blocked at an intermediate
node and the message is completely buffered at the current node. In this cut-through when a packet cannot cutthrough an immediate node, the packet is buffered at the node instead of being kept in the network. This helps it
to achieve high performance.
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III.
Implementation
DOI: 10.9790/0661-18110105
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IV.
Result
Table II & III shows the comparison of various parameters XY,WH,VCT with Dynamic Priority
Round Robin Algorithm.
Table II
PARAMETE
RS
AVAILA
BLE
XY
WH
VCT
VCT
+XY
Number of
Slices
28800
4%
0%
1%
0%
Number of
slice LUTs
28800
7%
1%
1%
1%
Number of
LUT-FF Pairs
-----
---
15%
30%
20%
Latency
-----
3.920n
s
2.525ns
2.826ns
5.600
ns
Route Latency
-----
1.294n
s
1.871ns
0.286ns
3.174
ns
Power
-----
11.24
mW
15.65
mW
10.56
mW
12.66
mW
-------
32.65
GbPS
50.693
GbPS
45.293
GbPS
22.85
GbPS
Throughput
Table III
PARAMETERS
AVAILABLE
VCT+WH+XY
VCT+WH+XY
With
DPRRRC
Number of Slices
28800
0%
0%
Number of slice
LUTs
28800
6%
2%
-----
4%
15%
Latency
-----
4.487ns
4.677ns
Route Latency
-----
3.447ns
3.006ns
Power
-----
11.44 mW
9.65 mW
Throughput
-----
28.526 GbPS
27.367 GbPS
DOI: 10.9790/0661-18110105
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Conclusion
The comparison of XY, WH, VCT was done and on comparison of the outputs VCT was found to be
the better algorithm. The results using hybrid VCT algorithm were also evaluated. These results using hybrid
VCT with DPRRRC were determined effectively. The results of hybrid VCT and hybrid VCT with DPRRRC
were compared and route latency, power and throughput were found to be decreased.
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DOI: 10.9790/0661-18110105
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