PHD MYarleque

KATHOLIEKE UNIVERSITEIT LEUVEN
FACULTEIT INGENIEURSWETENSCHAPPEN
DEPARTEMENT ELEKTROTECHNIEK (ESAT)
AFDELING ESAT-TELEMIC
Kasteelpark Arenberg 10, B-3001 Leuven (Heverlee), Belgi
RF POWER AMPLIFIERS
FOR WIRELESS COMMUNICATIONS
Promotors:
Prof. Dr. Ir. B. Nauwelaers
Prof. Dr. Ir. D. Schreurs
Proefschrift voorgedragen tot

het behalen van het doctoraat
in de ingenieurswetenschappen
door
Ir. Manuel Augusto Yarlequ Medina
June 2008
KATHOLIEKE UNIVERSITEIT LEUVEN

FACULTEIT INGENIEURSWETENSCHAPPEN
DEPARTEMENT ELEKTROTECHNIEK (ESAT)
AFDELING ESAT-TELEMIC
Kasteelpark Arenberg 10, B-3001 Leuven (Heverlee), Belgi
RF POWER AMPLIFIERS
FOR WIRELESS COMMUNICATIONS
Jury:
Prof. Dr. Ir.- Arch. H. Neuckermans,
voorzitter
Prof. Dr. Ir. B. Nauwelaers, promotor
Prof. Dr. Ir. D. Schreurs, promotor
Prof. Dr. Ir. A. Barel (VUB)
Prof. Dr. Ir. P. Wambacq (VUB/IMEC)
Prof. Dr. Ir. R. Mertens
(KULeuven/IMEC)
Prof. Dr. Ir. D. Vanhoenacker-Janvier
(UCL)
Prof. Dr. Ir. P. Colantonio
(Universit di Roma Tor Vergata,
Italy)
Proefschrift voorgedragen tot

het behalen van het doctoraat
in de ingenieurswetenschappen
door
Ir. Manuel Augusto Yarlequ Medina
U.D.C. 621.3.049.77
Wet. Depot : D/2008/7515/66
ISBN 978-90-5682-957-5
June 2008
Katholieke Universiteit Leuven - Faculteit Ingenieurswetenschappen

Arenbergkasteel, B-3001 Leuven (Heverlee), Belgi
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Wet. Depot : D/2008/7515/66
ISBN 978-90-5682-957-5
Acknowledgment
A journey of a thousand miles begins with one step. This has been a very
long journey, longer than I expected. Nevertheless, it has been an enriching expedition
with new experiences and challenges. I would not have reached this point without
the help and support of the people I met on this quest and the friends from here and
all over the world and my family in Peru.
While I am writing down these lines, it is raining heavily, which is somehow a recurring
feature in Belgium. Despite this being disturbing, particularly to Latin people, rain
stirs up in me joyful memories. My friends and I playing football in the rain, totally
soaked, falling down over the artificial grass that was more water than grass and each
fall a shower! Even more amazing, we played in the snow as well. It was a unique
experience, running and jumping over thick snow, kicking the snow instead of the ball
and doing our best to try to defeat the opposite team. But overall, we had lots of
fun.
First, I would like to thank the support of the SBA scholarship program of the KU
Leuven, which provided me with the facilities and resources to start, pursue and finish
my doctoral studies. My thanks are due to my home university in Peru, Pontificia
Universidad Catlica del Per. In addition, I would like to thank the former European
Network of Excellence (NoE) TARGET, which allowed me to realize fruitful scientific
interchanges with other European universities related to my research area.
Above all, I would like to thank God because He chose this place (Leuven-Heverlee)
for me. He knew that here I would find everything I needed to carry out this project
and realize my dream; the vibrant scholarly atmosphere, the friends, the church community, the sports facilities, the forest, the castle, nature replete with birds. No, I do
not think He forgot anything.
I would like to thank my two promoters, Professors Dominique Schreurs and Bart
Nauwelaers for all the academic and extra-academic assistance.
Dominique Schreurs, who was also my office mate, provided me with abundant scientific information, which was valuable for my research. Likewise, she introduced
me to academics from other European universities, which was of high importance for
the development of this investigation. Additionally, she managed to proofread all my

papers, and even exceeding her own time, did a thorough revision and correction of
my thesis manuscript. Her open and cheerful character contrasts with my reserved
and shy personality. I remember that she broke up my silence many times to chat
for a while, which turned out to be very refreshing and this frequently ended up in
laughter. I want to express my deep gratitude to her for all this.
Bart Nauwelaers, who with his smart advice and refined sense of humor, relieved some
of the tense moments during the course of this research. I remember particularly that
after staying working at the faculty over the Christmas and New Year holidays, I was
feeling exhausted and down, then he came to my office to greet me and his enthusiasm
and cheer changed my mood completely and recharged my energy. Furthermore, he
provided me with all the necessary means to continue my research when the time and
the resources had expired. For all this and also for making time in his very tight
agenda to proofread my thesis, I am very grateful to him.
I would like to thank my research group Telemic for providing me with assistance
from the very beginning and during the course of this adventure, in particular to
my colleagues Dave Trappeniers and Ilja Ocket and the secretary Ann Deforce. A
very special acknowledgment to the former Telemicer Peter Delmotte, his technical
assistance and clever ideas were fundamental for this investigation. Additionally, I
want to express my gratitude to my colleague Maciej Myslinski for his important
collaboration on the execution of the measurements. On the other hand, I am also
grateful to all the technicians of the ESAT mechanical and electronics workshop, in
particular, to Ms. Noella Gaethofs for her sympathy and patience during the whole
device mounting process.
This part of the acknowledgment crosses the Belgian borders and goes to the University of Rome Tor Vergata. I want to express my gratitude to professors Franco
Giannini and Paolo Colantonio, for their invaluable assistance and guidance during
my stay in their institution. I have to truly confess that the experience I gained there
allowed me to clearly mark the path to follow for the final development of this investigation. Additionally, I would like to express my very warm thanks to my Italian
colleagues Rocco, Augusto, Antonio, Patrick and Marco for their company and friendship during my stay there. Finally, my gratitude to Professor Iltcho Angelov from
the University of Chalmers, Sweden, without his support, the essential non-linear
modeling task would not have been finished successfully.
I am also very grateful to all the members of my examination committee for realizing
a thorough revision of the manuscript and providing me with important insights and
remarks that improved the contents and quality of this final manuscript.
During the first years of my doctorate, I had the constant support (although she was
in Peru) of Ms. LiliAna Mendoza. I want to express my gratitude to her for all her
understanding, friendship and comforting. She had a lot of faith that I would finish
this work and always expressed it so that I would not forget it. I am grateful to her
for this.
ii
With the risk of forgetting someones name, I would like to express my appreciation and gratitude to all the international friends I met on this journey: Aude (from
France), Sonja (from Germany), Onur (from Turkey), Javier (from Spain), Roberto
(from Mexico), Oscar, Jairo, Don Jairo and Elizabeth (from Colombia), Claudia,
Daniela, Sandra (from Chile), Diego, Mauricio, Marcelo (from Bolivia), Luis (from
Ecuador), Els, Sandra, Ellen, Joke and Bart (from Belgium). I am thankful to my
compatriots and friends Josefina, Romina, Antonio, Fernando, Luis, and Javier. Additionally, I want to thank my friends Geert and Chris, from the conditioning training
class, Wouter, Julian and Sebastian from Football Leuven, and finally from my dancing class, I would like to thank Rommy, Katrien, Sandy and Ives. And overall, I
would like to express my gratitude to all these friends whose names I cannot recall,
for a strange and unfair reason, at this moment, but I am sure that they were utterly
important and I am indebted to them.
I would also like to express my profound gratitude and acknowledgment to three
special people. To Ms. Maria Adela, for her friendship, company, special attention
and caring for me at every moment. To Ms. Isabel Fernandez, for her determined
and opportune counseling. And to Ms. Vina Vaswani, for her invaluable friendship
and support as well as for all the transcendental talks and advice.
A special thanks to my parents and my brothers. Despite the distance, they always
made me feel that I was with them in Peru. One of my brothers often liked to joke
that I was calling up from a public telephone in Lima, very close to home, and that I
would suddenly show up. The telephone talks with my mum were always comforting
and cheering. I believe I received the persevering and stubborn character from her,
without which it would have been hard to finish this job.
Finally, I want to reserve these last lines to my dearest love; to this long-awaited and
unrevealed love that I endeavor to find. I am not sure yet if you were already in my
dreams or whether you somehow accompanied me all this time without me realizing.
However, I have to thank you for being this last motivation and driving force that
ultimately took me to the end of this journey. Gracias Amor Mio.
Manuel Yarlequ
Leuven, June 2008
iii
Abstract
The most recent standards for wireless communications have resorted to the Orthogonal Frequency Division Multiplexing (OFDM) technique to reduce channel impairments. Multipath fading and intersymbol interference (ISI) can be limited by using
multiple orthogonal sub-carriers. Nevertheless this OFDM signal exhibits large instantaneous signal amplitudes compared to its average values. This compels the use
of linear amplifiers working with several dB backoff with respect to their 1 dB compression point (P1dB). In this way, the entire OFDM signal is amplified linearly;
however at the cost of a very poor efficiency. This increases the energy consumption
and reduces operating time per battery charge of mobile terminals. Hence, providing
linear amplification with high efficiency has become one of the major challenges for
current RF amplifier design for wireless communications.
Several techniques are under research to tackle this problem. These techniques can be
classified as linearity and efficiency oriented techniques. Predistortion, feedforward
and feedback techniques are examples of the first kind of technique. They mainly
correct the inherent distortion of the amplifier by providing an inversion function of
the amplifier or by comparison with the original input signal. Examples of the second
type of technique are dynamic biasing, dynamic load and Envelope Elimination and
Restoration (EER), which basically vary the bias or load of the amplifier according
to the input signal.
This PhD-thesis has focused on Doherty amplifiers (dynamic load technique) and
high efficiency class-E amplifiers (main amplifier in EER) applied to WiMAX at 3.5
GHz. In the design process of these amplifiers, the concept of equivalent capacitance
is introduced and applied successfully. Measurements of the designed Doherty amplifier confirm the potential benefits of this technique in terms of overall efficiency and
linearity in comparison with legacy class-AB amplifier. Nonetheless, this design task
is not possible without a reliable and sturdy device model. Hence, the task of constructing a non-linear model for a GaAs HEMT device was undertaken in this thesis,
which gave fine results. The conjunction of this reliable model with the equivalent capacitance concept has made possible the contemporization of aged design techniques
to face the stringent requirements of modern wireless communications.
Samenvatting
De meest recente standaarden voor draadloze communicatie maken gebruik van Orthogonal
Frequency Division Multiplexing (OFDM) technieken om de transmissiefouten veroorzaakt
door het kanaal te beperken. Multipad fading en intersymboolinterferentie (ISI) kunnen
beperkt worden door het gebruik van meerdere orthogonale subdraaggolven. Dit OFDMsignaal vertoont echter grote ogenblikkelke signaalamplitudes in vergelking met de gemiddelde waarden. Dit maakt het noodzakelk om lineaire versterkers te gebruiken met meerder
dB backoff ten opzichte van het 1 dB compressiepunt (P1dB). Op deze wze wordt het totale
OFDM signaal lineair versterkt, echter ten koste van een zeer lage efficintie. Dit verhoogt
het energieverbruik en vermindert de werkingsduur per batterlading van een mobiele terminal. Daarom is het lineair versterken met een grote efficintie een van de grote uitdagingen
voor het huidig ontwerp van RF-versterkers voor draadloze communicatie.
Verschillende technieken worden onderzocht om dit probleem aan te pakken. Deze technieken
kunnen gerangschikt worden als gericht op lineariteit of op efficintie. Voorvervorming,
voorwaartskoppeling en terugkoppeling zn voorbeelden van het eerste type van techniek.
Deze corrigeren vooral de inherente vervorming van de versterker door een inverse functie
van de versterker te gebruiken of door een vergelking met het originele ingangssignaal.
Voorbeelden van technieken van het tweede type zn dynamische instelling, dynamische
belasting en omhullende eliminatie en restoratie (EER), waarb in essentie de instelling of
de belasting van de versterker wordt gevarieerd in overeenstemming met het ingangssignaal.
Deze doctoraatsthesis focusseert zich op Doherty-versterkers (techniek met dynamische belasting) en hoge efficintie klasse E versterkers (de hoofdversterker b EER), en dit toegepast
op WiMAX b 3.5 GHz. In het ontwerpproces van deze versterkers werd het concept
van equivalente capaciteit met succes ingevoerd en toegepast. Metingen van de ontworpen Doherty-versterker bevestigen de potentile voordelen van deze techniek in termen van
globale efficintie en lineariteit in vergelking met traditionele klasse AB versterkers. Niettemin is de ontwerpopdracht niet mogelk zonder een betrouwbaar en robuust model voor
de transistoren. Bgevolg werd het construeren van een niet-lineair model voor een GaAs
HEMT transistor een van de taken in deze thesis, en dit werd met gunstig gevolg volbracht.
Het samenvoegen van dit betrouwbare model met het concept van de equivalente capaciteit
heeft het mogelk gemaakt om de oude ontwerptechnieken te moderniseren, zodat ze het
hoofd kunnen bieden aan de strenge vereisten voor moderne draadloze communicatie.
vii
Contents
Acknowledgment
Abstract
Samenvatting
vii
List of acronyms
xv
List of symbols
xvii
1 General introduction
1.1
Introduction and motivation . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Scope of the research work . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Chapter descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 RF power amplifier basics
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Basic RF amplifier characteristics . . . . . . . . . . . . . . . . . . . . .
2.3
Load line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Figures of merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
2.4.1
Drain efficiency and power added efficiency . . . . . . . . . . .
12
2.4.2
Harmonic distortion and intermodulation distortion . . . . . .
14
ix
Contents
2.4.3
Adjacent channel power ratio . . . . . . . . . . . . . . . . . . .
17
2.4.4
Error vector magnitude . . . . . . . . . . . . . . . . . . . . . .
18
Class of amplifiers: from class-A to class-C . . . . . . . . . . . . . . .
18
2.5.1
Class-A power amplifier . . . . . . . . . . . . . . . . . . . . . .
20
2.5.2
Reduced-conduction-angle amplifier: class AB, B and C . . . .
22
Harmonic output termination: tuned load . . . . . . . . . . . .
24
Class-E power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . .
27
2.6.1
Capacitance and switching losses . . . . . . . . . . . . . . . . .
28
2.6.2
Class-E operation analysis . . . . . . . . . . . . . . . . . . . . .
30
2.7
Class-F power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . .
38
2.8
Actual figures of merit and efficiency - linearity challenge . . . . . . .
41
2.9
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
2.5
2.6
3 RF devices for power amplifiers
47
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
3.2
General concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
3.2.1
Two-port network and stability condition . . . . . . . . . . . .
50
3.2.2
Two-port power gain . . . . . . . . . . . . . . . . . . . . . . . .
51
3.2.3
Maximum frequency of oscillation and cut-off frequency . . . .
52
3.2.4
Bandgap and breakdown effect . . . . . . . . . . . . . . . . . .
54
GaAs technology and devices . . . . . . . . . . . . . . . . . . . . . . .
56
3.3.1
MESFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
3.3.2
HEMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
pHEMT, mHEMT and power HEMT . . . . . . . . . . . . . .
59
Silicon-based technology and devices . . . . . . . . . . . . . . . . . . .
60
3.4.1
Si MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
3.4.2
DMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
3.3
3.4
Contents
VDMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
LDMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
SiGe HBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
3.5
GaN technology and devices . . . . . . . . . . . . . . . . . . . . . . . .
70
3.6
Technologies and applications . . . . . . . . . . . . . . . . . . . . . . .
74
3.7
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
3.4.3
4 High efficiency RF power amplifier
79
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
4.2
From lumped components to transmission line class-E power amplifier
79
4.2.1
Transmission line-based class-E power amplifier . . . . . . . . .
82
4.3
2 GHz SiGe class-E amplifier . . . . . . . . . . . . . . . . . . . . . . .
84
4.4
X-band GaAs class-E power amplifier . . . . . . . . . . . . . . . . . .
88
4.5
2.4 GHz GaN class-E power amplifier . . . . . . . . . . . . . . . . . . .
93
4.6
Class-E with non-linear capacitance . . . . . . . . . . . . . . . . . . .
96
4.7
Harmonic orthogonality analysis of class-E amplifiers . . . . . . . . . . 102
4.8
4.9
4.7.1
Class-E with linear shunt capacitance . . . . . . . . . . . . . . 105
4.7.2
Class-E with non-linear shunt capacitance . . . . . . . . . . . . 106
Linearity of class-E power amplifier and EER technique . . . . . . . . 110

4.8.1
Class-E amplifier linearity . . . . . . . . . . . . . . . . . . . . . 110
4.8.2
Class-E amplifier linearity in EER configuration . . . . . . . . 112
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5 GaAs HEMT device modeling
115
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.2
Basic concepts: measurements, calibration and deembedding
5.3
Test structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
xi
. . . . . 116
Contents
5.4
5.5
5.6
5.3.1
Test fixture for packaged SiGe BFP620 . . . . . . . . . . . . . 120
5.3.2
Test fixture for bare-die GaAs FPD750
. . . . . . . . . . . . . 123
Small signal modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5.4.1
Equivalent circuit of extrinsic network . . . . . . . . . . . . . . 125
5.4.2
Four-port representation of extrinsic network . . . . . . . . . . 133
5.4.3
De-embedding and extraction of device intrinsic parameters . . 139
Large-signal modeling using empirical Angelov FET model
. . . . . . 144
5.5.1
Angelovs drain current expression . . . . . . . . . . . . . . . . 144
5.5.2
Angelovs capacitance expressions
5.5.3
Add-on parameters and power performance . . . . . . . . . . . 151
. . . . . . . . . . . . . . . . 148
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6 WiMAX RF power amplifier
155
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.2
WiMAX standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

6.2.1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.2.2
IEEE 802.16-2004, fixed wireless access . . . . . . . . . . . . . 158

Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Medium access layer . . . . . . . . . . . . . . . . . . . . . . . . 159
6.2.3
IEEE 802.16e-2005, mobile wireless access . . . . . . . . . . . . 159

Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Medium access layer . . . . . . . . . . . . . . . . . . . . . . . . 160
6.2.4
WiMAX transmitter . . . . . . . . . . . . . . . . . . . . . . . . 160

Power classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.2.5
6.3
WiMAX OFDM PAPR and CCDF . . . . . . . . . . . . . . . . 162
WiMAX class-AB and class-E power amplifier design using equivalent

capacitance concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
xii
Contents
6.3.1
Simplified models and legacy design procedures for class-AB

and class-E amplifiers . . . . . . . . . . . . . . . . . . . . . . . 165
Class-AB amplifier and device-current model . . . . . . . . . . 165
Class-E amplifier and switch model . . . . . . . . . . . . . . . . 166
6.4
6.3.2
Equivalent capacitance for class-AB and class-E power amplifier

modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.3.3
3.5 GHz class-AB and class-E power amplifier design . . . . . . 170
Doherty power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 175

6.4.1
Basic theory
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.4.2
Generalization of two-stage Doherty amplifier . . . . . . . . . . 179
6.4.3
Asymmetric power divider for device size compensation . . . . 182
6.4.4
Doherty technique using built-in amplifiers . . . . . . . . . . . 184
6.4.5
Inverted Doherty power amplifier . . . . . . . . . . . . . . . . . 185
6.4.6
Three-stage Doherty amplifier . . . . . . . . . . . . . . . . . . . 187
6.4.7
Design of two-stage and three-stage Doherty amplifiers . . . . . 189

Two-stage Doherty amplifier . . . . . . . . . . . . . . . . . . . . 189
Three-stage Doherty amplifier . . . . . . . . . . . . . . . . . . . 193
Stability loop condition, Rollets proviso . . . . . . . . . . . . . 195
6.4.8
Performance and WiMAX compliance . . . . . . . . . . . . . . 198

AM-AM and AM-PM response of Doherty amplifier . . . . . . 204
State of the art of 3.5 GHz WiMAX power amplifiers
6.4.9
. . . . . 204
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7 Conclusions
207
List of publications
229
Curriculum vitae
231
xiii
List of acronyms
2DEG
Two Dimensional Electron Gas
ACPR
Adjacent Channel Power Ratio
BiCMOS
Bipolar CMOS
BJT
Bipolar Junction Transistor
CCDF
Complementary Cumulative Distribution Function
CMOS
Complementary Metal Oxide Semiconductor
CPW
Coplanar Waveguide
CW
Continuous Wave
DMOS
Double Diffused MOSFET
DPA
Doherty Power Amplifier
EER
Envelope Elimination and Restoration
EM
Electromagnetic
EVM
Error Vector Magnitude
FoM
Figure of Merit
GaAs
Gallium Arsenide
GaN
Gallium Nitride
HBT
Heterojunction Bipolar Transistor
HD
Harmonic Distortion
HEMT
High Electron Mobility Transistor
IMD
InterModulation Distortion
xv
List of acronyms
InP
Indium Phosphide
ISI
Intersymbolic Interference
LDMOS
Lateral DMOS
LM
lattice-matched
LOS
Line-of-Sight
MESFET
Metal Epitaxial Semiconductor Field Effect Transistor
mHEMT
metamorphic HEMT
MMIC
Monolithic Microwave Integrated Circuit
MOSFET
Metal Oxide Semiconductor Field Effect Transistor
OFDM
Orthogonal Frequency Division Multiplexing
P1dB
Power at 1-dB compression point
PA
Power Amplifier
PAE
Power Added Efficiency
PAPR
Peak to Average Power Ratio
pdf
probability density function
pHEMT
pseudomorphic HEMT
RF
Radio Frequency
SiC
Silicon Carbide
SiGe
Silicon Germanium
SOLT
Short Open Load Thru
TRL
Thru Reflect Line
VDMOS
vertical DMOS
WiMAX
Worldwide Interoperability for Microwave Access
ZDVS
Zero Derivative Voltage Switching
ZVS
Zero Voltage Switching
xvi
List of symbols
Symbol
description
Cds
intrinsic drain-source capacitance
Cgd
intrinsic gate-drain capacitance
Cgs
intrinsic gate-source capacitance
Cjo
zero-voltage junction capacitance
Cpds
extrinsic drain-source capacitance
Cpgd
extrinsic gate-drain capacitance
Cpgs
extrinsic gate-source capacitance
Cout
output capacitance
C band
4-8 GHz frequency band
stability measure
EB
breakdown electric field
Ec
lowest conduction band energy
EF
Fermi energy level
Eg
bandgap energy
Ev
highest valence band energy
f
fmax
frequency
maximum frequency of oscillation
fT
cut-off frequency
amplifier gain
gm
intrinsic transconductance
IDS
drain-source current
xvii
List of symbols
Symbol
description
IDD
DC drain current
iDS
instantaneous total drain-source current
iRF
instantaneous radio-frequency current
iS
instantaneous switch current
Rollett stability factor
K band
Ka band
Ku band
IQ
quiescent current
Ldp
extrinsic drain inductance
Lgp
extrinsic gate inductance
Lsp
extrinsic source inductance
n+
drain efficiency
highly doped n-layer
PDC
DC power
Pdiss
dissipated power
Pin
RF input power
Pout
RF output power
electrical charge
Rdp
extrinsic drain resistance
Rgp
extrinsic gate resistance
Rsp
extrinsic source resistance
RL
resistive load
Ropt
optimal resistive load
S band
geometrically derived stability factor
unilateral power gain
Vbi
built-in voltage
VDS
drain-source voltage
xviii
List of symbols
Symbol
description
VDD
DC drain voltage
vDS
instantaneous total drain-source voltage
VGS
gate-source voltage
VGG
DC gate voltage
Vp0
pinch-off voltage
vS
instantaneous switch voltage
angular frequency
W band
X band
XL
reactive load
Yij
admittance parameter at port i from port j
Zij
impedance parameter at port i from port j
Zopt
optimal impedance for class-E operation
xix
Chapter 1
General introduction
1.1
Introduction and motivation
Energy-saving technologies have been developing intensively and rapidly in the last
decades, pushed mainly by the need to reduce CO2 emission and therefore global
warming (see Fig. 1.1). The latter is becoming more and more plausible each day,
raising an unprecedented attention by the main world economies. Simultaneously, for
the same reason, major efforts have been undertaken to replace fossils fuel as primary
source of energy. Renewable energy mechanisms such as solar panels, wind turbines,
biomass, biofuels and geothermal centrals are being revitalized and deployed worldwide for this purpose. On the other hand, energy-saving technology is being applied
on daily appliances and commodities (see Fig. 1.2). The energy consumption of these
summed over million units and over months is responsible of an appreciable part of the
dioxide emission. Hence, electrical artifacts such as dishwashers, photocopiers, TVs
and light bulbs are being technological enhanced to reduce their energy consumption
to the minimum. In the particular case of lighting, there has been an important transition from the very inefficient incandescent bulb to more compact fluorescents, and
even these are being expected to be replaced by more efficient LEDs, although there
are still technical issues to be solved [1].
In the telecommunications arena, this energy-saving trend has been already in the
field due to the mobility requirement of nowadays communications. Portables devices
such as GSM, PDA, laptops depend only on the energy provided by a lithium-ion
battery, and therefore their consumption should be smartly administered among all
the electronics components, likewise, their energy consumption should be minimized.
One well-known, but effective way to reduce the consumption is by reducing the supply voltage, because the power consumption depends approximately on the square of
this value. Recently a technology with 0.3 V supply voltage has been reported, which
1
1.1. Introduction and motivation
Figure 1.1: Global warming and temperature rise
can be ten times more efficient than the current technology [2]. However, this and
other improvements only refer to the digital electronics or base-band processing of
the terminal. The consumption of the analog or RF electronics can not be optimized
in this straightforward manner. On the other hand, among all the RF components,
the power amplifier is the one which draws the highest power as it consumes about
40 percent of the overall power budget. Therefore, an increase of its power efficiency
would extend the battery life of the handset considerably. An improvement of the
power amplifier efficiency is not only vital in the mobile terminal, but also in the cellular base station. In this last scenery, the economy cost and consumption of electricity
could be extremely high together with the air pollution and carbon emissions from
the electricity generating stations necessary for their operation. Some figures found
in [3] estimate that a fully-loaded 3G cell utilizing legacy power amplifier technology
may consume about 3 kW of power, which gives a cost of 1600 US dollar of electricity
per year in US, or 2300 Euro in Europe. A European operator with a network of 20
000 base stations would draw about 60 MW, giving an electricity cost per year of 46
million of Euro, and a carbon footprint around 220 000 tons of CO2 per year.
Another characteristic of the Telecommunications, at present, is the variety of services that this should support. Besides the legacy telephony, internet and multimedia
services should be supported as well. This results in high speed digital data which
should be transported over a particular channel. Normally these channels (copper
cable and wireless channels) are bandwidth limited and the transmission conditions
are severe, for instance multipath fading in radio channels (see Fig. 1.3a). Under this
context, orthogonal frequency-division multiplexing (OFDM) technique has arisen as
a robust method to deal with these conditions. In this technique, the high speed
data are split into several slower data flows, each of these are modulated using a
specific sub-carrier. The particularity of OFDM is that these sub-carriers are orthogonal among each other which allows an overlapping of the spectrum of the contiguous
sub-carriers without causing interference with each other. The interference of each
sub-carrier is null exactly at any of the sub-carrier frequencies (see Fig. 1.3b). This
2
1.1. Introduction and motivation
Figure 1.2: Differents aspects of saving energy and reducing CO2 emission
avoids the use of guard band, which also brings up an increase of the channel capacity. The slow data sub-carriers have an associated long time separation between
symbols, which makes them less vulnerable to inter symbolic interference (ISI) occurring under multipath propagation conditions. On the contrary, the complete OFDM
signal is prone to suffer of ISI due to the shorter time interval. Hence, normally some
symbols of the OFDM stream are used as guard times. At the end, the number of
advantages of OFDM prevails over its disadvantages and it is used in most of the
modern telecommunications standards. Hence, OFDM can be found in ADSL on
POTS copper wires, Wireless LAN standards 802.11a, g, digital TV DVB-T, mobile
TV DVB-H, and Wireless MAN 802.16 (WiMAX).
Despite its broad range of applications, OFDM signals still represent a challenge to
the RF amplifier designer. In the time domain (see Fig. 1.3c), this OFDM signal
exhibits high peak amplitudes, which are rare, but they should be amplified with the
same fidelity as the most frequent low amplitudes. Statistically, it is found that this
signal presents a high peak to average power ratio (PAPR), which would be around
10 dB. This would demand a linear amplifier that should be operated 10 dB backoff
from its 1-dB compression point (P1dB) in order to amplify linearly all the signal
amplitudes. Evidently, this is detrimental for the power efficiency, since the typical
efficiency of 40-70% at P1dB could be reduced to values lower than 5% at 10 dB backoff. As a result, applications with OFDM signals would show poor battery life (in
the mobile terminal) or high electrical power consumption (in the base station) with
all the negative consequences above mentioned. Hence, the challenge is to provide an
amplifier that works linearly over this 10 dB of PAPR and still keeps moderate/high
efficiency over this range. Several techniques are under research to tackle this prob3
1.2. Scope of the research work
Figure 1.3: Multipath propagation (a) and OFDM in frequency (b) and time domain (c)
lem. These techniques can be classified as efficiency oriented techniques and linearity
oriented techniques. Examples of the first sort of techniques are predistortion, feedforward and feedback techniques, which mainly correct the inherent distortion of the
amplifier by providing an inversion function of the amplifier or by comparison with
the original input signal. Examples of the second type of techniques are dynamic
biasing, dynamic load and Envelope Elimination and Restoration (EER), which basically vary the bias or load of the amplifier according to the input signal. However
one sole technique may not be sufficient to achieve the target and a combination of
these may become the ultimate solution.
1.2
Scope of the research work
This research comprises several aspects involved in the area of RF power amplifiers
under the scenery described above. However, the main goal will be to design amplifiers capable of operating with acceptable linearity and efficiency simultaneously. The
linearity figures of merit (FoM) should comply with the requirements of an OFDM
application. For this research WiMAX 802.16e is selected due to its important relevance nowadays. The efficiency range should be kept moderate/high over a range of
10 dB.
State-of-the-art technologies and devices will be reviewed, as well as their applicability
4
1.3. Chapter descriptions

for RF power amplifiers. Si technology is a very attractive choice due to its relatively
low cost and continuous improvement in cut-off frequency (fT ). The convenience of
this technology for RF amplifiers will be studied. Likewise, the relatively brand-new
GaN technology will be examined. This technology exhibits astonishing breakdown
voltages with very high cut-off frequency, and it is seen as a potential candidate to
compete with de-facto technologies such as Si LDMOS and GaAs.
Once a specific device or technology is selected, the next step is to see if there is a
reliable device model for this device. Normally, the device model provided by the
manufacturer is not accurate enough in the non-linear regime or alternatively only
DC and S-parameter measurements are provided. Therefore, all the steps involved in
the construction of a non-linear model will be studied.
Finally, RF power amplifier design methodologies will be reviewed and applied. Classical linear amplifier and high efficient amplifier aspects will be covered. The high
efficient class-E power amplifier will be studied in depth, due to its relevance in the
EER amplifier system. Additionally, Doherty efficiency-enhancement technique will
be assessed and implemented. A final evaluation of its linearity and efficiency performance, under WiMAX signals, will be realized at the end.
1.3
Chapter descriptions
This thesis book is structured in seven chapters, including the introduction. The
contents from chapters two to seven will be described next.
In chapter two, fundamental concepts of RF power amplifiers will be introduced. The
load line concept as well as classic FoM of an amplifier will be described. A theoretical
revision from class A to class F amplifiers will be presented. Likewise, a brief revision
of advanced techniques to comply with linearity and efficiency requirements will be
realized. Simultaneously, the average efficiency concept will be presented. This will
help to ponder the actual efficiency of legacy amplifier configurations.
In chapter three, technological facets of devices that are candidates for RF amplifiers
will be reviewed. This chapter will start with a description of device-related FoM
such as cut-off frequency (fT ) and breakdown electrical field. Then, the status quo
of the prime RF technology, which is GaAs, will be reported. HEMT devices will be
mainly described. The cost-effective Si technology will be covered next. Si MOSFET,
LDMOS and SiGe HBT will be studied and their applicability to RF power amplifiers
will be reviewed. Finally, the emerging GaN technology will be studied. Its physical
principle and technological issues will be covered. Additionally, a brief assessment of
all these technology alternatives from the application perspective will be realized at
the end of this chapter.
Chapter four is dedicated to the high efficiency class-E power amplifier. The evolu5
1.3. Chapter descriptions

tion from the original lumped-component implementation to the configuration based
on distributed elements will be developed. The latter topology is the one that is
applicable in the microwave range of frequencies. Three types of technologies have
been utilized in the design of this type of amplifier. These designs will be described
in this chapter. A first class-E amplifier implemented as a hybrid circuit at 2 GHz
utilizes a packaged SiGe HBT. Next, MMIC GaAs technology is utilized to design
a second class-E amplifier at X-band. Finally, a third class-E amplifier at 2.4 GHz
employed a GaN HEMT bare-die device. Additionally, a theoretical analysis of the
class-E amplifier considering linear and non-linear capacitances is performed. The
concept of Harmonic Orthogonality is utilized for this last study.
Chapter five covers different aspects for developing a non-linear device model. The
modeling procedure, developed in this chapter, is applied to a GaAs HEMT bare-die
device. Initial considerations to construct an adequate test fixture as well as calibration and de-embedding concepts are presented at the onset of this chapter. Two different approaches to de-embed device S-parameters are described. These de-embedding
techniques are based on equivalent circuit and four-port network representation. The
intrinsic device parameters are extracted from the de-embedded S-parameters. These
parameters along with the DC IV characteristics are used to construct the non-linear
model. Angelov equations are used for the formulation of the non-linear currents
and capacitances. Basic guidelines about how to obtain first-values of Angelov model
parameters are described. This chapter concludes with recommendations regarding
the final tuning of the non-linear model.
Chapter six starts with a description of the WiMAX technology, its application sceneries and its two standards. The probability distribution (CCDF) and PAPR are reviewed for this particular application. After this introduction, the model developed in
chapter five is employed to design a class-AB and class-E amplifier for WiMAX at 3.5
GHz. The concept of equivalent capacitance is introduced in this part of the chapter.
Initial linearity performance is realized on these two amplifiers. Actually, these amplifiers were built to be used in Doherty and EER amplifier configurations. From these
two configurations, Doherty amplifier was developed in this thesis to comply with the
final goal of the thesis. Two designs based on two and three-stage Doherty amplifier
are described. Finally, an evaluation and comparison of the class-AB amplifier and
the two-stage Doherty amplifier is realized using WiMAX OFDM signals. Measurements and simulation outcomes demonstrate that the Doherty amplifier outperforms
the legacy class-AB in terms of linearity and efficiency.
In Chapter 7, the final conclusions are drawn as well as final aspects and hereafter
investigation is explored.
Chapter 2
RF power amplifier basics

2.1
Introduction
In this chapter, basic concepts on power amplifiers will be introduced. A special

emphasis on differentiating power amplifiers from conventional small-signal amplifiers
will be necessary in order to understand the specific requirements for this type of
circuit.
Unlike in the small-signal case, the load line is a very important concept for power
amplifiers. It describes the large signal regime of the transistor. However the load
line does not define exclusively the type of amplifier, because this can be influenced
by the dynamic behavior of the device. Hence, what might seem a class AB power
amplifier could also have the characteristic of a class-E or class-F power amplifier.
In order to ponder on the different types of amplifiers, figures of merit have to be defined. This will give an idea of the benefits or disadvantages of applying a specific type
of amplifier. Conventionally, it is stated that low-efficiency linear amplifiers (classA, class-AB) are convenient for non-constant-envelope signals while high-efficiency
non-linear amplifiers (class-E, class-F) are for constant-envelope signals. Nevertheless, current and advent mobile applications simultaneously demand high efficiency
and linearity. These antagonist requirements have led to the development of add-on
solutions which involve the utilization of linearizers and/or efficiency-enhancement
techniques. The effectiveness and feasibility of these techniques are under research
nowadays. A brief description of this cornerstone will be presented at the end of this
chapter.
2.2. Basic RF amplifier characteristics
Figure 2.1: General block diagram of a single stage RF amplifier
2.2
Basic RF amplifier characteristics
In order to start the description and characterization of RF power amplifiers, a general

configuration of a single-stage RF amplifier is presented in Fig. 2.1. This conventional
circuit is applicable either for small or large-signal (power) amplifiers. It comprises
an input matching network, the active device, and the output matching network.
Matching networks are designed in order to make the device behave in an optimal
way according to a specific goal. As an example, these matching networks can be
tailored in order to make the device capable of amplifying extremely small signals
with very low noise at the output (low noise amplifier), or they can be tailored such
that a maximum gain is realized, or they can be tailored such that the device is
driven over its maximum rating, and therefore maximum output power is obtained
(power amplifier). This matching network can be implemented physically by using
lumped components, distributed elements (transmission lines) or a combination of
both, depending on the application and/or range of frequencies. From the point of
view of modeling, these matching networks, which comprise passive elements only, are
basically characterized by intrinsic linear elements, and therefore they are considered
to be linear (and time invariant) networks per se.
Unlike the matching networks, the active device can be characterized as either a linear
or non-linear network, depending on the electrical power range of the signals involved
in the process. If the power level of the input signal is very small (see Fig. 2.2 case
A), such that device characteristic and output approach respectively a linear system
and linear output, i.e., when superposition and scaling properties are fulfilled [4],
then the device can be modeled in terms of two-port S- parameters. This is the
general approach used in low noise amplifiers and high-gain small-signal amplifiers.
This S-parameter description is only valid under a specific bias point and does not
conceptually depend on the level of the input signal. The linear concept can be stated
from the frequency viewpoint as well. If the number of harmonic components at the
output is the same as at the input, i.e., there is no harmonic generation, then the
system is linear.
2.3. Load line
Figure 2.2: Linear and non-linear behaviour of amplifier
Contrary to the small signal approach, under large signal levels operation, the timedomain waveform at the output shows some distortion with respect to the input
signal (as illustrated in Fig. 2.2 case B). Very complex models intended to represent
the non-linear characteristics of the active devices or amplifiers are necessary. From
the frequency viewpoint, this means that besides the harmonic components of the
exciting signal, additional harmonic components are generated due to the device or
amplifier non-linearity. In chapter 5, a methodology to construct a last-generation
non-linear model will be described.
Since the aim of the thesis is oriented mainly to power amplifiers, very basic - but
important - concepts related to them will be presented next. These concepts are load
line and power amplifier figures of merit.
2.3
Load line
The concept of a load line is tightly linked to power amplifiers, since it gives a clear
representation of the capabilities of a device for maximum output power application.
It represents the trajectory of all the instantaneous values of current (iDS ) and voltage
(vDS ) of a device when this one is operated under a specific load and at a given
bias point. Furthermore, plotting the load line can help to visualize and optimize
the amplifier for maximum efficiency, or alternatively for minimum thermal power
dissipation.
In Fig. 2.3 a basic amplifier schematic is presented, which will help to state the basic
equation of a load line. This amplifier is biased through an RF choke inductor LCH
with a bias voltage VDD and drain bias current IDD . The DC blocking capacitor Co
will hold a steady-state voltage VDD considering that the output voltage vo swings
low and the capacitance value is large enough to maintain the voltage VDD during
the entire RF cycle.
9
2.3. Load line
Figure 2.3: Basic amplifier circuit for load line definition
In steady state the following equations can be established for this basic amplifier
vDS = VDD + vo
(2.1)
IDD = iDS + io
(2.2)
where the values of the variables correspond to the DC plus AC components, for
instance vDS corresponds to the total drain-source DC voltage plus AC voltage.
Additionally at the output of the circuit, the load impedance can be used to relate vo
and io
ZL =
vo
io
(2.3)
Combining the three latter formulas, a relationship between iDS and vDS can be
established
iDS = IDD
vDS VDD
ZL
(2.4)
This last equation defines precisely the load line of a device given a specific bias point
(IDD , VDD ) and load impedance ZL , i.e., it defines the trajectory of all the combination of values (iDS ,vDS ) of the device under specific operating condition. When
10
2.3. Load line
Figure 2.4: Amplifier load line (solid line: resistive load, dashed line: complex load)
the value of the impedance ZL is a real value RL , the equation (2.24) becomes the
equation of a straight line with a slope 1/RL . If vDS is assumed to be the independent variable in the equation (2.4), then vDS could take any value and therefore could
produce any unlimited value for iDS . Nevertheless this is not possible due to the real
physical limitation of the device, which can be visualized in the DC IV characteristics
of the device. That is the reason why the load line is always presented on a DC IV
plot, as a way to confine the load line excursion inside the physical maximum rating
of the device. There are basically four figures that limit the excursion of the load
line: the knee voltage (minimum vDS ), the breakdown voltage (maximum vDS ), zero
value current (minimum iDS ) and the device maximum current (maximum iDS ). An
example of a load line with real load impedance can be observed as the solid line in
Fig. 2.4.
It is also very important to remark that when the load is complex, equation (2.4)
becomes the equation of a shifted and rotated ellipse [5], as can be also seen in
Fig. 2.4. From this it can be established that by observing the load line we can
deduce if the transistor is driven by a real load or a complex load. Nevertheless, if
an RF transistor is terminated only with a 50 load, without matching circuit, the
intrinsic load line observed will be an ellipse instead of a straight line, which is due
to the effect of the intrinsic output capacitance of the device that combines with the
real 50 impedance into a complex load. Furthermore, these load line traces serve
as a technique to know when the device output capacitance is canceled out by the
matching circuit and the intrinsic device only sees a purely real load at its terminals.
11
2.4. Figures of merit
Figure 2.5: Power components flowing in an amplifier
2.4
Figures of merit
In order to evaluate how well an RF power amplifier performs for a particular application, it is necessary to establish figures of merit. The values of these figures of
merit are the reference values for comparison with other amplifiers using other design
techniques or technologies. For the purpose of this thesis, figures of merit related to
efficiency and linearity will be described next.
2.4.1
Drain efficiency and power added efficiency
In order to describe the two basic figures of merit drain efficiency and power added
efficiency a scheme with the power flow in an amplifier is presented in Fig. 2.5.
In this figure, four main power components can be defined:
Input power (Pin ), which is the power flowing into the amplifier input, over a determined frequency range or bandwidth. For initial testing purposes, this input power
could be concentrated into a single frequency component (the fundamental).
Output power (Pout ), is the power flowing out of the amplifier over a determined
frequency range or bandwidth. If the input power is only contained in one harmonic
component (the fundamental), the output power corresponds to the power measured
at the fundamental frequency, as well.
Harmonic output power (Phout ), corresponds to the power of the harmonic compo12

nents, different from the fundamental, presented at the output of the amplifier, due
to the non-linear characteristics of the latter. This is testable when the excitation
signal is at the fundamental frequency.
DC power (PDC ), corresponds to the DC power drawn from the power supply during
amplifier operation. This value can be calculated or measured as the constant bias
voltage multiplied by the average DC current at both drain and gate terminals (in
case of FETs).
Dissipated power (Pdiss ), is the power dissipated in the device as a heat. It is wasted
power and has to be minimized.
Dissipated power at gate (Pdiss,G ), is the power dissipated at the gate.
Additionally, based on these definitions, the power balance equation of the amplifier
can be established
Pin + PDC = Pout + Phout + Pdiss + Pdiss,G
(2.5)
This relationship will be used later on for an efficiency-enhancement technique.

Given all the previous definitions, the two most used efficiency measures are now
defined.
Drain Efficiency is defined as the amplifier output power Pout divided by the DC
power consumption PDC
Pout
PDC
(2.6)
Power Added Efficiency (PAE)is defined as the (RF) power added by the amplifier
(Pout -Pin ) divided by the DC power consumption PDC
Pout
Pout Pin
=
P AE =
PDC
PDC

1
1
1
= 1
G
G
(2.7)
This last definition carries more information than the previous one, since it also
depends on the gain of the amplifier (Pout =GPin ). While the drain efficiency increases
monotonically with the input power, the PAE reaches a maximum and then its value
decreases till zero, and it could even have a negative value.
On the other hand, a one-stage amplifier is usually not enough to fulfill the output power and gain requirements for wireless applications; and therefore multistage
amplification systems are necessary. In the case of a two-stage amplifier, the total
efficiency can be calculated as [6]:
13
Figure 2.6: Harmonic output power and second and third order intercept point
T otal =
1
1 G 2
1
+
1
2
(2.8)
where 1 and 2 are the drain efficiency values of the first and second stage, and G2
is the gain of the second stage. From equation (2.8) it can be concluded that the
efficiency of the last stage (second stage in this case) is the one that dominates the
total efficiency. That is the reason why it is very important to have a very highefficiency type of amplifier for the last stage, which also determines the maximum
output power.
2.4.2
Harmonic distortion and intermodulation distortion
As it was briefly described in section 2.2, a power amplifier is a non-linear system that
generates harmonic components besides the frequency corresponding to the excitation
signal, when it is operated under large-signal regime.
14

There are two basic figures of merit to quantify how large the distortion is associated
to these harmonic components, namely harmonic distortion and intermodulation distortion.
Harmonic distortion
This distortion is calculated or measured when the amplifier is excited with a singletone test signal, and when harmonic distortion components are generated at the
output (see Fig. 2.2). Since the second and third harmonic components are normally
the largest ones, distortion figures associated to these are defined as follows:

HD2,dBc = 10log
Pout (2f0 )
Pout (f0 )

HD3,dBc = 10log
Pout (3f0 )
Pout (f0 )

(2.9)
These figures are expressed in dBc or decibel relative to the power at the fundamental
frequency. As it can be observed in Fig. 2.6, the power level of the harmonics changes
with the input power. Therefore their harmonic distortion figures in dBc change as
well.
When all the distortion components are to be included in a single figure of merit,
then the total harmonic distortion (THD) is defined
P
Pout (nf0 )
n2
T HDdBc = 10log10
Pout (f0 )
(2.10)
Alternatively to the above-mentioned definitions, there exist the Intercept Point

figures. For low to medium distortion level, it can be established based on Taylor
series that the second harmonics amplitude depends on the square of the input signal
amplitude, the third harmonic depends on the cube of the input amplitude, and so
forth. Then, their corresponding power slope in logarithmic scale is proportional to
the order of the harmonic component (see Fig. 2.6). If these harmonic distortion
lines are extrapolated, they intersect the prolongation of the line corresponding to
the fundamental output power at the nth order intercept point (IPn). The larger
these numbers, the smaller is the distortion. The advantage of these figures of merit
is that they do not depend on the input power.
Intermodulation distortion
A slightly more realistic approach for the actual wireless scenery is to consider the
output of an amplifier when it is excited by two tones. These two tones will produce at
the output different frequency components (intermodulation products, see Fig. 2.7).
15
Figure 2.7: Intermodulation distortion and third order intermodulation intercept point
From all the intermodulation products (IMD) observed at the output, the ones closest
to the exciting signal frequencies are the most relevant, since they will be inside the
bandwidth of the system. These products correspond to the third order intermodulation products (IM D3 ), which numerically correspond to the frequencies 2f2 f1
and 2f1 f2 , given that the difference between f1 and f2 is small. Additionally, it
is assumed for testing and modeling that low to medium input power excitations are
used (weakly non-linear behavior) and that the two tones have the same amplitude.
Under the above-mentioned assumptions IM D3 can be calculated using

IM D3,dBc = 10log10
Pout (2f2 f1 )
Pout (f2 )

10log10
Pout (2f1 f2 )
Pout (f1 )

(2.11)
The two definitions are equal when there is not long-term memory effect. Like in
the case of harmonic distortion analysis, an intercept point can also be determined
as shown in Fig. 2.7. Likewise, for weak non-linearity, the slope of the IM D3 in
logarithmic scale is in the order of three.
This figure of merit will provide more realistic numbers about the distortion performance of the amplifier. Nevertheless this could be insufficient, when strong linearity is
required and complex digital modulated signals are involved. Then, figures of merit
16
Figure 2.8: Adjacent channel power ratio definition
such as Adjacent Channel Power Rejection (ACPR) and Error Vector Magnitude
(EVM) are better distortion figures and should be used instead of HD or IM D3 .
2.4.3
Adjacent channel power ratio
The transmission of the information over a particular channel should be confined

within the assigned bandwidth to this channel. Nevertheless, the non-linear characteristic of the amplifier causes intermodulation distortion, which spread over the
adjacent channels (spectral regrowth). This leaked power is defined as adjacent channel leakage (ACL) or adjacent channel power (ACP). Therefore the adjacent channel
power ratio (ACPR, ACLR) can be determined as the ratio of the power leaking into
the adjacent channel compared to the power in the main channel [7, 8],
R
ACP R[dBc] = 10 log
adj
R
ch
P SD() d
P SD() d
!
(2.12)
where adj and ch specifies the frequency bands of the adjacent and the main channel
(see Fig. 2.8), and P SD() is the power spectral density of the amplified signal. The
adjacent channel is centered at a frequency offset (of f ) from the main channel. The
values of the different s are determined by the specific wireless standard.
Alternatively, a spectral mask can be utilized to ponder nonlinearities and spectral
regrowth. The spectral mask defines the limits of the signal spectrum within a specific
frequency range. Unlike ACPR, it is not necessary to integrate the power over the
adjacent channel. The dimension of the mask is specified by the wireless standard.
17
2.5. Class of amplifiers: from class-A to class-C
Figure 2.9: Error Vector definition (a), reference and received data constellation for a 64
QAM signal (b)
2.4.4
Error vector magnitude
While ACPR is meant to measure the out-of-band distortion, the Error Vector Magnitude (EVM) is to assess the in-band distortion caused by the amplifier non-linearities.
Given a digital modulation constellation, the error between the original constellation
vector and the measured one is the error vector magnitude [7] (see Fig. 2.9a). This
value is averaged over a determined number of transmitted symbols. The normalized
rms value of the EVM can be defined as [8]:
EV MRM S
v
u P
2
u
|S Rk |
u kK k
=u
P
t
2
|Rk |
(2.13)
kK
where Sk is the received (measured) vector, Rk is the reference or original symbol

vector and K is the total number of symbols. An example of a constellation, showing
the received and reference symbols for a 64QAM constellation, is reported in Fig. 2.9b.
2.5
Class of amplifiers: from class-A to class-C
Given the device DC characteristics, a first bias point used in power amplifier is the
one in the middle of the DC characteristics, which is known as a class A bias point
(see Fig. 2.10). This bias condition ( Imax
2 , VDD ) ensures plenty of room for the output
signal excursion, and therefore the probability of reaching the cut-off and saturation
regions, which cause distortion, is small.
It is important to remark that this bias point is also widely used in small-signal
applications. What makes the difference between large signal (power) amplifier and
18
Figure 2.10: Load lines for different loading conditions
small-signal amplifier is the range of the signal excursion and the capabilities to reach
the limits of the device. In order to illustrate this, a simple small-signal model of the
output of a device is presented in Fig. 2.11. In small-signal scenery, a first criterion to
terminate the device properly is to use the complex conjugate of the output impedance
of the device. This implies to present a load, which inductive part cancels the effect of
Cds , and which real part is equal to 1/gds . Under this condition the load line observed
will be the one indicated in Fig. 2.10, case A1. As can be seen, this implies a reduced
current excursion, less than the available maximum device current. Likewise, if a
load is chosen with a smaller resistance, the load line is the one indicated as A.2 in
Fig. 2.10. In this case a reduced voltage excursion is obtained as compared to the
maximum voltage rating. Therefore maximum output power is not reached. In order
to reach the maximum output power of the device, a load line like the one marked
A3 in Fig. 2.10 must be obtained. The latter means to use a load, which real part is
only determined by the maximum ratings of the device
RoptclassA =
Vmax Vknee
2 (VDD Vknee )
=
Imax
Imax
(2.14)
The imaginary part of this load is such that it cancels the equivalent output reactance
of the device.
Nevertheless, this optimal load value, most of the time, will cause a high mismatch
between load and device, and therefore a relatively high output VSWR.
From the above description it is clear that the criterion for designing a class-A power
amplifier is different from the one used for class-A small-signal applications. The goal
19
Figure 2.11: Small signal model of device output
for a power amplifier is to get the maximum power from the device, driving it into its
limits.
2.5.1
Class-A power amplifier
We have already mentioned some characteristics of the class-A amplifier in the above
section, now the study will be completed with the determination of some figures of
merit.
It is clear also from Fig. 2.10 that the bias point for this class of operation is
IDD = IQ =
VDD = VQ = Vknee +
Imax
2
(2.15)
Vmax Vknee
2
(2.16)
Recurring to Fig. 2.3 and equation (2.1) and (2.2), these latter equations can be
re-written to reflect the device class-A operation under a sinusoidal input signal
iDS (t) = IQ + Iac = IQ + Iout cos(t)
vDS (t) = VQ + Vac (t) = VQ + Ropt Iac (t) = VQ + Iout Ropt cos(t)
(2.17)
(2.18)
where iD (t) and vD (t) correspond to the DC plus AC component of the drain current
and voltage respectively.
20

These equations are valid as far as the reactive part of the device is cancelled out by
the imaginary part of the optimal load.
These equations help us to determine the power and efficiency figures
PDCclassA
1
=
T
1
vDS (t)dt
T
VDD Imax
iDS (t)dt = VQ IQ =
2
(2.19)
Pout =
2
Ropt
Iout
2
2
Ropt
Iout
2IQ VQ
(2.20)
(2.21)
where T is the period of the sinusoidal signal.

These equations tell us that power and efficiency of this amplifier increase with the
square of the output current Iout and that the DC consumption is constant, irrespective of the output current. When this current Iout turns into its maximum value
(Imax /2), then the maximum and typical values are obtained
PoutclassA =
Imax (Vmax Vknee )

Imax (VDD Vknee )
(Imax /2)2 Ropt
=
=
(2.22)
2
8
4
classA =
(Imax /2)2 Ropt

Vmax Vknee
VDD Vknee
=
=
2IQ VQ
2(Vmax + Vknee )
2 VDD
(2.23)
In case Vknee is sufficiently small to be neglected, then classA reaches the typical
value of 50% of maximum drain efficiency.
The reason of the low efficiency figures for this type of amplifier is that it is always
drawing a constant DC power (see equation 2.19), independent of the level of the
output power. Even when there is zero output power, the amplifier is drawing a
constant DC power that is wasted as heat. Therefore, one technique to make this
amplifier more efficient is to reduce the DC power consumption by decreasing the
quiescent current, but keeping the same maximum current and voltage excursion. In
Fig. 2.12, a way to reduce the quiescent current by reducing the conduction angle is
illustrated. This will lead to the next class of amplifiers: class B, AB and C.
21
Figure 2.12: Reduced-conduction-angle amplifier
2.5.2
Reduced-conduction-angle amplifier: class AB, B and C
Mainly intended to get better efficiency numbers, class-AB, -B and -C amplifiers

share the common characteristic that the device current conducts only part of the 360
sinusoidal cycle (see Fig. 2.12). Depending on the conduction angle value, the class-B,
-AB and -C mode are conventionally defined as indicated in table 2.1. The conduction
angle is determined by the quiescent gate voltage (VGSq ), which is a function of the
device pinch-off voltage (Vp0 ) as well as the built-in voltage (Vbi ).
In order to determine the benefits of reducing the conduction angle, initial relationships for drain current can be established based on Fig. 2.12 for the period [,]

iDS () =
IQ + Iout cos(),
0,
0 || < 2 ;
2 || <
Q
where cos(/2) = Iout
, and Iout = Imax IQ
Then, iDS () can be rewritten as

iDS () =
Imax
1cos(/2) (cos
cos(/2)),
0 || < 2 ;
|| <
0,
If Fourier series are defined for iDS (), then the DC current can be calculated as
22

Table 2.1: Reduced-conduction-angle amplifiers figures
Mode
A
AB
B
C
Conduction Angle ()
2
2
1
=
2
IDC
Bias Point (VGSq )

Vp0 +0.5(Vbi Vp0 )
Vp0 +(00.5)(Vbi Vp0 )
Vp0
<Vp0
Quiescent Current (IQ )

0.5Imax
(00.5)Imax
0
0
Imax
(cos cos(/2))d
1 cos(/2)
||<
2
IDC =
Imax 2.sin(/2) .cos(/2)

.
2
1 cos(/2)
(2.24)
and the magnitude of the nth harmonic as

1
In =
Imax
(cos cos(/2))cos(n)d
1 cos(/2)
||<
2
(
In =
Imax sin()
n=1
2 . 1cos(/2) ,
sin(n/2).cos(/2)n.cos(n/2).sin(/2)
2.Imax
,n 2
.n.(n2 1) .
1cos(/2)
(2.25)
The equations (2.24) and (2.25) are used to define the DC and harmonic behavior
of this type of amplifier and are plotted in Fig. 2.13 for clearer reference. As it can
be observed, the DC component decreases monotonically as the conduction angle is
reduced, which means that efficiency will increase. However, the output power will
be lower because the fundamental component becomes smaller with the conduction
angle.
Additionally it can be observed from Fig. 2.13 that odd harmonics are equal to zero
for class B operation and that the second harmonic is always in phase with the
fundamental component disregard of the class of operation, which is not the case for
higher harmonics. Nevertheless, it is very important to remark that this conclusion
is based on a very simple model of the transistor trans-conductance gm (which is
considered constant with Vgs ) and drain current. When more accurate models are
used instead, harmonic behavior can be appreciable different from this description.
23
Figure 2.13: Current harmonic components for reduced-conduction-angle amplifiers
Harmonic output termination: tuned load

As it has been shown in the previous section, drain currents with reduced conduction
angle have numerous harmonic components, theoretically an infinite number. At
the output of the amplifier, we only want the fundamental component and not the
harmonics components, so the latter have to be cancelled somehow. A first idea to
realize this cancellation is to provide short circuits for all the harmonics except the
fundamental. Traditionally, this has been implemented with a shunt resonant circuit
(tank), like the one indicated in Fig. 2.14. This technique for harmonics termination
is known as Tuned Load [9].
Given that only the fundamental current component is present at the output, the
output voltage has a sinusoidal waveform, which is also reflected back as a sinusoidal
waveform at the drain terminal. Therefore, in order to have a maximum excursion
in voltage, the drain waveform must have a quiescent point (DC) equal to half the
maximum drain voltage (typically Vbreakdown ). Furthermore, the load that guarantees
this condition can be determined as
Ropt =
VDD Vknee
I1
where I1 is given by equation (2.25) for n = 1, then

24
(2.26)
Figure 2.14: Tuned load harmonic termination
Ropt =
VDD Vknee
Imax sin()
2 . 1cos(/2)

=
2 (VDD Vknee )
Imax
Ropt = (RoptclassA )
1 cos(/2)
sin
1 cos(/2)
sin
(2.27)
where this optimal value has been expressed as a function of the optimal load in class
A operation, RoptclassA (see equation (2.14)), for comparisons sake.
Provided this optimal load at the fundamental and the short circuits at the harmonics,
the following power and drain efficiency figures can be calculated:

Pout =
VDD Vknee

I1
1
Imax sin()

= (VDD Vknee )
.
2
2 1 cos(/2)
2
using equation (2.22), this can be expressed as
Pout
1
= (PoutclassA )
PDC = VDC IDC = VDD
sin()
1 cos(/2)
Imax 2.sin(/2) .cos(/2)

.
2
1 cos(/2)
25
(2.28)
Figure 2.15: Optimal load (a) and output power/drain efficiency (b) relative to class A
Likewise using equation (2.19),
PDC =
1
(PDCclassA )
2.sin(/2) .cos(/2)
1 cos(/2)

(2.29)
And considering equation (2.23), the drain effiency can be determined as
Pout
= classA
PDC
sin()
2.sin(/2) .cos(/2)

(2.30)
How these values vary with the conduction angle is presented in Fig. 2.15. Some
important remarks arise from observing these plots:
The optimal loads for class-B and class-A have the same value (see Fig. (2.15)a).
The output power for class A and B is the same; nevertheless class B draws
less DC power, mainly due to the reduced DC current as can be verified from
Fig. 2.13
Drain efficiency increases with the reduction of the conduction angle, for instance in class B operation the drain efficiency that can be obtained is /2
times the efficiency of class A operation, that is 78.5%. Higher drain efficiency
26
2.6. Class-E power amplifier

Table 2.2: Efficiency and linearity for class A to class C amplifiers
Mode
A
AB
B
C
Conduction Angle
2
2
Theoretical Efficiency
50%
50-78.5%
78.5%
78.5%-100%
Linearity
excellent
between class A and B
moderate
poor
can be obtained in class C operation, theoretically the maximum efficiency is

100%; nevertheless the output power will decrease with the angle reduction as
can be observed in Fig. 2.15b, reaching the trivial case of zero output power for
a zero conduction angle.
It is also important to remark that the linearity of the amplifier is affected by the
reduction of the conduction angle, basically due to the fact that the device will have
smaller excursion in the linear region when the conduction angle is reduced. The
most linear amplifier is obtained for class A operation and less linearity is seen for
class C operation. An amplifier operating in class A or B exhibits similar linearity
performance if the transconductance of the device (gm ) is considered constant [10].
However, this is not normally the case, and better linearity performance in class A
bias condition is normally expected. On the other hand, class B operation offers
higher efficiency than class A for the same output power. Therefore a good trade off
between linearity and efficiency is to operate the amplifier in class AB, which is the
most common solution nowadays for RF power amplifiers.
As a way to summarize most of the information presented for class-A to class-C
amplifiers, some typical values for these are presented in table 2.2.
An alternative solution for the harmonic terminations would be to use open circuits
rather than short circuits, which is a technique that has been widely used in RF class
E power amplifier. Furthermore, instead of trying to cancel the harmonics, some
relatively new techniques [11, 12], make use of them to shape the drain current with
the aim of obtaining an increase of the output power and drain efficiency. These
techniques will be described in detail in the following sections.
2.6
Class-E power amplifier
From our analysis of class-A to class-C amplifiers, it is clear that the device behaves
as a current source controlled by the input signal and bias level. Unlike these cases,
in class D and E amplifiers the device is overdriven such that it behaves more like a
switch than as a current source. This is done with the intention to shape the drain
waveform into a square pulse. This will reduce the overlapping of the intrinsic current
27

and voltage waveforms, and therefore the thermal dissipation in the transistor is less
too.
A class-D amplifier operates with two switching devices commuting between ground
and VDD . Because of the required synchronization between these two devices and the
parasitic reactances involved, this type of amplifier is only feasible in low frequencies applications (around tens of MHz). For this reason, its description will not be
presented in further details because it is not so relevant for the scope of this thesis.
Complete information about this amplifier can be found in the references [13, 14].
Unlike class-D amplifiers, a Class-E amplifier has the advantage of operating with
only one switching device, and despite the fact that its application initially was only
for low frequencies, its use has been extended to microwave frequencies nowadays. A
detailed analysis will be presented in the following sections.
2.6.1
Capacitance and switching losses
In order to understand the principles of an amplifier working in class E, let us start by

considering an example of a generic non-linear amplifier whose simplified schematic
and corresponding voltage and current waveforms are shown in Fig. 2.16 [13]. The
capacitor Cout corresponds to either or both the intrinsic device capacitance or an
external capacitance added for filtering/matching purposes.
In the time-domain waveform, two overlapping regions can be distinguished
T ov1 (16 ns) that corresponds to the intersection of the end of the conducting
region and the start of the cut-off region, or in other words, the transition region
from ON to OFF.
T ov2 (34 ns) that corresponds to the intersection of the end of the cut-off region
and the start of the saturation region, or in other words, the transition from
OFF to ON.
From these two overlapping regions, T ov2 is the most critical since it lasts longer and
implies larger values of current and voltage for this example.
This amplifier has been biased with 12 V at the drain and draws a DC current of 125
mA. In order to evaluate the losses in this amplifier, the following simplified analysis
can be performed:
Loss in the Output Capacitor, at the beginning of T ov2 (see Fig. 2.16b), the
capacitor is charged to 15 V, and thus the energy stored is
Ecap =
C V2
= 37 nJ
2
28
Figure 2.16: Study case: non-linear amplifier (a), current and voltage waveforms (b)
At the end of this period T ov2 , the voltage Vds has dropped to 2 V, given a storage
energy less than one nJ. The missing energy has been dissipated in the transistor. To
put this in terms of power, this loss of energy has to be multiplied by the frequency
PCap = Ecap f = 129 mW
Loss in the transistor due to ON resistance, the current associated to the output
capacitance has to be calculated first. The charge can be calculated as
Q = CV = 5 nC
Then in order to obtain the capacitance current, this charge has to be multiplied by
the frequency
Icap = Q f = 17.5 mA
Therefore the current during the saturation period, can be calculated by subtracting
Icap from the DC current, then
ION = IDC Icap = 125 mA 17.5 mA = 107.5 mA
29
Figure 2.17: Power balance of a non-linear power amplifier
Finally the power can be calculated by multiplying this value by the ON voltage (see
Fig. 2.16b)
PON = ION VON = 107.5 2 = 215 mW
Then the total dissipated power is
Pdiss = PCap + PON = 344 mW
A graph showing the flow of the power can be seen in Fig. 2.17.
As it has been shown the loss due to the output capacitance is an appreciable part of
the total losses. There are even cases where this loss is the most important one and
has to be controlled, diminished or eliminated. A method to cancel the loss due to
this capacitor in the transition from OFF to ON was proposed by Sokal and Sokal in
1975 [15], and gave rise to the class E power amplifier.
2.6.2
Class-E operation analysis
The following analysis is the classical analysis for class E operation. It is based on the
original proposal of their inventors [15] and the mathematical analysis of Raab [16].
This circuit was intended to be used at low frequencies and it is implemented by a
30

lumped components network, like the one shown in Fig. 2.18. Despite the simplicity
of this circuit, the following assumptions or idealizations are assumed for the involved
elements:
- The RF choke inductance is large enough to assume that a constant current is
flowing through it.
- The internal resistance of the choke is zero.
- The quality factor of the output resonant circuit is high enough to consider a pure
sine wave flowing through the output load.
- The capacitance and inductance of the resonant circuit have zero resistive part.
- The switch device has zero on-resistance.
- The switch device has zero current fall time.
- The shunt capacitance Cout is linear and independent of the voltage across it.
Based on these conditions, it can be established that only one harmonic current
component can pass through the output branch
iRF () = Irf sin( + )
(2.31)
where = wt and is the phase angle of the sinusoidal wave.

Applying Kirchoff current law (KCL) at the switch node
iS () + iCAP () = IDD iRF ()
(2.32)
Additionally in the capacitor branch
iCAP () = Cout
dvS
d
(2.33)
Considering the switch is open (device in cut-off) for [0, ] and is closed [, 2],
then equation (2.32) can be split in two distinct parts:

iCAP () =

iS () =
IDD Irf sin( + ),

0,
0,
IDD Irf sin( + ),
31
0 < ;
< 2
0 < ;
< 2
(2.34)
(2.35)
Figure 2.18: Classical configuration of class-E PA, in terms of lumped components
These currents can be observed in Fig. 2.19.

Equation (2.33) can be solved for vS by integrating the equation and considering
vS (0) = 0 as a boundary condition. Then using this expression in equation (2.34), vS
can be determined as

vS () =
1
Cout (IDD
+ Irf (cos( + ) cos())),
0,
0 < ;
< 2
(2.36)
In subsection 2.6.1 it has already been described that losses at the output capacitance
could become a major detrimental factor for efficiency. In class E operation this is
avoided by assuring that in the transition from OFF to ON, the switch voltage is
zero, i.e., vS () = 0. This condition is known as Zero Voltage Switching (ZVS), see
Fig. 2.19. The acronym ZVS will be used from now on. Then applying this ZVS
condition to equation (2.36) the following relationship can be established

Irf = IDD
2 cos()

(2.37)
Substitution of equation (2.37) into (2.35) and (2.36) yields expressions for switch
current and voltage depending solely on IDD and
(
iS () =
(
vS () =
IDD
Cout
0 < ;
0,
IDD
2cos()sin(+)
2cos()
2cos()+(cos(+)cos())
2cos()
0,
32
< 2
,

0 < ;
< 2
(2.38)
(2.39)
Figure 2.19: Class E current and voltage waveforms
These equations are sufficient to derive the main features of this type of amplifier,
including its figures of merit.
The DC voltage can be calculated based on vS (), since the resistance of the choke is
zero, hence
VDD
=
2
Z2
vS ()d =
IDD tan()
2 Cout
(2.40)
This also establishes a relationship between VDD and IDD . Normally, VDD is an
independent variable for the design and IDD is the dependent variable. Knowing the
DC voltage, the DC power consumption can be determined as
PDC = VDD IDD =
2
2
IDD
2 VDD
Cout
tan()
=
2 Cout
tan()
(2.41)
The output power can be calculated as the power contained in the fundamental component of the switch current and voltage. Applying the Fourier transform to the
current and voltage expressions indicated in formula (2.38) and (2.39), the output
power can be calculated as
33
Figure 2.20: Power output capability for class-E amplifier
2
sin()
1
IDD
Re{V s(k=1) Conj(Is(k=1) )} =
(2.42)
2
2 cos() Cout
where V sk and Isk are the complex Fourier components of vS and iS respectively.
Re represents the real part of a complex number and Conj means complex conjugate.
The minus sign in Is(k=1) is used to consider the current provided from the device
(as switch) to the output network. As it can be noticed, the expression for the output
power (formula (2.42)) is similar to the expression for the DC power (formula (2.41)).
Hence, the drain efficiency is obviously
Pout = Pf0 =

Pout
= 100%
=
PDC
(2.43)
This last formula is independent of the phase angle . This means that all the sets of
waveforms (iS ,vS ) defined for different values of have 100% efficiency. Nevertheless
among all these possible solutions, there is one that gives the optimum performance
in terms of power capability and waveform feasibility. To analyze this, first let us
calculate the power capability factor [16]
Pmax =
Pout
vSmax iSmax
34
(2.44)

where vSmax and iSmax are the maximum values of the switch voltage and current.
These values can be calculated by taking the derivative of formulas (2.38), (2.39) and
equaling those to zero. This gives the angle s that maximize/minimize those expressions. Then evaluating formulas (2.38) and (2.39) for these angle s, the maximum
switch current and voltage can be found:
vSmax

IDD 2 cos() 2 cos() arcsin 2cos()
2 cos() Cout
p

IDD 2 4 cos2 () + cos()
(2.45)
2 cos() Cout
iSmax =
IDD (2 cos() + )
2 cos()
(2.46)
Replacing equations (2.42), (2.45) and (2.46) into equation (2.44), an expression for
Pmax can be found, which is only dependent on
Pmax =
2 cos() sin()
Den() (2 cos() + )
(2.47)
where

Den() = 2 cos() 2 cos() arcsin
2cos()
2 4 cos2 () + cos()
The expression (2.47) can be solved numerically in order to find the angle that
maximizes Pmax . In Fig. 2.20 the variation of Pmax with the angle can be observed.
Since Pmax has to be positive, the angle is restricted to the range [ 2 ,0]. In this
range, the angle -0.57 rad (opt ) corresponds to the maximum value Pmax . Voltage and
current waveforms related to this angle are known as the optimal class-E waveforms.
An example of these waveforms have been already shown in Fig. 2.19. Another
characteristic of the optimal class-E amplifier is that the derivative of the switch
voltage vS at the transition from OFF to ON ( = ) is zero. This condition is known
as zero derivative voltage switching (ZDVS). Alternatively, ZDVS can be interpreted
as the condition in which the capacitor current becomes zero at the transition OFF
to ON (see Fig. 2.19). Furthermore, it is in the optimal class-E operation where the
value of iS and vS are always positive. Other angles give either negative iS or
negative vS (see Fig. 2.21), which make them more restricted physically. Commonly
when class-E is referenced, the optimal class E operation is meant, where both ZVS
and ZDVS conditions are fulfilled.
35
Figure 2.21: class-E waveforms for different values of
For this optimal class-E condition, the optimal impedance Zopt can be calculated. In
terms of circuit components, this optimal impedance is represented and implemented
by RL +jXL in Fig. 2.18. Furthermore, this impedance corresponds to the impedance
seen by the device at the output without including Cout and therefore it can be
calculated as
Zoptk =
VSk
IRFk
(2.48)
where k is the frequency index, VSk and IRFk are the complex Fourier components
of vS and iRF respectively. Using equations (2.31), (2.37) and (2.39), Zopt at the
fundamental frequency is determined as
Zopt =
0.28 ej49
= RL + jXL
Cout
(2.49)
It can be noticed that the optimal load depends solely on Cout . Furthermore, from
equation (2.42) we know that the output power depends on Cout as well. Usually, at
low frequencies, the value of Cout is a design variable for obtaining a target output
power. This is possible because a required value of Cout can be obtained by adding
external capacitance to the transistor or by sizing the dimensions of a device (when
36

Table 2.3: Class-E lumped component design values
Element
Value
Cout
0.32Pout
2
wVDD
RL
2
0.58VDD
Pout
XL
2
0.66VDD
Pout
device processing is available). Then by replacing the value of Cout in terms of Pout
in the expression for the optimal load, all the lumped component design values can be
determined as function of output power and DC voltage (see Table 2.3). Regarding
the elements Lo Co which conform a resonant circuit with the highest quality factor
(infinite, theoretically) at the operating frequency , their values are related by
=
1
Lo C o
(2.50)
Actually, an infinity quality factor is a non-practical condition and a finite value has
an influence on the general performance of the amplifier. New numerical methods considering the quality factor of the resonant circuit suggest corrections to the formulas of
Table 2.3, where the quality factor should be an input parameter [17, 18, 19, 20, 21, 22].
The design formulas, described so far, can not be applied at high frequencies because
the output capacitance Cout can not be tailored. Adding external capacitance parallel
to the device is no longer feasible because of all the involved parasitics. So the value
of Cout is fixed and determined solely by the intrinsic device capacitance. Likewise,
the output power is set and limited by the intrinsic device capacitance. An exception
can take place if the device can be sized by technological processing.
The foremost features of a class-E topology, such as circuit simplicity and high drain
efficiency, can be shadowed by two factors not mentioned until this point. Maximum
voltage and current ratings are high in comparison with other types of amplifier.
The maximum voltage and current for the optimal class-E can be calculated from
equations (2.45) and (2.46), considering = 0.57 and equation (2.40),
vSmax = 3.56 VDD
37
(2.51)
2.7. Class-F power amplifier
iSmax = 2.86 IDD
(2.52)
This maximum switch voltage has become a restricting factor for recent technologies
featuring low breakdown voltage (see chapter 3). On the other hand, the effect of
the maximum current is not obvious and direct, since it depends on the DC current,
which simultaneously depends on the DC voltage, output capacitance and frequency,
see equation (2.40). As a result, it can be concluded from equation (2.52) and (2.40)
that there exists a maximum frequency for optimal class E operation [23, 24]
iSmax = 2.86 IDD = 2.86 (3.12 Cout VDD ) fmaxclassE =
0.018 iSmax
Cout VDD
(2.53)
Beyond this frequency, optimal class E is not guaranteed. It has to be remarked that
in this equation iSmax is the maximum current available from the device.
2.7
Class-F power amplifier
A last type of amplifier to be mentioned in this overview is the class-F amplifier.

This sort of amplifier [25] is, as a matter of fact, an improvement technique applied
to conventional class-B or class-AB amplifiers to get higher output power and better
efficiency figures. To understand the idea behind this technique, a conventional class
B amplifier and its voltage and current waveforms are presented in Fig. 2.22. As it
was already described in subsection 2.5.2, a tank circuit is added in shunt with the
load in order to filter out all the current harmonic components but the fundamental
one. As a result, the drain voltage becomes a sinusoid with a DC offset. The drain
current is the aforementioned truncated sinusoid. The overlapping in time of this
drain current and the voltage becomes the dissipated power of the device/amplifier
and this should be minimized in order to improve the efficiency. A way to achieve
this, is to add a tank circuit tuned at the third harmonic in series with the tuned load
(see Fig. 2.23). As a result, the net drain voltage will be the sum of the fundamental
and the third harmonic voltage components. The outcome of the interaction of these
two waves is a flattening of the drain voltage as can be observed in Fig. 2.23. This
brings up a reduction of the overlapping, and thereby less dissipated power. On the
other hand, the voltage of the fundamental can be increased beyond the conventional
limit as a result of the room left after the flattening, and therefore the output power,
contained in the fundamental, can be increased.
Mathematically the drain voltage can be expressed as
vDS () = VDD + V1 cos() + V3 cos(3)
38
(2.54)
Figure 2.22: Circuit and corresponding voltage and current waveforms for class-B power
amplifier
Figure 2.23: Circuit and corresponding voltage and current waveforms for class-F power
amplifier
Several combinations for the values of V1 and V3 are possible as long as V3 is negative,
because otherwise the effect will be opposite to the expected one. The case illustrated
in Fig. 2.23, corresponds to the case where V1 = 9V8DD and V3 = V91 . This is known
as the maximally flat case [26]. For this case, it can be inferred that the amplitude of
the fundamental can be enlarged 98 times the legacy class-B amplitude, and therefore
an increase in 0.5 dB in output power can be obtained. Moreover, an efficiency
improvement of 98 times class B efficiency can be expected as well. This means an
efficiency of 88.5%.
From all the possible combinations of V1 and V3 , the maximum output power and
efficiency is obtained for the case V3 = V61 . Due to the flattening effect of the third
39

harmonic in this case, the fundamental amplitude can be enlarged up to V1 = 2VDD
3
keeping the same voltage excursion as a conventional class B amplifier. As a result,
an increase of 0.6 dB in output power and an efficiency of 90.7% could be obtained.
The flattening effect of the third harmonic is only feasible when V3 is in anti-phase
with V1 . Recalling the current harmonic behavior from Fig. 2.13, it can be seen that
the phase of the third harmonic is negative when the conduction angle is higher than
180, i.e., in class AB operation. Then this technique is usually applied at this bias
condition.
Besides third harmonic enhancement, other higher odd harmonics (fifth, seventh and
so forth) can be added to the fundamental to shape the drain voltage even more.
Thereby, an increasing output power and efficiency is obtained. The limiting case is
when infinite odd harmonics are considered, given rise to a square drain voltage [27].
For this particular case, the required harmonic impedances can be determined based
on Fourier expansions of the voltage and current waveforms. The voltage and current
Fourier coefficients are
VDSn =
j4VDD
j2.VDD
n
n ((1)
n=1
IDSn =
1), n 2
jImax
2
jImax
(n2 1) (1
n=1
+ (1)n ), n 2
(2.55)
where n is the frequency index, VDSn and IDSn are the complex Fourier components
of vDS and iDS respectively. Therefore the required harmonic impedances in this case
will be [27]
8V
DD
Imax
VDSn
=
Zn =
0
IDSn
n=1
n = 2, 4, ..
n = 3, 5, ...
(2.56)
Despite being a theoretical case, a practical implementation of this can be essayed (see
Fig. 2.24a). A quarter wavelength transmission line provides the required impedance
transformation. The open circuit effect of the tank circuit at the fundamental is
transformed into short circuits at even harmonics and into open circuits at the odd
harmonics thanks to the 4 transmission line. This approach could work well at
medium-high frequency applications, where device extrinsic parasitics could be neglected and the physical length of 4 could be acceptable. At very high frequencies,
the parasitics degrade the effect of the 4 transmission line and have to be compensated. On the other hand, there is no odd current harmonic component in class-B (see
Fig. 2.13) implying that there would not be voltage odd harmonics despite providing
40
2.8. Actual figures of merit and efficiency - linearity challenge
Figure 2.24: Class F amplifier with quarter wavelength TL (a) to square drain voltage
waveform (b)
infinite impedances. In practice, this can be solved by increasing the conduction angle
above class B (class AB operation), which generates odd harmonics components.
Unlike other classes of operation already described, there is not a unique definition for
the class F technique. Some authors [25, 26] define class F as the maximally flat case
(third harmonic enhancement), while others consider class-F as the one with square
voltage and truncated sinusoidal current (infinite harmonics) [14]. What is clear is
that in this technique, mainly odd harmonics are controlled to improve the amplifier
performance, or alternatively open/short circuits loads are used. Relatively recent
researches have been carried out to control even and odd harmonics in a more accurate
way by setting harmonic loads different from zero or infinity. This technique is known
as Harmonic Manipulation (HM) Technique [11, 12]. Actually the second and third
harmonics are only controlled in this technique. This is because higher harmonics are
short-circuited by the output device capacitance at such high microwave frequencies.
2.8
Actual figures of merit and efficiency - linearity

challenge
Most common types of amplifiers used in communications have been already described
in previous sections, including their typical figures of merit. At this point, it is important to emphasize that figures of merit such as output power and efficiency are
based on peak output power. Typical efficiency values around 40% for class A or 70%
for class AB amplifier are cited, but are only possible when the device is reaching the
saturation region. These efficiency values will decrease substantially when the power
41
Figure 2.25: OFDM signal trajectory (a) and probability distribution (b) for the IEEE
802.11a standard
amplifier is operated backed off from this peak condition. Legacy applications such as
AMPS and GSM, which bear constant-envelope RF signals, can operate the amplifier
at its peak condition and obtain high efficiency values. Nevertheless, relatively new
applications like W-CDMA, WLAN and WiMAX demand the use of complex nonconstant envelope signals, see Fig. 2.25a (which can accommodate higher data rates
per bandwidth unit). In this case, the efficiency of the amplifier will change continuously over time according to the amplitude of the signal. Then, it could happen
that the efficiency stays low for longer periods of time and is high at sporadic time
instants, leading to a very poor average efficiency.
A proper way to measure the efficiency in this case is to use the concepts of average
output power, average DC power and average drain efficiency, defined as follows;
Z
Poutavg =
Pout p(Pout ) dPout
(2.57)
PDC (Pout ) p(Pout ) dPout
(2.58)
Z
PDCavg =
davg
R
Pout p(Pout ) dPout
Poutavg
R
=
=
PDCavg
(2.59)
where Pout is the output power, p(Pout ) is the probability of an output power level
Pout and PDC (Pout ) is the DC power consumption at an output power level Pout .
42
Figure 2.26: Probability distribution for transmit power level in urban and suburban
environment[28]
As a matter of fact, there are two ways to define the probability function used in
the formula above [29]. A first approximation would be to consider the probability
density function (pdf) of the signal power itself. An example of this can be seen in
Fig. 2.25b [14]. Nevertheless there is another representative definition for this pdf
given the wireless scenery in which they are applied. In applications like CDMA,
the output power of the mobile handset is controlled by the base station in order
to avoid interference among channels. Then a statistic of the different power levels
of the mobile handset during normal operation can be constructed. These statistics
depend on more factors than in the former definition, for instance system architecture,
propagation conditions, distance, etc. An example of this distribution can be seen in
Fig. 2.26 [28]. It can be inferred from this graph that the output power of the amplifier
is most of the time around 6 dBm instead of at its peak power. So the average
efficiency as defined in formula 2.59 could be as low as 3%. Then, irrespective of the
pdf definition applied, it can be concluded that for non-constant envelope signals and
for RF signals with power control, the amplifier is operated with several dB back off
from its peak power, which leads to very poor efficiency. On the other hand, when
the amplifier is operated in the back off region, its linearity is acceptable, which is
not the case when it is reaching saturation due to all the intermodulation products
distortion.
Given this scenery, new techniques have been proposed to improve the linearity and/or
efficiency for large power dynamic range. These can be characterized as linearity or efficiency oriented. Some representative linearity-oriented techniques are pre-distortion,
feedforward and feedback, while for efficiency-oriented techniques we have dynamic
biasing, envelope tracking-EER and dynamic load.
43
Figure 2.27: Linearity-enhancement technique: predistortion
In Fig. 2.27 the general idea about the pre-distortion technique is illustrated. A predistorter compensates the amplifiers non-linearities by presenting a transfer function
which is the inverse of the amplifier transfer function, giving as a result a linear function over the full dynamic range. This compensation could be realized at the RF level
in an analog way or it could be implemented in base-band as a digital pre-distorter.
In Fig. 2.28 the general characteristics of efficiency-oriented techniques are presented.
The common idea behind all these techniques is to move the load line dynamically
with the input power. Conventionally, the load line is fixed and sized to provide
maximum excursion for maximum input power, however this load line becomes nonoptimal for lower input power conditions. Therefore, this load line has to change
continuously according to the input power. This load line variation can be obtained
by changing the bias current with the instantaneous input power (see Fig. 2.28a).
Alternatively, the bias current as well as bias voltage can be varied with the input
power (see Fig. 2.28b), or specifically the load impedance can be adapted dynamically
with the instantaneous output power (see Fig. 2.28c).
Linearizers, such as pre-distorters, show their best performance when the amplifier
is at its highest output power because this is when the highest levels of distortion
are presented, but their effect is not so relevant when the amplifier is backed-off
and the amplifier itself poses good linearity. At this moment, it is paramount to
improve the efficiency instead, with some of the efficiency-oriented techniques already
mentioned. As a result, the ultimate solution for the linearity/efficiency challenge,
posed by current wireless applications, would be to utilize a combination of a linearizer
and an efficiency enhancement technique [30].
44
2.9. Conclusions
Figure 2.28: Efficiency enhancement techniques
2.9
Conclusions
In this chapter, an overview of all the basic concepts involved in the world of RF
power amplifiers was presented. A distinction between small signal amplifier and
power amplifier was necessary to understand the particular conditions under which
the transistor is operated. Since there are several sorts of power amplifiers, figures of
merit have to be defined in order to have ways for intercomparison. Amplifiers having
good performance in terms of linearity (class-A, class-AB) or efficiency (class-E, classF) have been described. Nevertheless in the actual wireless context, amplifiers having
both features at the same time are demanded. This has led to the development of
new strategies to construct amplifier architectures aimed to fulfill both conditions.
Most of the results presented hereby were based on very simple device models. These
figures can be used as initial design value references. However they start to fail
appreciably as the frequency increases. This implies that more accurate models closer
to the physics and device structure have to be explored. On the other hand, new device
technologies have been developed in recent years in order to cope with the stringent
requirements of the RF market, like cost-effectiveness, compactness and integrability.
Therefore, issues related to current and new generation device technologies, as well
as device modeling, will be the subjects of the following chapters.
45
Chapter 3
RF devices for power

amplifiers
3.1
Introduction
Most of the results presented in the second chapter were based on an oversimplification of device characteristics and behavior. Despite the incurred inaccuracy, this
simplification gives a first idea about the requirements for selecting or discarding a
specific device technology. For instance, class-E amplifiers demand the highest device
breakdown voltage as compared to other amplifier configurations. This requirement
restricted the applicability of this type of amplifier for high frequency applications
in the past, because technology development was stretching the device speed at the
expense of the device breakdown voltage. However, this changed with the advent of
GaN devices. These devices, showing outstanding breakdown voltages, bring classE configurations back in the game. Nevertheless this GaN technology is not 100%
mature when compared to legacy technologies as SiGe and GaAs.
Of these two mature technologies GaAs has been dominating the RF power amplifier
market [31, 32, 33] due to its unique characteristics as high cut-off frequency, relatively
high breakdown voltage, and high gain. Nevertheless there have been major efforts
to enhance Si technologies in order to make them comparable with GaAs, and in this
way obtain some of the RF amplifier market. On the other hand, the attractiveness
of Si technologies results from their integrability with traditional device processes and
their low cost.
Because of the importance of these technological concepts and considering the current
developments on the power amplifier scenery, this chapter will give a broad overview
on most of the device types used for designing power amplifiers.
47
3.2. General concepts
3.2
General concepts
In order to situate the devices utilized in RF power amplifiers in the current electronic
global market, a brief overview of the electronics mainstreams will be necessary. For
this purpose, F. Schwierz [31, 32, 33, 34, 35] made a good description of the two major
trends in recent years
Mainstream electronics
This refers to the electronics found in massive digital components such as processors, field-programmable gate arrays (FPGA), application-specific integrated circuits
(ASIC) and memories. The dominant type of transistor in this case is the MOSFET,
specifically in its CMOS configuration, and the semiconductor material employed for
all these devices is Silicon. A crucial characteristic of these devices is the high level
of miniaturization and integration. The number of transistors shrunk on one integrated circuit (IC) has grown rapidly in the last decades. How this integration would
be over the time was foreseen many years ago by Gordon Moore [36]. The updated
interpretation, of what is known as Moores law nowadays, said that the number of
transistors on an integrated circuit for minimum component cost doubles every 24
months. In Fig. 3.1 this law is illustrated.
As the level of device integration soars, the device size decreases dramatically (downscaling). As a result, in 2007 most of the PC processors are fabricated using 65 nm
fabrication processes. Under this process, the minimum MOSFET length that can
be obtained is 35 nm. For instance a Pentium 4 processor can contain more than 40
million of this type of transistors.
RF electronics
Unlike the one described above which is mainly digitally oriented, this technology
is for analog, RF or microwave purposes. It has its origins and main developments
in military applications, which were preponderant in the 1970s and 80s [31, 32, 33,
34, 35, 37]. Its widespread use in commercial applications started in the 1990s with
the surge of mobile communications. RF devices are used to construct circuits such
as oscillators, mixers, low noise amplifiers, and RF power amplifiers. These basic
blocks are crucial parts in electronic equipments used in e.g. cellular communications,
wireless LAN, and satellite TV for instance.
While in mainstream electronics, integration has proven to make circuits smaller,
faster, and cheaper, in the RF world, integration has shown not to be a good option due to the poor yields and the high expenses incurred compared with discrete
component solutions (hybrid circuits). For instance implementing an RF circuit as a
monolithic microwave integrated circuit (MMIC) would be far more expensive than
48
Figure 3.1: Transistor count for Intel processor and Moores Law [38]
fabricating it as a hybrid circuit and additionally it would have a much larger time
to market (TTM).
In contrast to mainstream electronics where basically one semiconductor material (Si)
is found and mainly one type of transistor (MOSFET) is exploited, in the RF domain
a variety of semiconductors substrate materials is being utilized, for instance SiGe,
GaAs, InP and GaN. Likewise, more than one device structure is employed, hence
transistor structures such as MESFET, HEMT, BJT, HBT, LDMOS can be found.
Due to the lack of success with integration, the device scaling has not been developed
as dramatically as in the digital world. For instance, HEMT devices used in typical
microwave applications have typically a length of about 250 nm nowadays. As a
matter of fact, Moores law has never been applied in this environment.
Finally, it is fair to mention that more and more circuits traditionally built using RF
devices are now being implemented in CMOS technologies [7] with all the implied
benefits that this involves. As a result, this may lead to think that the line between
mainstream electronics and RF electronics will disappear eventually. However, one
essential aspect has been missing: an RF CMOS solution has limitations due to the
presence of larger parasitics and losses as the frequency increases. As a result, it could
be expected that RF devices will be still dominating in transceiver elements such as
low noise amplifiers and power amplifiers .
As in the second chapter of this thesis related to power amplifiers, it is necessary to
define figures of merit in order to compare the different types of RF devices available.
fT and fmax are figures of merit to ponder high frequency capabilities, and breakdown
voltage to assess power capabilities. These will be described next with some related
49
Figure 3.2: Active device as a two port network
basic concepts.
3.2.1
Two-port network and stability condition
An active device can be characterized by a two-port network like the one shown in
Fig. 3.2. In this case, expressions defining the relationship between the input/output
current/voltage can be defined by using Y- or H-parameters [39], or alternatively
with S-parameters if travelling voltage waves are considered instead. While Y/Hparameters are normally utilized in low-frequency electronics, S-parameters are widely
used in RF electronics. This because of the fact that measuring travelling voltage
waves is technically more feasible than providing a broad-band short or open circuit
at very high frequencies.
Particularly each S-parameter receives the following RF technical term as an expression of the concept associated with it:
Input return loss= 20log |S11 | ,
Gain= 20log |S21 | ,
Isolation= 20log |S12 | ,
S21 =
v2
v1+
S12 =
Output return loss= 20log |S22 | ,
S11 =
v1
v1+
|v+ =0
2
|v+ =0
2
v1
v2+
|v+ =0
1
S22 =
v2
v2+
|v+ =0
1
where
are the forward travelling waves entering the device and v1 , v2 are the
backward travelling waves coming out of the device.
v1+ , v2+
50

Although it is not the case here, it is worth to mention that in case of (passive)
reciprocal components, S21 = S12 , the associated technical term is insertion loss.
Unlike passive components, which never oscillate, an active device can either be able
to maintain an oscillation or to amplify a signal. Since the aim is to make the device
operate as an amplifier, spurious intrinsic oscillations must be avoided. In this context,
a device is said to be unconditionally stable when it does not oscillate for any source
or load impedance presented at its terminals. Otherwise, it is said that device is
conditionally stable or potentially unstable. It is assumed that the aforementioned
load and source impedance have a positive real part (i.e., they are inside the Smith
chart). To numerically evaluate this stability condition, Rollets stability factors have
to be calculated, as follows:
2
1 |S11 | |S22 | + ||
2 |S12 S21 |
(3.1)
|4| = |S11 S22 S12 S21 |
(3.2)
K=
Then a device is unconditionally stable when K > 1 and 4 < 1. Alternatively, the
factor can also be utilized to evaluate the stability
2
1 |S11 |
| + |S
|S22 4 S11
12 S21 |
(3.3)
In this case has to be greater than 1 to guarantee unconditional stability. This

factor has the advantage of being a single parameter and it can be used as a reference
to compare the stability of two or more different devices.
3.2.2
Two-port power gain
There are three ways to define the power gain of the network shown in Fig. 3.2 [39].
These are power gain (G), available gain (GA ) and transducer power gain (GT ),
which give three different figures. However, these three values coincide when they
are maximized. In this case, the maximum gain is giving in a unique form by the
following formula
GTmax =

p
|S21 |
K K2 1
|S12 |
(3.4)
where K corresponds to the Rollets factor (see equation (3.1)). As it can be inferred
from the GTmax formula, a solution is only possible when the device is unconditionally
51

stable (K > 1), corresponding to the input and output conjugately matching case.
This gain is also known as maximum available gain (M AG) or GM AX. On the other
hand, when the device is conditionally stable, the maximum gain can be defined in
an alternative way, for example by setting K = 1 in equation (3.4). In this case this
maximum gain is known as Maximum Stable Gain (M SG)
M SG =
|S21 |
|S12 |
(3.5)
Another alternative, in case of conditional stable devices, is the unilateral power gain
(U ). This is defined as the maximum power gain that can be obtained from the
two-port network, after it has been made unilateral with the help of a lossless and
reciprocal embedding network [40]. When the embedded device is unilateral, the
0
reverse transmission from the output to the input port is null, i.e., S12
= 0. This U
definition was proposed by S. Mason in 1953 [41] as an invariant figure of merit to
compare transistors. This means that this value would be invariant with respect to
changes or artifacts of the environment surrounding the transistor. This value used
to be determined experimentally by making the device unilateral and maximizing its
gain. Nowadays, it is calculated from measured S-parameters, as follows:

2
S21

1

S12
|S12 S21 |

U=
=

det[1 S S ]
2 K SS21
2 Re SS21
12
12
(3.6)
where K is again the Rollets factor. Nevertheless, unlike the above-mentioned gains
which depend on whether or not the device is unconditionally stable, the unilateral
power gain(U ) [40] is independent of any stability condition.
3.2.3
Maximum frequency of oscillation and cut-off frequency
The maximum frequency of oscillation fmax and cut-off frequency fT are two figures
of merit to define the high frequency capabilities of a device.
fmax analytically can be determined from the unilateral power gain and corresponds
to the frequency value at which the unilateral power gain U becomes unity
U (f ) |f =fmax = 1
(3.7)
Therefore it is the maximum frequency of device activity above which there is no power
gain. On the other hand, its name comes from an alternative method to determine its
value. In this method [40], the device is embedded in an oscillator circuit, with input
52
Figure 3.3: fT and fmax of an LDMOS device
and output circuits incorporating a tuner, and attempts are then made to produce
oscillations in the circuit at as high frequency as possible. In practice, this value is
determined based on S-parameter measurements, which are used in equation (3.6) to
calculate U and then to determine the fmax . Furthermore, the frequency at which U
becomes one could be also the frequency at which the maximum available gain GTmax
and the maximum stable gain M SG are also unity [40, 42]. As a result, these power
gain figures of merit can be utilized to define fmax as well.
Unlike fmax , which is defined based on power gain values, fT is established on a
current gain figure. The cut-off frequency is the frequency at which the small signal
current gain of the transistor, h21 , becomes unity
h21 (f ) |f =fT = 1
(3.8)
The values of U and h21 in dB decrease monotonically with the frequency at a rate
of -20 dB/dec. This property is important because it allows to calculate fmax or fT
by extrapolation when the instrument capability is insufficient to measure these high
frequencies. An example of the calculation of fmax and fT can be observed at Fig. 3.3
for an LDMOS device [43].
53
3.2.4
Bandgap and breakdown effect
It has been already described in chapter two, sections 2.5.1 and 2.6.2 (class-A and
class-E PA) that the amplifier output power depends on the maximum voltage that
the device can stand. Then a figure of merit that measures this device characteristic
is necessary. Normally, the breakdown voltage of the transistor is the one used for
this purpose. This voltage figure, associated also to a breakdown electrical field, is a
characteristic of the type of material used in the transistor fabrication as well as the
transistor layout. Fundamental concepts related to this figure of merit are presented
next.
In solid-state physics, it is well established that electrons in materials are allowed or
forbidden to have specific energy ranges or bands. Particularly there are two allowed
bands: the valence band and the conduction band. It can be described that electrons
in the conduction band flow when an electrical field is applied, whereas in the valence
band they are not able to. In between these two bands, there is the forbidden band
or bandgap (see Fig. 3.4a), numerically defined as the energy difference between the
top of the valence band and the bottom of the conduction band. Then, electrons in
the valence band should have enough thermal energy to jump over this bandgap and
be part of a current generation process.
Normally in semiconductor materials, impurities (electrons or holes) are added to
them with the intention to have a large number of potential carriers present in the
conduction band (at ambient temperature). These impuritiy carriers are the ones
that flow when an electric field is applied to the material. The trajectory that these
carriers follow is not straight but scattered due to the continuous collision with the
ionized doping impurities. Nevertheless, the velocity associated to these carriers increases with the electric field level till it reaches a saturation point (saturation velocity
[44]). Higher electric fields increase the energy of the carriers which are transferred
to the material lattice by collisions. When this energy reaches a certain critical value,
the collision of these carriers with the semiconductor crystal will be enough to move
one electron (of the intrinsic material) from the valence band to the conduction band,
generating a new electron-hole carrier (impact ionization). This carrier can produce
again a new electron-hole pair, and so on. As a result, a current multiplication takes
place in the material, this process is called avalanche (breakdown).
As it is remarked in [44], what produces the avalanche effect is a critical energy produced under specific electrical field. As a result, typical values of DC breakdown
voltages can not be an accurate reference for defining the maximum voltage ratings
under RF operation, since electrical conditions are different and therefore the associated energies for impact ionization are different as well. What can be expected is
that under RF regime the onset of the avalanche will require higher electrical voltages
than in DC conditions. Pulsing the device for very short time (RF) would not provide
enough energy to the carriers for causing the avalanche effect.
Another important effect that limits maximum voltage excursion is the tunneling or
54
Figure 3.4: Bandgap energy concept (a) breakdown electric field versus bandgap energy (b)
Zener breakdown, which is described as the avalanche effect produced in reversedbiased p-n or Schottky junctions, in which carriers surpass (or tunnel) the energy
barrier without having the required energy. This requires a very thin barrier and a
highly doped material, conditions met by most current RF devices. It is found that
the probability of tunneling depends exponentially on the energy barrier or bandgap
energy to the 3/2 power [45].
It can be inferred from the descriptions of avalanche and tunneling effects that the
bandgap energy of the material is a key characteristic that limits or defines the breakdown electrical field or voltage. In a very rough way, it is stated that a device with a
higher bandgap energy will exhibit higher breakdown voltages. This can be observed
in Fig. 3.4b for Si, GaAs, SiC (polytypes1 3C, 4H and 6H) and GaN.
Breakdown currents can not be destructive if either a limitation mechanism and /or
a heat dissipater is provided.
Regarding transistor parameters, the breakdown characteristics are given as function
of the junction breakdown voltages in case of BJT/HBT devices. For instance: VCBO ,
the maximum collector-base voltage with open emitter and VEBO , the maximum
emitter-base voltage with open collector. In case of FETs/HEMTs, the parameters
are VGSO (VBDGS ), the gate-source breakdown voltage and VGDO (VBDGD ), gatedrain breakdown voltage.
1 Polytypes are variations of the same chemical compound that are identical in 2 dimension and
differ in the third.
55
3.3. GaAs technology and devices
Figure 3.5: MESFET layer structure (a) and typical layout (b)
3.3
GaAs technology and devices
GaAs is the de-facto technology used in microwave (power) amplifiers since the 70s
[37]. It exhibits good frequency capabilities and relatively high breakdown voltages.
These characteristics can not be obtained simultaneously in other technologies. Furthermore, it is a mature technology showing acceptable reliability.
One of the first devices fabricated using this technology was a metal-semiconductor
FET (MESFET), showing cut-off frequencies around 3 GHz at the onset of this technology and reaching values around 50 GHz years later [37]. Nowadays MESFETs are
superseded by hetero-structures devices: HEMTs and HBTs.
Recent research shows GaAs HEMTs reaching a cut-off frequency of 440 GHz [46].
This is the result of the high carrier velocity of this compound semiconductor [44],
a proper band-gap engineering of the crystal lattice (metamorphic structure), and
device scaling.
These GaAs transistor structures will be presented in the next subsections.
3.3.1
MESFET
The typical structure of a MESFET can be observed in Fig. 3.5a. A lightly doped nlayer is grown epitaxially on top of a semi-insulating GaAs layer. This layer forms the
channel where electrons flow. Since GaAs electrons have higher mobility than holes
[44], MESFET channels are normally n-type. This channel has two metal contacts
corresponding to the source and drain terminals. In order to reduce the contact
resistance, a highly doped n-layer (n+) is added between the metal contact and the
56

channel. Likewise, an undoped GaAs layer is added between the channel and the
semi-insulating layer in order to reduce defects and impurities at the bottom surface
of the channel. In order to have control over the channel current, a gate in the form
of a Schottky contact (metal-semiconductor) is created between the source and drain
terminal. A dielectric gate contact (as in MOSFET) can not be created on top of the
GaAs channel, because the deposition of silicon dioxide or any good dielectric would
produce many traps at the interface. Likewise thermally grown oxide of GaAs is a
poor dielectric [47]. On the contrary, having a Schottky contact has the advantage of
a null dielectric capacitance as well as zero traps at the interface. As a result, higher
frequencies of operation can be obtained.
Negative voltages applied at the gate reduce the electron concentration in the channel
(depletion region) till the point of complete pinch-off of the channel. The voltage
associated to this state is known as pinch-off voltage. On the other hand, when the
drain voltage is increased, the channel current will increase correspondingly until it
reaches a point where it saturates. The voltage associated with this condition is known
as V dsSAT or knee voltage, because of its appearance on the DC characteristics.
Power handling capabilities as well as frequency response of MESFETs are closely
related to the physical dimensions and layout shape of the device. In Fig. 3.5b, a
classical configuration is shown. The gate length limits the high frequency response,
for instance 1 m gate lengths are suitable for applications up to C-band, 0.5 m
works fine through X-band, 0.25 m can go over Ka-band, and 0.15 m can be useful
through W-band. The gate width sets the DC and RF maximum current handling,
thus wider devices are more convenient for power amplifiers. Nevertheless, gate widths
in the range of an appreciable fraction of a wavelength deteriorate the device response.
Typically 150 m gate widths are found in X-band power applications, while 75 m
in Ka-band applications [48]. Normally several FET fingers are paralleled in order
to increase the total width of the device, as can be seen in the last figure. The
multiplication of the number of fingers by the gate width of one finger gives the total
gate width, which is also called gate periphery.
3.3.2
HEMT
The invention of the high electron mobility transistor (HEMT) came after the discovery of the GaAs Alx Ga1x As heterostructure in 1978 by Dingle et al. [49],
which showed super-lattice structures with electron mobilities superior to any bulk
GaAs structure at that time. Nevertheless, unlike this former discovery, there is no
unique first author/inventor of the HEMT transistor. It can be established from the
references and papers [37, 50, 51] that there were two simultaneous research activities
in this area, one led by R. Dingle at Bell labs., and a second one by T. Mimura at
Fujitsu labs. Both research developments ended up with the HEMT device [51, 52]
as it is known today.
57
Figure 3.6: GaAs HEMT band diagram (a) and layer structure (b)
In its simplest way a HEMT can be seen as a MESFET wherein the n-doped channel
has been replaced by a hetero-junction, i.e., a junction of two materials with different
band gaps (see Fig. 3.6). This heterojunction creates at the interface a very thin
layer of high mobility electrons called two-dimensional electron gas (2DEG). Unlike
the MESFET, where the gate voltage controls the depth of the depleted/undepleted
channel, the voltage in the HEMT gate controls the carrier density of this 2DEG.
As it was briefly described in section 3.2.4, the carriers in an n-doped semiconductor
follow a scattered trajectory instead of a straight one, due to the constant collision
with the ionized impurities. As a result, the net velocity is diminished. What is
paradoxical is that these blocking ions are left by the same electrons, when they are
freed in the n-doped material, necessary for the current generation. In the case of a
HEMT, this problem is avoided by separating the electrons and the ionized impurities
in two different layers. In the initial implementations, these layers were a thin layer
of highly doped n-type AlGaAs and an undoped GaAs layer with a lower bandgap
than the former. Due to the lower energy level of the GaAs conduction band, the
electrons generated in the n-type AlGaAs move completely into the GaAs layer (see
Fig. 3.6a. This also gives rise to a depleted AlGaAs layer. Furthermore, the movement
of electrons creates an electric field and band bending at the heterojunction. The
transferred electrons are bounded to a narrow potential (quantum) well within the
GaAs layer, known as 2DEG, and are spatially isolated from the impurity ions. As a
result, the electrons can move swiftly through this 2DEG layer without bumping into
impurity ions.
58

The electrical contacts to the HEMT device are very similar to the above-mentioned
MESFET. Source and drain contacts are ohmic contacts with a highly doped n-layer,
while the gate contact exhibits a Schottky junction. Operationally, drain and source
contacts are extended to the 2DEG layer, where the channel is. Negative voltage is
applied to the gate in order to have the n-AlGaAs layer completely depleted under
normal operation. Nevertheless this does not avoid that under low negative or zero
voltage a parasitic (MESFET) current occurs in this n-doped layer. To increase
device high frequency capabilities, the gate length has to be reduced. However, if the
transverse gate area is reduced, the gate resistance is increased, which deteriorates
the device power gain. A solution is to use a T-shaped or mushroom gate [53]. This
comprises of two parts: a narrow stem that forms the electrical contact with the
channel and a wider tee-top that provides a low-resistance path to the stem.
In real devices, the n-doped AlGaAs and undoped GaAs are not in direct contact, but
there is a spacing layer in between (see Fig. 3.6b). This additional layer guarantees
that the electrons of the 2DEG layer do not scatter when they pass closely to the ions
of the AlGaAs layer [44].
pHEMT, mHEMT and power HEMT

The materials of the heterojunction AlGaAs/GaAs are selected for having the same
lattice constant, which prevents the formation of traps at the interface. Nevertheless
the RF performance of this junction was not good enough in earlier years. Then a
solution was found by replacing the GaAs material with an InGaAs layer. The latter
has a lower energy band than the former, yielding a larger bandgap difference. As a
result, higher carrier concentration and mobility were obtained, and at the same time,
enhanced performance was achieved. However, these new materials have different
lattice constants. This issue was overcome by making one of the layers (InGaAs) very
thin, such that the layer stretches to fit the other material [32]. This device structure
is called pseudomorphic HEMT or simply pHEMT. A pHEMT layer structure can be
observed in Fig. 3.7a. Ordinarily, these devices show cut-off frequencies higher than
100 GHz and breakdown voltages around 16 V.
An alternative way to realize HEMT devices with different lattice constants is to
provide an intermediate (buffer) layer between them. These devices are known as
metamorphic HEMT or mHEMT (see Fig. 3.7c). The buffer layer is made of AlInAs
with graded concentration of Indium, such that it matches gradually the lattice of
the GaAs substrate with the InGaAs channel layer [32]. InGaAs is normally grown
on an InP substrate, but this is expensive and fragile compared to GaAs substrates.
With this buffer layer, any Indium doping level can be realized, even higher than
pHEMT and comparable with InP HEMT [46, 54, 55]. The major disadvantage of
this technology is the low breakdown voltage.
The legacy InP HEMT is a lattice-matched (LM) heterostructure, in which InGaAs
59
3.4. Silicon-based technology and devices
Figure 3.7: HEMT structures: pHEMT (a), LM HEMT (b), mHEMT (c) and power HEMT
(d)
is grown on InP substrate (see Fig. 3.7b). This device shows the highest performance
in terms of noise figure and cut-off frequency, but it is not commercially widespread.
This is due to economic reasons, as well as the size of the wafers (typically 3) and
their brittleness.
Finally, for power applications, the carrier concentration provided in the 2DEG, like
the one shown in Fig. 3.7a, could be not sufficient. Then multiple quantum wells have
to be stacked in order to increase the total carrier concentration. A structure for this
purpose is shown in Fig. 3.7d.
3.4
Silicon-based technology and devices
Silicon-based transistors have been occupying and taking over RF roles reserved exclusively to GaAs devices during the last couple of years [56, 57]. This is due to their
continuously increasing high frequency capabilities and integrability with baseband
technologies, the latter being dominated by Si CMOS technology. Integration and
low-cost factors are the driving forces of this new generation of Si devices. Nevertheless, the RF power amplifiers area is still one of the areas where Si devices have not
deployed successfully. This is because of the trade-off between cut-off frequency and
breakdown voltage of this technology. RF power amplifiers demand high values for
both parameters at the same time.
60
Figure 3.8: Silicon CMOS technology: basic structure (a) and figures of merit (b)
This section will describe the three most representative Si devices in RF applications
nowadays: Si MOSFET, SiGe HBT, and LDMOS.
3.4.1
Si MOSFET
A typical metaloxidesemiconductor FET (MOSFET) structure can be observed in

Fig. 3.8a. As its name describes, it comprises a layer of metal (actually polysilicon)
and a layer of silicon dioxide (SiO2 ) on top of a semiconductor material, the body
(in this case, p-type). Since SiO2 is a dielectric, the gate structure is equivalent to a
plate capacitor, with one of the terminals being a semiconductor. Additionally to the
gate terminal, there are two terminals (drain and source) connected to separate highly
doped regions (indicated as n+ in the figure). When a positive voltage is applied at
the gate, the number of holes decreases in the gate area, yielding to the formation
of a depletion region. Higher positive voltages cause electrons from the n+ region to
migrate to this depletion zone giving rise to what is called an inversion layer. This
layer allows the current between source and drain when a voltage difference is applied
between them. Finally, varying the voltage between the gate and body modulates the
conductivity of the inversion layer and makes it possible to control the current flow
between drain and source. Further details about the operation modes can be found
in the references [35, 7, 47, 58].
Despite polysilicon gates have been used for a long time, there is a return to metal
gates on the new coming processing (45 nm), likewise the silicon dioxide is being
replaced by a high-k dielectric material [59]. All this is aiming at controlling the
leakage current by the tunneling effect. On the other hand, in order to improve
carriers mobility, the channel material is expected to become a combination of silicon
with germanium, instead of only silicon.
In terms of figures of merit, there is a tradeoff between the cut-off frequency and the
breakdown voltage for this technology, as can be observed in Fig. 3.8b [60]. In a very
61

simple way, it can be described that the physical length of the channel determines
the transition time of the electrons flowing from source to drain. Shorter devices
make shorter transition time, and therefore higher operating frequencies. On the
other hand, the channel length also determines the maximum operating voltage of the
transistor which is determined by the breakdown field of the material. Then, having
a longer channel enables the transistor to operate at higher drain voltages, resulting
in more RF voltage swing at the output, but with the increase of the transition time
[58]. In practice, outstanding cut-off frequencies around 300 GHz have been already
reported [56, 57, 61], but with biasing voltages equal or lower than 1 V [62, 63]. Despite
this intrinsic limitation, design of RF CMOS power amplifiers for applications below
and around 5 GHz have been already reported [43, 64, 65, 66, 67, 68]. There is also
a research report showing a frequency of operation of 60 GHz in 90 nm technology
[69]. Most of these works are for low power applications. For higher output power
and relatively low frequency, an alternative MOSFET structure, namely LDMOS, has
been in use for applications like cellular base stations (see section 3.4.2).
An additional and interesting characteristic of MOSFETs, as well as HEMTs, is that
they have a negative temperature coefficient. This causes their drain current to decrease with temperature, which prevents thermal runaway and allows multiple MOSFETs to be connected in parallel without ballasting resistors [70].
3.4.2
DMOS
For high power applications and frequencies up to around 3 GHz, two different MOSFET structures have been applied successfully. These are both double-diffused MOSFETs (DMOS) and will be described in the following subsections.
VDMOS
As it was already described, there is a trade-off to be made in Si MOSFET technology
between high frequency response and breakdown capabilities. Longer channels lead to
higher breakdown voltages, but slower devices. Furthermore, for power applications it
is also important to have very low on-resistance because this yields higher current and
better efficiency figures. Nevertheless, if the channel is made longer to provide high
breakdown voltages, the channel resistance increases as well as the ON-resistance.
This comes from the basic fact that the resistance is proportional to its length d, but
d
).
inversely proportional to its transversal area A (R = A
One solution to reduce the ON-resistance without affecting the breakdown voltage
would be to make the device wider, which would increase the channel transversal
area. However, this would increase the gate capacitance, as a result of which the
device speed would worsen.
62
Figure 3.9: DMOS structures: VDMOS (a), LDMOS (b)
The issue lays in the fact that breakdown voltage and channel resistance depend on
the same physical spot of the transistor. A first MOSFET structure was proposed to
overcome this. It is called vertical diffused MOSFET (VDMOS), whose name relates
to the physical configuration of this device (see Fig. 3.9a).
This structure is built starting from a heavily n-doped substrate in order to minimize
the bulk portion of the channel resistance. Then a lightly n-doped epi layer is grown
on it and two successive diffusions are made, a p-doped region in which the inversion
channel will be generated and n+ defining the source connection. Next a thin high
quality gate oxide is grown followed by the polysilicon layer, forming the gate. Metallic
contacts are defined for the source and gate at the top, while the bottom of the wafer
provides the drain contact.
When there is no bias at the gate, the p material separates the n+ source and n
drain regions and current does not flow. When a small positive voltage is applied
at the gate, an amount of negative charge at the oxide-silicon interface is induced
as the holes are pushed into the semiconductor bulk (see Fig. 3.10a). As a result,
a depletion region is formed by the ions left by the holes. As the gate voltage is
increased, this depletion region gets wider and some free electrons from the n-doped
region are dragged into the interface. As the gate bias is increased more electrons are
confined underneath the gate interface, hence creating a conductive channel called
inversion layer (see Fig. 3.10b). Inversion means that material under the gate
turns from p-doped to n-type. Since an n channel is formed in the p material, under
the gate structure connecting the source to the drain, current can flow between these
terminals (see Fig. 3.10c).
The parameter BVdss defines the maximum drain to source voltage, with gate and
source short-circuited, that the MOSFET can stand without avalanche breakdown.
This depends on the p-n junction between the source and drain. The increasing
63
Figure 3.10: Operation stages in a VDMOS device: VGS1 > 0 (a), VGS2 > VGS1 (b),
VGS3 VGS2 and VDS3 > 0 (c)
electric field in the depletion region of the p-n junction is what causes the sudden
avalanche of the carriers. Therefore in order to control this effect, the n region has to
be as large as possible. The larger this region is, the higher is the breakdown voltage.
On the other hand, the resistance Rds in saturation depends of several resistance
components (see current trajectory at Fig. 3.10c). Among these, channel resistance
is the most dominant factor for relatively low voltage MOSFETs, while the resistance
associated to the n-drift region becomes the dominant factor for very high voltage
MOSFETs. In the latter, a trade-off between breakdown voltage and ON-resistance
has to be made. Nevertheless, unlike the legacy MOSFET, DMOS devices have more
physical dimensions to tune in order to get a higher breakdown characteristic and a
lower ON-resistance simultaneously.
In terms of maximum frequency figures, this device does not outperform others because of all the parasitic capacitances associated to it. The gate oxide capacitance, one
of the important ones, scales with the device size if this is scaled for power purposes.
LDMOS
The major disadvantages of VDMOS transistors arise from their physical layout.
Having the drain connected at the bottom of the device and the source at the top
causes serious technical issues. The drain contact has to be isolated from the grounded
metal carrier of the package by using an insulating material (typically Beryllium
Oxide), which is toxic and costly. The device source contact has to be connected to
the grounded package lead by means of bonding wires (see Fig. 3.11a). This causes
a parasitic inductance at source, and hence a drop in the device gain and frequency
response (for the classic common-source configuration). As a result, DMOS transistors
64
Figure 3.11: Packaging DMOS devices: drain has to be isolated in VDMOS (a), source
connected straight onto the metallic carrier in LDMOS (b)
were only used commercially for applications up to 1 GHz [71].

With the emergence of the lateral version of the DMOS (LDMOS), these problems
were overcome. As it can be observed in Fig. 3.11b, the drain contact is at the top
of the device, which suppresses the use of an insulator. Additionally, the source,
which is at the top, is also connected to the bottom of the device by means of a p+
sinker or a trench etched through the epitaxial layer. This will connect the devices
backside straight to the package metal carrier, and hence no grounding bonding wires
are needed. On the other hand, due to its physical structure, this device would
exhibit less intrinsic parasitic capacitances (Cgs, Cds) than VDMOS, hence providing
a higher operating frequency.
LDMOS can be pictured as a VDMOS but rotated 90. As such, it has all the
distinct features of the latter, which are high breakdown voltage and high frequency
response. This is obtained by providing separate regions for the device channel and
the breakdown region.
This device is fabricated on a highly doped (low resistivity) p-substrate, which is
used also as good quality ground plane. A low-doped p-type layer is then grown
on top of the substrate (see Fig. 3.9b). This light doping allows reduction of the
output capacitance Cds and increase of the breakdown voltage. The active area is
built within this epitaxial layer. The device channel is formed first by implanting
a p- base, which is self-aligned to the poly-gate boundary. The p- base is diffused
under the gate and sets the drain limit of the channel. Then, the n+ source contact is
implanted and also self-aligned with the same gate boundary. The source implant is
activated, however the diffusion is less than in the p- base. The difference in this lateral
diffusion becomes the device channel [72]. This form of building the device channel
allows getting short channels without having the lithography with the corresponding
resolution. Only careful process control is required. For instance, a channel length of
0.3 m can be obtained from a 1.5 m process. On the other hand, to make a device
65

that withstands high voltages, the drain has to be separated from the gate. Extending
the drain with a lightly doped n-drift region attains this. The goal of this drift region
(once it is depleted) is to distribute the electrical field around the drain side of the
gate, before impact ionization takes place [72]. Hence, typically these devices exhibit
a minimum breakdown voltage of 65 V for 28 V DC bias operation, and a minimum
breakdown voltage of 120 V for 50 V DC bias operation. Another remarkable feature
of these devices is the inclusion of some sort of Faraday shield, obtained by extending
the source metallization over the gate (see Fig. 3.9b). This minimizes the feedback
capacitance Cgd between the gate and drain metal [73].
The operation of these devices is similar to VDMOS and conventional MOSFETs.
Applying a positive voltage at the gate causes the formation of a depletion region and
conductive channel (inversion layer) afterward. The channel is so short that electrons
are always at saturation velocity [72]. Once the electrons leave the channel region
they flow over the n drift region and reach the drain terminal. This transit time in
the drift region is one of the limiting factors for high frequency operation.
LDMOS devices have replaced Si BJT and GaAs MESFET/HEMT in the cellular
base station amplifiers, covering more than 90% of this market nowadays. They are
found in 800/900 MHz (cellular/GSM), 1900 MHz (PCS) and 2100 MHz (WCDMA)
base stations. They can reach peak powers (P1dB) around 160 W [74] in these
applications. Ultimately, they have extended to the WiMAX arena, covering the 2.7
GHz and 3.5 GHz bands with output power around 75 W [74].
3.4.3
SiGe HBT
The SiGe HBT technology, developed in the late 1980s, combines the best of two
worlds: the high transport characteristic and flexibility of the heterojunction structures and the high yield, integrability and low cost of CMOS structures. It has become
a tough competitor to legacy GaAs RF technology, but mainly in low voltage applications. In that sense, it becomes a good candidate for replacing mobile PAs fabricated
in GaAs. The integration of SiGe HBTs with the conventional Si CMOS processing
gave rise to the BiCMOS processing technology, initiated by IBM [75].
In order to shed some light on this technology a quick review of the BJT (npn-type)
operation will be presented next. The BJT operation is based on the formation of
depletion regions at the collector-base (CB) and base-emitter (BE) junctions (see
Fig. 3.12a). These regions have an associated intrinsic potential that prevents the
flow of carriers over these regions. Nevertheless, this barrier can be varied by applying biasing at these junctions. Hence, if an inverse biasing voltage is applied at the
junction CB, the depletion region and the electrical field in it will increase. This electric field will attract some electrons from the base, making them to reach the collector
terminal. Anyhow, this produced current will be very low due to the intrinsically low
concentration of electrons in the p material. This scenery will change completely
66
Figure 3.12: BJT basic operation (a) SiGe HBT bandgap diagram (b)
67

when a forward-biasing voltage is applied at the junction BE, in which case a flow
of electrons will be supplied from the emitter to the base. These electrons will be
driven by the electric field of the CB junction, from the base to the collector, causing
a collector current. In the ideal case, all these electrons would reach the collector
terminal. However, some of them will recombine with the holes injected at the base
terminal. This recombination can take place in the base area, in the depletion EB
region or even in the emitter region when some holes diffuse into this region. This
account of recombination-holes becomes the base current. Anyway, this current is
a small fraction of the total emitter/collector current. The mechanism of providing
a large current at collector/emitter by injecting a small current in the base is the
typical characteristic of this type of transistor. This feature is measured in terms of
current gain (Ic/Ie). As can be inferred from the above description, this gain depends
mostly on the doping level of the emitter and base regions. In order to maximize
the gain, either the emitter doping has to be increased (increment of free electrons)
or the base doping decreased (reduction of recombination). The former has a limit
in the dopant activation2 , conventionally in the range of 1 2 1020 cm3 . The
latter would lead to a poor high frequency response due to the increase of the base
resistance. In this regard, it can be established that the cut-off frequency depends on
the depletion capacitances (EB and CB) as well as the transit time in the depleted
and non-depleted regions. All these factors have to be minimized in order to improve
the frequency response.
SiGe heterostructures came up as a solution to the issues presented for conventional
Si BJT devices. The Si material in the BJT base is replaced by a SiGe alloy in
the new device. This gives rise to a heterojunction between the Si emitter having a
bandgap of 1.12 eV and the SiGe base with a smaller bandgap (depending on the Ge
concentration). Since the lattice constant of the SiGe is larger than Si, the SiGe base
layer has to be strained (see Fig. 3.13b). Due to the different valence and conduction
bands of the heterojunction Si emitter/SiGe base (see Fig. 3.12b), electrons flowing
from the emitter to the base have to surpass a smaller energy barrier (0.02 eV for
Si0.85 Ge0.15 ) than holes moving from base to emitter (0.105 eV for Si0.85 Ge0.15 ).
Hence, the detrimental hole injection from base to emitter is highly reduced. This, at
the same time, allows increasing the base doping (lower base resistance) and narrow
its dimension, which leads to a shorter transit time in the base. On the other hand,
if the Ge content is graded across the base, having a maximum at the collector side,
then the bandgap is also graded but having a minimum at the collector side. As
a result, a built-in field is formed which accelerates the electrons going through the
base, further reducing the transit time.
The advantage of an increasing doping level at the SiGe base does not come without
cost. The boron dopant is diffused out of the SiGe layer during subsequent thermal
annealing3 cycles. This brings up a reduction of the current gain and cut-off frequency.
2 Thermal treatment causing release of a free electron (or hole) after dopant has been implanted
in the semiconductor.
3 Annealing is a heat treatment wherein a material is altered. Silicon wafers are annealed, so that
68
Figure 3.13: Boron diffusion in a SiGe layer with and without Carbon (a), lattice structure
(b)
Nevertheless it was found that by incorporating small amounts of carbon doping into
the SiGe epi layer, the boron out-diffusion can be reduced or effectively suppressed
[76, 77] (see Fig. 3.13a). As a result, the latest commercial SiGe technologies include
carbon doping (known as SiGe:C, or just SiGeC) as a necessary step to obtain high
yields (fT > 100 GHz).
Besides placing SiGe at the base and narrow it, this type of devices exhibit also
a collector with high doping level in order to reduce the base-collector depletion
region4 . This results in higher frequency characteristics because of the reduction
of the base-collector transit time. However, this brings up a high electric field in
the narrow space charge region, which leads to higher impact ionization factors and
therefore lower breakdown voltages [56]. As a result, typically very high frequency
SiGe transistors exhibit very low breakdown voltages (see Fig. 3.14 [78]). This last
factor is a remarkable obstacle for their use in power amplifier designs at very high
frequencies. However this does not limit their growing use in RF block circuits such as
low-noise amplifiers, oscillators, pre-amplifiers, mixers, etc. for applications such as
GSM, CDMA, Bluetooth, GPS, SONET, and so forth. Furthermore, the latest FCC
mandate to incorporate localization capabilities into the cellular mobiles in the USA,
dopant atoms, usually boron, phosphorus or arsenic, can be incorporated into substitutional positions
in the crystal lattice, resulting in drastic changes in the electrical properties of the semiconductor.
4 also known as space-charge region
69
3.5. GaN technology and devices
Figure 3.14: SiGe HBT cutoff frequency vs. breakdown voltage
pushes the integration of GPS and GSM/CDMA into one chip [79]. SiGe appears to
be a prominent technology to carry out this challenge with optimal yields and costs.
3.5
GaN technology and devices
Power amplifiers at RF frequencies demand devices with high breakdown voltages

or/and high current capabilities. The latter is usually achieved by placing several
devices in parallel, which increases the total width (or periphery) of the transistor.
However, this results in a very small matching resistance and the use of ballasting
resistors [70] for BJT/HBT structures. Under these conditions, devices exhibiting
high breakdown voltages become a more attractive solution. It has been already presented that the LDMOS transistor can fulfill this condition, and it is currently widely
used in cellular base stations. Nevertheless due to limitations in its technology and
structure, its frequency range is limited up to approximately 5 GHz. In this context,
GaN technologies appear as prime competitors showing high breakdown voltages as
well as higher frequency ranges. The latter comes from the implementation of GaN
device as a HEMT structure. This was realized at the beginning of the 1990s [80, 81].
The principle of operation of a GaN HEMT is slightly different from the GaAs described in section 3.3.2. In GaAs, a heterostructure composed of an n-doped layer
and an undoped channel layer gives rise to the formation of a 2 DEG layer of electrons, which can move swiftly through an ions-free undoped region. The conduction
band energy of the doped layer must be higher than the undoped region to make this
70
Figure 3.15: GaN basic structure [80]
possible. This conduction band offset stimulates the transfer of the electrons from
the n-doped region to the undoped layer. These electrons are confined in a very narrow region close to the heterojunction (2DEG). Hence, the donor of the doped layer
becomes the source of electrons, which is not the case in the GaN HEMT. In its basic
form, a GaN heterostructure is composed of undoped AlGaN and GaN layers (see
Fig. 3.15), with the former having higher conduction bandgap energy than the latter,
similar to the GaAs device. Nevertheless, in the GaN case both layers can be made
of intrinsic materials (undoped). The 2DEG layer comes mainly from a polarization
effect instead of a doping characteristic. Both bulk materials AlGaN and GaN are
pyroelectric5 material showing strong spontaneous polarization. Furthermore, AlGaN
exhibits larger polarization than GaN. On the other hand, AlGaN has a smaller lattice
constant than GaN, so it is strained to fit the lattice structure. This strain causes an
additional polarization component called piezoelectric6 polarization. The conjunction
of spontaneous and piezoelectric polarization produces a large positive sheet charge
at the heterojunction. Due to this, electrons tend to neutralize this charge by forming
a 2DEG thin layer in the GaN material adjacent to the heterojunction. Hence, it can
be deduced that the source of electrons does not come from a doped layer, but from
another source, which has been identified to be the natural donor-like surface states.
In brief, it can be established that due to the polarization features, it is feasible to
produce a 2DEG with high charge density in AlGaN-GaN heterojunction without any
intended doping process. This is a sui generis characteristic of the GaN HEMT.
In terms of carrier velocities, this device exhibits high saturated velocity comparable
with Si and GaAs, but relatively moderate electron mobility (see Table 3.1). The
5 Temperature
dependence of the spontaneous polarization in certain anisotropic solids. As a

result of a change in temperature, positive and negative charges move to opposite ends (i.e., the
material becomes polarized) and hence, an electrical potential is established.
6 Ability of some materials to generate an electric potential in response to applied mechanical
stress. All pyroelectric materials are normally piezoelectric as well.
71

Table 3.1: Comparison of material properties [82]
Property
Bandgap (eV)
Relative Dielectric Constant
Breakdown Field (MV/cm)
Saturation Velocity (cm/s)
Electron Mobility (cm2 /Vs)
Thermal Conductivity (W/cm-K)
Si
1.11
11.8
0.6
1x107
1350
1.5
GaAs
1.43
12.8
0.65
1x107
8500
0.46
4H-SiC
3.2
9.7
3.5
2x107
800
4.9
GaN
3.4
9.0
3.5
2.5x107
1200-2000
1.7
former feature is a characteristic of the bulk material, while the latter is a characteristic of the 2DEG carriers. This 2DEG electron mobility is not mainly dependent
on doping concentration, but on the 2DEG sheet density. In order to obtain high
frequency figures of merit (fmax and fT ), it is required that both velocity figures are
large. That is why these devices show relatively lower fmax and fT compared with
legacy technologies, such as GaAs. A comparison with this technology for the same
gate length can be observed in Fig. 3.16a. GaN HEMTs exhibiting an fT of 121
GHz (gate length=0.12 m) and fmax of 195 GHz (gate length=0.15 m) have been
already reported [80].
As a consequence of its wide bandgap characteristic (see Table 3.1), a GaN device
exhibits a high breakdown field and can withstand high operating temperatures. As
it can be observed from table 3.1, the breakdown field of GaN is about six times
higher than the one of Si and GaAs. This means that these GaN devices can withstand larger voltages, and therefore provide higher output power per mm of device
periphery. Furthermore, the wider the bandgap, the higher the critical temperature,
hence these devices can be operated at much higher temperatures compared with
their Si and GaAs counterparts. Besides its intrinsic high breakdown field, field plate
(FP) techniques [83] (used already in LDMOS) have been applied in GaN technology
to reach very high breakdown voltages. Available commercial GaN devices exhibit
VDSS breakdown voltages of 84 V (Cree) and 120 V (Eudyna) for drain bias of 28
V and 48 V/50 V respectively. Along with the high breakdown voltage, large output power density (W/mm) is accounted for these devices, as it can be observed in
Fig. 3.16b. Typical values of 10 W per mm gate width can be observed for this technology, which is approximately one order of magnitude higher than the conventional
GaAs technology.
Until a few years ago, GaN substrates have not been available. Therefore, sapphire
and SiC have been commonly used substrates for the growth of GaN epitaxial layers.
Nevertheless there is an important mismatch between the lattice constants of GaN
and the substrate materials just mentioned. The lattice mismatch is around 30%
between GaN and sapphire, while it is only 3.4% between GaN and SiC. Additionally, the thermal expansion coefficient mismatch between sapphire and GaN is larger
than between SiC and GaN, and therefore lower dislocation density is expected for
processing on SiC. Furthermore, the thermal conductivity of SiC is much higher (see
72
Figure 3.16: GaN fT compared with GaAs (a) and GaN output power density for sapphire
and SiC substrates (b) [80]
Table 3.1) than for sapphire (0.23 W/cm-K). So a better heat transfer between device
and substrate is provided for SiC. In Fig. 3.16b, the power densities obtained using
sapphire and SiC are compared as a function of frequency. The advantage of SiC over
sapphire is clear. Given all these facts, SiC is the preferred wafer material instead of
sapphire [80, 81]. Nevertheless, sapphire is preferred in some cases for its lower cost
and larger wafer availability. In recent years, GaN growth on Si substrates has been
reported [84, 85]. This is an attractive option given the low-cost, high-performance
and moderate thermal conductivity of the Si bulk.
A typical structure for a GaN HEMT can be observed in Fig. 3.15. The layer structure
consists of a nucleation layer, a GaN buffer/channel layer, an AlGaN barrier layer and
a cap layer. On top of this structure, Ohmic contacts for the source and drain are
located, as well as the Schottky gate contact. The cap layer is made of undoped GaN
or AlGaN material. The subsequent AlGaN barrier layer has an Al content typically
between 0.15 and 0.3 and can be doped or undoped as described earlier. The GaN
layer consists of the actual channel layer and a thick buffer layer. The nucleation
layer is required to control the polarity of the GaN and AlGaN layers, as well as to
carry out a monocrystalline growth of these layers despite the large mismatched with
sapphire or SiC substrates. First GaN devices suffered from high Ohmic drain/source
contact resistance of several ohms. This was due to the lack of a proper metal (an
associated work function [81]) that can go on top of such a wide bandgap material.
Currently, this is resolved by the use of a composite metal stack of Ti/Al/Ti/Au,
which gives a low resistance of about 1.25 mm [81], or less [80]. The gate contact
is made of Ni/Au and can be either rectangular or mushroom shaped. Although it is
not indicated in Fig. 3.15, the device fabrication is completed with a deposition of a
Si3 N4 passivation layer. This layer is critical in eliminating the dispersion between
the large AC and DC drain current. Measurements under large RF input drives show
73
3.6. Technologies and applications
Figure 3.17: GaN structure showing traps (a) current collapse (b)
a significant reduction in drain current compared to the DC value. This leads to an

increase of the ON resistance (and therefore knee voltage [83]) as well as an output
power compression. This dispersion effect is called current slump or current collapse
(see Fig. 3.17). This should not be confused with the self-heating effect. It has been
identified that this current slump takes place due to the presence of traps on the
surface of the gaps between the metal contacts, as well as in the region below the
gate. Between these two types of traps, surface traps seems to be the dominant ones
[81], although this is still under discussion [80].
3.6
Technologies and applications
A chart, indicated in Fig. 3.18 and based on [86], shows the main commercial wireless
applications nowadays and the forthcoming ones. The described technologies in this
chapter are shown as well. This chart is not specifically for RF power amplifiers,
but it covers radio frequency (RF) and analog-mixed signals (AMS). The boundaries
indicated in this chart are not fixed, but diffuse and variable in time. Since most of
the applications presented are mass market oriented, cost factors play a crucial role at
the time of choosing a technology. Multiple alternatives are available for frequencies
up to 10 GHz. Si and SiGe are not expensive and have exhibited an astonishing
increase in fT and fmax in recent years, hence these technologies tend to dominate the
spectrum until 10 GHz. On the other hand, III-V compound semiconductors (GaAs,
InP) are the dominant technologies for frequencies above 10 GHz, despite them being
74
3.6. Technologies and applications
Figure 3.18: RF technologies and applications
more expensive. This is due to their important figures of merit like relatively high
breakdown voltage, cut-off frequency and noise figure.
Narrowing the application spectrum to the specific case of RF power amplifiers, two
scenarios should be considered. Power amplifiers, aimed for base stations, exhibit different technical specifications than the ones used in portable terminals. For instance,
the output power ranges are quite different. A portable terminal typically has an
amplifier with an output power around 1 W, it is normally biased at 3 V and draws
the power from a battery. The output power of a base station is in the range between
20 W and 100 W or above. The bias voltages are normally 28 V or 48 V, and these
are provided by a DC power supply plugged to the electrical network.
At the onset of the mobile communications, the base station amplifiers were designed
with Si BJT and GaAs MESFET [32], then they were replaced by Si LDMOS for
applications up to 2 GHz. Low cost and technological maturity were the key factors of
Si LDMOS success. With the emerging of WiMAX at 3.5 GHz, Si LDMOS appeared
as a good competitor to win the supremacy for this application. However, GaAs
HEMT and GaN HEMT are expected to be interesting technological solutions as
well. The drop in power efficiency and density of Si LDMOS PAs at 3.5 GHz plays
in favor of GaAs technologies, although the latter are more expensive. GaN HEMT
amplifiers exhibit even higher power density than GaAs amplifiers and are already
commercially available, but their MTBF (Mean Time Between Failures) and reliability
are still under discussion [87]. Power compression over time is one of their major issues.
GaAs technologies have unquestionable optimal figures of merit and are mature but
cost issues could restrain their use in mass-oriented applications like WiMAX.
Power amplifiers for mobile terminals are battery operated, so a low knee voltage is
75
3.7. Conclusions
a prime requirement to have an acceptable power efficiency figure. Unlike the base
station amplifier case, GaAs was the technology used from the onset and is still the
prime technology for portable devices nowadays. GaAs HBTs are mainly used instead
of GaAs HEMTs because the former can work with a single voltage bias and exhibit
better linearity figures. By the time the cellular market was starting up, GaAs technology was virtually the only technology for RF circuits, however, at present several
solutions exit. Driven by cost factor and technological improvements, major efforts
have been realized to provide SiGe and Si CMOS power amplifier modules that could
compete with GaAs amplifiers. They are commercially available as samples and are
still under evaluation [62, 86]. On the other hand, due to the proliferation of many
standards and bands for cellular communications, power amplifiers solutions have to
adapt to these new requirements. Then, compared to initial solutions which were
based on single package devices and RFICs, nowadays multi-band multi-mode power
amplifier modules become available. These PA modules integrate most of the matching and bias networks, and could also provide power detection, power management
and RF switches [86].
At the millimeter wave range (starting from 30 GHz), the alternatives to realize power
amplifiers are reduced to InP and GaAs technologies. Between these two technologies,
the GaAs pHEMT is the dominant one for frequencies less than 77 GHz [86]. Despite
the fact that these technologies are the most optimal at high frequencies, they also
face challenges for the uppermost frequencies ranges. Power amplifiers require the
conjunction of high breakdown voltage and current gain at any frequency range. At
the highest frequency ranges, GaAs pHEMTs provide acceptable breakdown voltages
but with limited current gain, and InP HEMT exhibit adequate current gain but
with low breakdown voltage. Then the challenge is to engineer a device featuring
acceptable voltage and current gain at the same time. In this regard, the mHEMT
technology raises as a very interesting approach [32, 62]. This device structure exhibits
the best trade-off between the high voltage feature of GaAs pHEMT and large gain of
InP HEMT. Alternatively, the GaN technology is also a good candidate to compete
with legacy GaAs and InP at millimeter wave ranges. As it was already described,
this technology exhibits impressive power density figures due to the combination of
extreme breakdown voltage and high current density. Nevertheless, reliability figures
have to be guaranteed first. Major efforts are being carried out in that direction
nowadays [87].
3.7
Conclusions
The physics principles and main features of GaAs HEMT, Si CMOS/LDMOS, SiGe
HBT and GaN HEMT technologies have been presented. Although these do not cover
the total universe of alternatives for designing an RF power amplifier, they cover most
of the used technologies nowadays. While in recent years Si technology has been taken
over a number of roles or functions performed exclusively by III-V technologies before
76
3.7. Conclusions
(for instance mixers, local oscillators and filters), this is not completely the case in
the RF power amplifier area. This demands high voltage/current and frequency capabilities at the same time. The trade-off between voltage and frequency capabilities
of Si technology restrains its applicability in RF power amplifiers at high frequencies
starting around 5 GHz. Nevertheless, in the mass-market context, cost is a major
driving force and a key factor at the time of choosing a technology. Hence, despite
the intrinsic breakdown limit of Si technology, a new Si device type was engineered
in order to overcome this limitation. As a result, Si LDMOS was created and became
the de-facto technology for cellular base stations, replacing GaAs technology. The
same cost factor might also push GaAs mHEMT as the preferred technology instead
of legacy InP at the very upper frequency range. On the other hand, reliability and
maturity are factors that prevent GaN to make a breakthrough in the market. However, once these factors are resolved, this technology still has to prove being better
and more cost-effective than its predecessors, namely Si LDMOS and GaAs. GaN
technology may have more success in military applications. A similar scenery can be
observed nowadays with Si CMOS and SiGe BiCMOS RF amplifiers, which are struggling to replace and displace well-established GaAs technologies in mobile handsets
power amplifiers. Observations on technology evolution and history may lead to the
conclusion that despite the improved characteristics of a specific technology, this may
never hit the market. It is very difficult to break up the status-quo or inertia of the
market. To achieve this, the synergy of many factors is required. The technological
one is, most of the times, not sufficient.
77
Chapter 4
High efficiency RF power

amplifier
4.1
Introduction
The fundamental concepts presented in chapter two will be applied in this chapter to
design RF class E power amplifiers. Furthermore, this will imply the utilization of
a specific device technology, which features have been already described in chapter
three. The limitations and/or advantages of a specific technology will be plausible
during the design process and in the final results. Since the technique described in
chapter two has been based on idealization and simplification of a device model (ONOFF model), final performance could show large error margins. Furthermore this
will increase with the operating frequency. Some attempts to correct this technique
involve the addition of more elements to the ON-OFF model, for instance the inclusion
of device ON-resistance, current fall time and/or non-linear intrinsic capacitances. In
particular, the latter has been considered in recent techniques which propose new class
E design equations. Despite these equations lead to a more complete methodology, it
still lacks complete accuracy. This will be demonstrated in this chapter by resorting
to the concept of harmonic orthogonality.
4.2
From lumped components to transmission line

class-E power amplifier
The basic theory for the class-E power amplifier has been developed in chapter two,
section 2.6.2. The basic circuit is repeated in Fig. 4.1a as a reference. In this circuit,
79
4.2. From lumped components to transmission line class-E power amplifier
Figure 4.1: Class-E power amplifier based on lumped components (a), and on transmission
lines (b)
the switch operation is realized by a transistor operating alternatively in the cutoff and saturation regimes. The capacitance Cout is considered to be linear. The
resonant network (Co Lo ) is tuned to the operating frequency, and the optimal load
composed of RL and jXL assures that the class-E operation conditions are fulfilled.
These conditions are:
a) Zero-voltage switching (ZVS) in the device terminal from off to on,
b) Zero-voltage-derivative switching (ZVDS) in the device terminal from off to on.
Under these conditions, the overlapping of the current and voltage waveforms is always
zero. This implies that the power dissipation is zero and the output power is equal to
the DC power, hence that the highest efficiency is obtained. Based on the ZVS and
ZDVS conditions, closed relationships to calculate the value of each of the network
elements have been already determined in chapter two, section 2.6.2. These are
repeated in Table 4.1, along with the maximum ratings for this type of amplifier.
Alternative formulas can be found in [17, 18, 21] that take into account the loaded
quality factor of the network in a more precise way, but for the purpose of this section
the tabulated equations are sufficient.
It is important to notice that by the time this type of amplifier was proposed [15],
the frequency range of the applications was in the order of a few MHz. Then, many
assumptions for the device model and network were valid for those ranges of frequencies. Over-driving the device in cut-off and saturation region would make it behave as
an ideal switch. The equivalent capacitance was given by the intrinsic capacitance of
the device plus an external capacitance. By looking at the formula of Cout , it can be
deduced that this together with the bias voltage determines the output power. The
device breakdown defines the bias voltage, implying that this value is fixed. Therefore
the only way to increase the power was by increasing the equivalent capacitance. Nor80

Table 4.1: Class E design values and maximum ratings
design element
value
maximum ratings
value
Cout
0.32Pout
2
VDD
vSmax
3.56 VDD
RL
2
0.58VDD
Pout
iSmax
2.86 IDD
XL
2
0.66VDD
Pout
fmax
0.018iSmax
Cout VDD
Lo
QL RL XL
Co
1
2 L0
Pout
2
3.14 VDD
Cout
mally this would imply a large value of external capacitance in shunt with the intrinsic
one. As a result, the value of the intrinsic capacitance was negligible in comparison
with the external capacitance. Hence, the net capacitance could be assumed linear.
Moreover, the parasitics resulting from the connection of the extrinsic capacitance to
the device are negligible for this range of frequencies.
On the other hand, the load RL found by the equation in Table 4.1 normally does not
match with the impedance of the transmission line or antenna, hence an impedance
transformation network was needed. This would imply the use of at least two more
lumped components (L-C network) [7, 68]. This transformation network brings up
losses in the output power, which increase with the transformation ratio [68].
With the increase of the frequency, the parasitic elements of each of the lumped
components become more relevant. The winding capacitance of the inductor can
not be neglected, neither can the resistance of the windings. Likewise, capacitors
exhibit inductive parasitics and resistive losses. At the end, these elements turn into
a resonant circuit with a self-resonant frequency typically lower than 1 GHz. This also
means for instance that an inductor behaves as a capacitor at frequencies higher than
its self-resonance. As a result, the basic circuit shown in Fig. 4.1a transforms into
a complex network with unexpected results. Nevertheless, optimization procedures
or methodologies have been applied in order to take into account all these parasitic
effects [43, 68] and still obtain high efficiency figures. On the other hand, the accuracy
of these lumped element models is only guaranteed over a certain frequency range.
For instance, Murata and Panasonic capacitor models are usually valid from 300
kHz to 6 GHz. In practice, the lumped-element methodology with optimization has
been applied until frequencies of approximately 2 GHz . At microwave frequencies
a method based on transmission lines has been applied successfully until frequencies
around 10 GHz. This will now be described in further detail.
81
4.2.1
Transmission line-based class-E power amplifier
This method transforms the classical class-E theory given in the time domain into
the frequency domain [23, 24]. A transformation plane can be defined after the
capacitance Cout (see vertical dotted line in Fig. 4.1a). At this plane, the impedance
(Zopt ) seen into the class-E network can be defined as
Zopt =
vS
iRF
(4.1)
where vS is the switch voltage and iRF is the current going through the class E
network. The expressions for these variables have been already defined in chapter
two, section 2.6.2 and are repeated here:

iRF () = IDD
(
vS () =
IDD
Cout
2 cos()

sin( + )
2cos()
0,
(4.2)
0 < ;
< 2
(4.3)
The angle is constant and equal to 0.57 rad. for the optimal class-E amplifier.
Since the quality factor of the resonant network is infinite, only one harmonic current
component is present in the expression for iRF , as is also verified in equation (4.2).
Hence, if the harmonic components of the switch voltage vS can be found by a Fouriertransformation, the harmonic components of the impedance can be determined as
F{vS }k
F{iRF }k
Zoptk =
(4.4)
with k being the frequency index.

The current IRF has only one non-zero component at the fundamental, the rest of the
components are zero, therefore the impedance becomes infinite at these harmonics.
This gives the following expression:
(
Zoptk =
0.28ej49
Cout ,
k = 1;
k 6= 1
(4.5)
This last formula is the main formula for designing class-E amplifiers at microwave
frequencies. It implies the use of a network based on transmission lines (see Fig. 4.1b)
such that Cout sees the harmonic impedances indicated in equation (4.5). If these
82
Figure 4.2: Simulated Class E waveforms using a non-linear FET model
frequency-domain conditions are fulfilled, it will imply that in the time-domain, ZVS
and ZDVS conditions are fulfilled as well.
Unlike in the lumped-component case, the output capacitance is only the devices
intrinsic capacitance. This is because the introduction of an external capacitance can
not be accomplished without the addition of parasitics associated with the connection.
This will degenerate the performance of the class-E amplifier. An advantage of this
configuration is that the transmission line network is built considering a 50 load.
Then a transformation network will not be required, as in the lumped-component
case. On the other hand, the maximum ratings indicated in Table 4.1 are still valid
in this case.
The theoretical waveforms are similar to the lumped components configuration. However, when first simulations were performed utilizing an actual non-linear model, two
major differences were observed, as reported in Fig. 4.2. The first one is the non-zero
voltage during ON period. This is associated to the intrinsic resistance of the device,
which causes a non-zero voltage during saturation. The resulting power loss can be
estimated by using the formulas developed in [24, 16]. Secondly, class-E theory assumes a negligible drain/collector current fall-time or virtually equal to zero ps in the
transition ON-OFF. This is not the case as can be observed in Fig. 4.2. This may
be associated to the transit time in the transistor. However, this is discarded given
that this is in the order of picoseconds. After performing additional simulations, it
turned out to be the rise and fall times of the sinusoidal excitation signal. This effect
can be reduced by using a square or trapezoidal signal instead of a sinusoidal one
[88]. Alternatively, when a sinusoidal signal is employed, it has to be very high such
that its transitions reduce and the signal behaves as trapezoidal one. This brings up
a drop in PAE although an increase in drain efficiency. The best solution is to use
a pre-amplifier that squares the sinusoidal wave. This could be implemented as a
83
4.3. 2 GHz SiGe class-E amplifier

Table 4.2: BFP620 Technical specifications
Parameter (maximum ratings)

Collector-emitter voltage (VCEO )
Collector-base voltage (VCBO )
Emitter-base voltage (VEBO )
Collector current (IC )
Base current (IB )
Cut-off frequency (fT )
Value
2.8 V
7.5 V
1.2 V
80 mA
3 mA
65 GHz
class-F amplifier.
The number of harmonics to be controlled in class-E is usually only one or two (second
or third harmonic). This is because Cout will short out the higher components of Vs
at microwaves frequencies. Alternatively, there exists a similar methodology known
as harmonic manipulation (HM) [11, 12, 89] that works with one fundamental and
one or two harmonics as well. This method also has shown high output power and
drain efficiency, although its operating principle is different from class-E. On the other
hand, it could happen that at certain very high frequencies it would not be possible
to control the second and third harmonic, because they are zero. Then, the point
would be whether it makes sense to construct a class-E or HM PA controlling only
the fundamental component, for instance at frequencies above 10 GHz. All indicates
that class-E or HM PA loose sense under this scenary.
In the original work [23, 24] about the transmission line-based class-E method, equations were proposed to define the length and characteristic impedance of the transmission lines indicated in Fig. 4.1b). Nevertheless, this configuration and solution is
not unique, and alternative configurations can be proposed to provide the required
impedances. This will be shown in the class-E amplifiers developed in this thesis,
which will be discussed in the next sections.
4.3
2 GHz SiGe class-E amplifier
It has been described in chapter three, section (3.4.3) that SiGe arose as an interesting RF technology due to its high cut-off frequency and compatibility with CMOS
processing (BiCMOS), although it exhibits low breakdown voltages. The purpose of
the design described below was to verify the suitability of this technology for class-E
power amplifiers at a testing frequency of 2 GHz. The device found in the market,
by the time this design was realized, was an Infineon Technologies BFP620 packaged
transistor. This transistor is a SiGe HBT encapsulated in a SOT343 package. The
main characteristics of this device can be found in Table 4.2. A Gummel-Poon model
for the device and lumped-component model for the package (valid up to 6 GHz) are
also provided in the datasheet.
84

A first design parameter that can be defined straightforwardly is the collector bias.
The maximum VCE is 2.8 V and using the corresponding formula from Table 4.1 a
bias of 0.75 V should be used. However, this bias value can be slightly higher giving
the fact that this value is calculated at DC and assuming the base is open, which does
not coincide with the actual device operating conditions (RF and base connected).
At the end, by testing, it was verified that 1 V can be used as collector biasing. The
base current bias was set slightly above cut-off (40 A), such that an offset voltage is
not necessary to compensate the built-in voltage of the junction base-emitter.
The second step in the design process is to determine the output capacitance of
this device for class-E operation. The non-linear model does not provide this type
of information, furthermore it involves non-linear capacitances. Then a small-signal
model was constructed in order to determine the output capacitance. A first detail
to be defined is for which bias point to do the extraction. Normally this is not
indicated in publications. Furthermore, the transistor switches between cut-off and
saturation constantly. Nevertheless, by recalling the mathematical procedure for classE amplifiers in chapter two section 2.6.2 it can be noticed that the output capacitance
value enters in the calculation in the cut-off condition. As a result, the capacitance
at that condition was used as a reference for the output capacitance.
The model constructed in the cut-off condition is indicated in Fig. 4.3a. The device
intrinsic model includes the silicon substrate losses [90], which is a key element for
the correct extraction of the model. The initial values of the package model were
obtained from the devices datasheet. The initial values for the intrinsic capacitances
were obtained from the values at 1 MHz provided by the manufacturer. Finally all
these elements were optimized to fit the S-parameter measurements of this device
at cut-off condition (IB = 0 mA, VCE = 0.75 V ). S-parameter measurements were
performed at the microwave laboratory and were compared with the ones provided by
the manufacturer, giving very similar results. The test fixture for the device testing,
which is also used in the design, will be explained in chapter five, section (5.3.1).
Once the optimization process was completed, the values indicated in Fig. 4.3a were
used as final values for the model. However, this model is too complex to be used in
the transmission line class-E design methodology. This model had to be reduced or
simplified. Then, after performing some calculations and approximations, a simpler
circuit could be obtained and this is reported in Fig. 4.3b. This is valid up to approximately 5 GHz. This was enough to control at least one harmonic, besides the
fundamental component. An interesting remark about this simplified model is that
the output capacitance value (0.12 pF) coincides with the value of Ccb given by the
manufacturer at lower frequencies (f req = 1 MHz, VCB = 2 V ). Furthermore, Ccb
is used directly as output capacitance in [91] about frequency-approximation class-E
design.
In the original paper [23], equations were formulated for one stub class-E matching.
Since the transistor model could not be reduced to only an output capacitance as
in the original work [23], this procedure could not be applied. However, the target
85
Figure 4.3: SiGe small-signal model: complete version (a) simplified version (b)
Figure 4.4: Double-stub SiGe HBT class-E amplifier: layout (a), physical realization (b)
86
Figure 4.5: SiGe HBT Class E measured performance
at this stage is clear and consists in finding a network that provides the following
impedances at the intrinsic output capacitance plane:
(
Zoptk =
0.28ej49
Cout
= 186 ej49 ,
at 2 GHz;
at 4 GHz
(4.6)
Due to the complexity of the network, an optimization procedure was utilized to find
the correct matching. A first solution considering two transmission lines and one stub
was considered. Nevertheless the impedance of the transmission lines were too low
(31 ) to be implemented in a Rogers substrate RO3010 (635 m of thickness and
electrical constant of 10.2). For this substrate, impedances between 40 and 100
were feasible. Then a solution with two transmission lines and two stubs was chosen
and proved to be physically implementable (see Fig. 4.4). For this design, CPW was
chosen as transmission line type since it would make the testing easier and allow the
direct use of GSG Picoprobes probes.
The solution shown, in Fig. 4.4, was optimized using ADS Momentum software. On
the other hand, bridges were necessary to connect the ground planes of the CPW stub,
such that the even non-TEM mode or slotline modes would be suppressed [92, 93].
Unlike the conventional air bridges used in MMICs, these bridges were implemented
by using metalized via holes and a back layer.
The final performance of this SiGe Class-E amplifier is reported in Fig. 4.5. A maximum PAE of 49.7 % with an output power of 2.65 dBm was obtained for this amplifier. Although a fair efficiency is obtained, the output power is very low compared
to the maximum output power that this device can provide (11 dBm according to
87
4.4. X-band GaAs class-E power amplifier

the datasheet). The problem can be understood if the theoretical class-E maximum
power and current are calculated using the equations from Table 4.1:
2
Pout = 3.14 VDD
Cout = 4.73 mW = 6.7 dBm
iSmax = 2.86 IDD = 2.86 (3.14 VDD Cout ) = 13.5 mA

This theoretical output power is small due to the low DC bias, as it depends on the
square of this value. Moreover, the maximum current excursion (13.5 mA) is also small
compared to the maximum current available from this device (80 mA). This means
that the current capability of the device is wasted. Unless the bias voltage is increased,
the output power and current would remain small. This is an actual limitation for
this new low voltage technology with high frequency response, but small breakdown
voltages. Another way to increase the power and current figures would be to increase
the intrinsic capacitance, although this is not feasible for a packaged device. Even if
this were possible, this capacitance can not be increased without restraint, because
the maximum class-E frequency (see Table 4.1) would limit this value. Alternatively,
class-E differential and complementary configurations could be used to increase the
output power [43, 68, 88].
4.4
X-band GaAs class-E power amplifier
Despite the SiGe technology shows cut-off frequencies close to or comparable to the
value for GaAs technology, its low breakdown voltage limits its applicability for RF
power amplifiers. GaAs technology is the preponderant technology in this area which
will be shown with the design of a class-E power amplifier at 9.6 GHz (X-band) [94].
For this design, a 0.5 m GaAs pHEMT device (1500 m gate periphery) has been
adopted, provided by Selex Sistemi Integrati (Italy). The device exhibits a breakdown voltage and maximum current of 18 V and 400 mA respectively. It has been
characterized and modeled by a non-linear neural network model [95] developed at
the University of Rome Tor Vergata.
The DC operating point is set close to pinch-off (Vpinchof f =-0.9 V) and has been
tuned taking into account stability considerations and maximum allowable drain voltage (Table 4.1), resulting in a gate voltage of -0.8 V and a drain voltage of 5 V.
The output capacitance is composed of the intrinsic device capacitance plus an additional external capacitance. Usually the latter is added in order to achieve a target output power, but this will decrease the frequency range for class-E operation.
Therefore, for high frequency applications, this capacitance is reduced basically to
the intrinsic output capacitance. Moreover, for sake of simplicity, the device output
88
Figure 4.6: Voltage/current waveforms and dynamic load line for two power levels obtained
by direct calculation (a) and class-E mode tuning (b)
capacitance has been assumed linear. Actually, the non-linear output capacitance can
be represented equivalently by a linear capacitance for Class-E design purposes [96].
The value of this output capacitance can be defined by small-signal extraction at cutoff or by a load-line method [97] (if a non-linear model is available). It is determined
that the value of this capacitance is approximately 0.32 pF for this device.
Given the high operating frequency for this amplifier, the first condition to be verified
is the applicability of the optimal class-E condition at this frequency. Then by taking
the corresponding formula in Table 4.1, the maximum frequency for this condition
can be determined
fmaxclassE =
0.018 iSmax
= 4.5 GHz
Cout VDD
(4.7)
This indicates that it is not possible to realize an optimal class-E operation at 9.6
GHz, which means that the amplifier can only be designed to operate in a sub-optimal
class-E mode or properly speaking in a class C-E operation [98]. Given this scenery,
two procedures were investigated in [94] to find the harmonic loads to realize a class-E
amplifier.
A. Direct calculation
This procedure neglects the limitation indicated in equation (4.10) and applies the
conventional equation (4.5) to calculate the harmonic loads. Therefore the following
89

Table 4.3: Comparison of simulated performance based on the X-band class-E procedures
Method
Direct Calculation
Class-E Mode Tuning
Output Power (dBm)

26
22
(%)
43
28
PAE (%)
35
12
values are to be considered

(
Zoptk =
0.28ej49
Cout
= 14 ej49 ,
at 9.6 GHz;
at 19.2 GHz
(4.8)
B. Class-E mode tuning

This procedure can be applied as far as a good non-linear model for the device is
available. It is based on ZVS condition fulfillment. The values calculated by the
previous method are used as starting values and it is also taken into account that
the phase of this should be higher than 49 because of the capacitances non-linearity
[99]. Subsequently, an optimization of the fundamental load is performed until a zero
voltage value at the drain is reached at the on-off transition. Then the harmonic load
values that lead to ZVS are found:

Zopt =
20 ej80 ,
,
at 9.6 GHz;
at 19.2 GHz
(4.9)
Based on the values obtained in the above procedures, the corresponding output
matching networks were designed using transmission lines. The network presented
at the drain node is such that the optimal impedance value (method A or B) at the
fundamental frequency is realized, and high impedance (virtually an open circuit) is
set at the second harmonic. Higher harmonics (28.8 GHz) were not considered since
the device does not exhibit any current gain at those frequencies.
The input matching for both methods has been defined by determining the complex
conjugate of the impedance seen at the gate terminal.
Simulated voltage and current waveforms, using the harmonic balance analysis tool
of ADS, are shown in Fig. 4.6 for these two circuit designs. It can be observed that
the direct calculation method does not guarantee a ZVS condition fulfillment, while
on the other hand, the second method shows this condition. The load lines can also
be obtained based on these waveforms and are shown as well.
It was expected that the second design method (class-E mode tuning) would perform
better than the first one (direct calculation), since the losses at the off-on transition
are minimized. The actual results (see Table 4.3) however show that the output power
and efficiency of the first design are relatively better than the second one. This result
90
Figure 4.7: X-band GaAs class E power amplifier layout, designed employing direct calculation method
reflects the preponderant effect of the devices on-resistance and non-zero current fall
time on the efficiency and output power of a ZVS-based class-E power amplifier at
high frequencies. This may lead us to conclude that ZVS is not the exclusive factor
that necessarily leads to high efficiency. Alternative strategies could be used in order
to get high efficiencies at these frequencies as well [89].
An important remark about the Class-E mode tuning is that this procedure was
realized using a sinusoidal excitation, while the original class-E proposal [15, 16]
considered a square wave excitation, i.e., with zero transition time.
Clearly it can be stated that the design using direct calculation does not fulfill the
class-E principles of ZVS and ZDVS. Nevertheless the harmonic loads were found
based on the class-E frequency approach. As a result, some researchers considered
this as a class-E amplifier. Moreover in [100, 91] it is proposed to use a set of harmonic
loads (load circles) found by load pull simulations as class-E solutions where output
power could be traded in for efficiency. At this point, we are reluctant to consider this
type of frequency solution as a class-E amplifier without first verifying its behavior
in the time domain. Nevertheless, for this design, the frequency domain concept has
been assumed neglecting the time domain behavior. This allows comparing this work
with other research works.
Since the first design provides the best performance, the MMIC layout for this circuit
has been developed and simulated. The input and output matching networks have
been realized using radial stubs, which allow to save some space in comparison with
the transmission line stub solution. Due to the same restriction, /8 transmission
lines have been used to bias the device. The effect of these lines on the matching
has been considered in the design of the matching networks. The capacitor-via hole
set is tuned to resonate at the operating frequency, providing a short circuit at this
91
Figure 4.8: 9.6 GHz GaAs class-E PA performance (a) and comparison with state of the art
X-band class-E PA (b). Ref: (1)[101], (2)[102], (3)[103]
frequency, which is necessary for the /8 transmission line. Additional work was
performed to keep the device and the amplifier stable over a broad frequency range,
since it became conditionally stable over a range of frequencies around the operating
frequency. Such stabilization was realized by using a shunt gate resistor of 32 . This
resistor is decoupled also by the capacitor-via hole set at the operating frequency.
The resulting amplifier layout, realized following Selex (former AMS) MMIC process
design rules, is reported in Fig. 4.7. The simulated performance figures are depicted
in Fig. 4.8a.
Additionally, it has been noticed during the design process that given an optimal classE output matching network, the final performance of the amplifier could be improved
by controlling the second harmonic of the input matching circuit [11, 12, 89]. As it
was mentioned previously, the first harmonic is fixed to the complex conjugate of the
devices input impedance (gain maximization).
As can be noted a simulated output power of 27 dBm with a drain efficiency of 55 %
has been obtained. This can be compared with the results available in literature, as
reported in Fig. 4.8b. Unfortunately this MMIC amplifier was not fabricated due to
logistic issues, so measurement results can not be provided.
In comparison with the SiGe HBT class-E PA presented in section 4.3, this amplifier
works at a higher operating frequency (5 times higher) and with larger output power
(two orders of magnitude larger). Although this comparison is not completely valid,
it sheds some light on the discussion why this technology is the de-facto technology
for RF power amplifiers nowadays.
92
4.5. 2.4 GHz GaN class-E power amplifier
4.5
2.4 GHz GaN class-E power amplifier
GaN technologies have drawn a lot of attention in recent years due to their outstanding
breakdown voltage and output power density. This associated with a HEMT device
structure gives the right combination for high output power at high frequency, as it
was already described in chapter 3 section 3.5. A sample of this capability is shown
by the design of a 2.4 GHz GaN class-E power amplifier, described next.
This amplifier has been designed for C-band application, by using an Al0.5 Ga0.5 N/GaN
HEMT with 1 mm gate periphery (10x100 m gate fingers) provided by Selex. This
device exhibits a breakdown voltage of 70 V and a maximum current of 400 mA. It
has been modeled by an Angelov model [104, 105].
In this case, due to the high breakdown voltage characteristic of the GaN device, its
drain bias was fixed to 20 V and the gate bias was fixed to -3 V, which is close to
cut-off condition.
The output capacitance is reduced to the intrinsic capacitance and it can be calculated
based on the S-parameters at cut-off or by using a load-line method. Due to the
availability of the model, a load-line method was utilized. The value inferred in this
case was 0.23 pF.
Initially, the operating frequency for this design was set at 5.5 GHz. When first
simulations were performed the load line obtained for class-E was the one indicated
in Fig. 4.9a. As it can be observed, the current excursion exceeds the maximum
current limit. This gave a first indication that the amplifier can not operate in optimal
conditions at that frequency. By recalling the equation for maximum current in classE operation from Table 4.1,
iSmax = 2.86 IDD = 2.86 (3.14 VDD Cout ) = 9 VDD Cout
we see that the only way to decrease the current is by decreasing the biasing or
the frequency. The capacitance can not be reduced, because it corresponds to the
devices intrinsic part. Reducing the bias voltage is not a good alternative for this
type of device, because the effect of the high knee voltage on the effective voltage
excursion would be more deleterious. Then the only remaining option was to reduce
the operating frequency. As a result, the operating frequency was set at 2.4 GHz.
With this new operating frequency, the load line is within the cut-off and saturation
region, see Fig. 4.9b.
Knowing the DC characteristics and output capacitance, the maximum class-E operating frequency can also be calculated
fmaxclassE =
0.018 iSmax
= 1.56 GHz
Cout VDD
93
(4.10)
Figure 4.9: Load line for class-E operation at 5.5 GHz (a) and at 2.4 GHz (b)
This frequency is lower than the chosen operating frequency, which leads to the conclusion that the class-E operation that can be obtained will be sub-optimal. As it has
been described in subsection 4.4, the direct calculation procedure can provide a fairly
good solution even if the ZVS condition is not fullfilled. Looking for ZVS could even
lead to a poor efficiency under sub-optimal operation.
Based on these considerations, the harmonic loads can be calculated to be
(
Zopt =
0.28ej49
Cout
= 80.7 ej49 ,
at 2.4 GHz;
at 4.8 GHz
(4.11)
The implementation of this amplifier is in a hybrid-circuit format, which, for this

case, consists of the GaN chip fixed to a metallic carrier (heat dissipater) and wire
bonded to Alumina boards containing the input and output matching networks (see
Fig. 4.10a).
The Alumina board to be used for the input and output matching networks has predefined dimensions: 4.5 mm x 7.5 mm. Therefore the minimization of the physical
dimension of the matching layout became critical and it was realized by using radial
stubs and bended transmission lines.
The bias network was embedded in the matching layout by using a short-circuited
stub and 100 pF MIM decoupling capacitors. The latter are mounted on the metallic
carrier and wire bonded to the end of the stub (see Fig. 4.10a).
The stabilization of the device and amplifier were realized using series and shunt gate
resistors (both resistors were needed). These resistors are thin film resistors. Since the
region of stabilization includes the operating frequency, the efficiency of the amplifier
is unavoidably decreased.
The time-domain voltage and current waveforms of this amplifier (based on layout
component models and simulations) can be observed in Fig. 4.10b. One characteristic
noticed in suboptimal operation is that the maximum voltage does not reach the
94
Figure 4.10: Block diagram of GaN class E power amplifier (a) and simulated time domain
waveforms (b)
Figure 4.11: 2.4 GHz GaN class-E power amplifier (a) and S-parameter simulation and
measurement (b)
typical 3.5 VDD value [98]. This can be observed also in the simulation, as the device
reaches only 50 V, given that the maximum is 70 V. On the other hand, as it was
already observed in section 4.4, the ZVS condition is also not reached in this case.
This amplifier was physically implemented and assembled by U. Roma Tor Vergata
[106]. S-parameter measurements were performed at the beginning to verify the device
operability and performance under small signal excitation. The results reported in
Fig. 4.11 present auspicious agreement between simulation and measurements for the
class-E bias point VDS = 20 V and VGS = 3 V. This gives an indication of the
satisfactory response of the matching boards and the device model for this specific
bias and small signal excitation. Nevertheless, under large signal excitation, the
actual power and efficiency figures reported in Fig. 4.12, exhibit some remarkable
disagreement. This is more notorious for the first bias point than for the second one.
This leads to conclude that there is an important inaccuracy in the non-linear model
for the largest excursions. However, a drain efficiency of 55% (PAE of 44.3%) was
95
4.6. Class-E with non-linear capacitance
Figure 4.12: 2.4 GHz GaN class E power amplifier performance with VGS = 3 V and
VDS = 20 V a), and with VGS = 2.8 V and VDS = 15 V b)
obtained with an output power of 31.6 dBm. This output power was about 9 dB
higher than the values reported in earlier works [107, 108] for this type of technology.
4.6
Class-E with non-linear capacitance
Initial closed-form equations derived for class-E operation [16], in chapter 2 section
2.6.2, assumed that the capacitance Cout (see Fig. 4.1a) is linear, which is the case
at low frequencies where the external capacitance is much larger than the intrinsic
one, giving as a result a net linear behavior. At very high frequencies, however,
the capacitance Cout is composed solely of the device intrinsic capacitance, since the
addition of external capacitance would decrease the maximum operating frequency
(The maximum operating frequency in class-E mode is inversely proportional to the
shunt capacitance Cout ). Furthermore, for most devices this intrinsic capacitance
changes with the voltage across it. Therefore, new methods taking into account
the non-linearity of this capacitance were established. The first one [109] solved
the problem for a particular abrupt junction transistor output capacitance (grading
coefficient= 0.5) and later on for a grading coefficient in the range from 0.5 to 0.75
[99]. The first method will be described next.
In order to illustrate the variations in the design equations and in the class-E maximum ratings due to this non-linearity, the results for a class-E power amplifier with
a non-linear capacitance of grading coefficient 0.5 will be shown. The corresponding
formula for Cout can be established as
Cout = r
Cjo
1+
96
vs
Vbi
(4.12)
Figure 4.13: Class-E with non-linear capacitance (a), time domain waveforms for =0.57
rad (b)
where Cjo is the shunt capacitance at switch voltage vS = 0 and Vbi is the built-in
potential.
The procedure in this case will follow the same lines as the linear capacitance case
(see chapter two, section 2.6.2). Since the circuit analysis for this case is similar to
the linear case, the following expressions can be formulated (see Fig. 4.13a)
iCAP () = Cout

iS () =
0,
IDD Irf sin( + ),

iCAP () =
dvS
d
IDD Irf sin( + ),

0,
(4.13)
0 < ;
< 2
(4.14)
0 < ;
< 2
(4.15)
Replacing the value of Cout in equation (4.13) by equation (4.12)

iCAP () = r
Cjo
vS
1+
Vbi
dvS
d
(4.16)
Then using equation (4.15) and (4.16), the value of vS can be determined, with the
boundary condition vS (0) = 0
97
vS () =
Vbi
0,

IDD Irf (cos(+)cos)

2Vbi Cjo
+1
2
1 ,
0 < ;
(4.17)
< 2
Applying the zero voltage switching (ZVS) condition to the last expression, the following relationship is established

Irf = IDD
2 cos
(4.18)
This is similar to the linear case. Actually the ZVS condition is equivalent to state
that the integral of the capacitor current is zero during a signal period. Since the
current expression for the non-linear and linear case are similar, the same relationship
for Irf and IDC hold.
Substitution of equation (4.18) into (4.14) and (4.17) yields the following expressions
iS () =
vS () =
0,
0 < ;

IDD
Vbi
0,

2 cos sin( + )
2 cos
IDD (2cos+(cos(+)cos))
4Vbi Cjo cos
< 2
+1
2

1 ,
(4.19)
0 < ;
< 2
(4.20)
These are the basic equations for class-E operation with non-linear capacitance and a
grading factor of 0.5. Similar to the linear case, there are several solutions depending
on the value of . Among these, there is one considered the optimal case and it is
defined based on the Zero Derivative Voltage Switching (ZDVS) condition. The value
corresponding to this condition can be found as
dvS ()
|= = iCAP () |= = 0
d
(4.21)
Solving this equation for the angle , gives the solution =0.57 rad. This value
coincides with the optimal value in the linear case. This can be understood since
the current expressions for linear and non-linear capacitances are similar. One set
of voltage and current waveforms corresponding to the optimal case for non-linear
capacitance is shown in Fig. 4.13b.
98

It is assumed in [99, 109] that since the overlapping of the Vs and Is waveforms is
zero (switching losses equal to zero), this amplifier is 100% efficient. Therefore it is
established that
PDC = IDD VDD = Pout =
2
Irf
RL
2
(4.22)
Using this last equation and (4.18) the value of IDD can be solved
IDD =
8 VDD
cos2
2 RL
(4.23)
Then the output power can be defined as
Pout =
2
8 VDD
cos2
2 RL
(4.24)
From this last expression the value of the optimal RL can be derived for =0.57 rad.
This value coincides with the value found in the linear case and it is already indicated
in Table 4.1.
Unlike the linear case, where the output capacitance Cout is determined, in this case
the capacitance Cjo is defined. To this purpose, it has to be considered that the DC
drop at the choke inductor LRF C is zero, then
VDD =
1
2
Z2
vS ()d
(4.25)
Using this last equation and (4.20), (4.23) the capacitance Cjo is solved
Cjo =
12sin2 Vbi sin
6Vbi (sin2 (24Vbi 24 2 VDD + 4 VDD ) + 6 2 VDD )

12RL Vbi
(4.26)
This value is a design parameter used when a transistor is tailored for a particular
class-E power amplifier application. If the transistor design can not be modified
according to equation (4.26), this could serve to find the optimal transistor bias given
a specific frequency and load.
The output voltage vo () plus the fundamental component of the voltage across the
reactance XL can be expressed as
99
Figure 4.14: XL /RL ratio versus DC supply voltage for different built-in voltages
v1 () = Vo sin( + ) +
XL Vo
cos( + ) = V1 sin( + 1 )
RL
(4.27)
where
s
V1 = Vo
1+
XL
RL
2
(4.28)
is the amplitude of v1 , and
1 = + tan
XL
RL

(4.29)
Since the reactance of the resonant circuit Co Lo is zero at the fundamental frequency
1
0=
Z2
vS () cos( + 1 ) d
0
Then, this equation can be solved for 1 , giving the following expression
100
(4.30)
Figure 4.15: Normalized maximum switch voltage versus VDD for different built-in voltages
1 = tan
2(48 Vbi Cjo + IDD + 6 2 Vbi Cjo )

5 2 IDD + 24 Vbi Cjo 32IDD

(4.31)
Then the reactance XL can be calculated from equation (4.29), which gives
XL = RL tan(1 )
(4.32)
A plot of the reactance XL versus the DC voltage for various degrees of nonlinearity
Vbi , is shown in Fig 4.14. The condition Vbi = corresponds to the case of linear
capacitance. As it can be observed, the typical phase of 49 (XL /RL ' 1.16) of the
optimal load for the linear case is not longer applicable in this case. This angle is
higher than 49 depending on the DC voltage and the non-linearity factor Vbi .
Also the maximum switch voltage defined as 3.5VDD is no longer valid for the nonlinear case. The waveform vS given by equation 4.20 implies a new maximum. This
peak voltage can be found considering that it occurs when
dvS ()
= iCAP () = 0
d
Using equations (4.15) and (4.18), the angle that maximizes vS () is solved
101
(4.33)
4.7. Harmonic orthogonality analysis of class-E amplifiers
V smax = 2
(4.34)
Then this angle is substituted in equation (4.20) to find the maximum switch voltage
Vsmax =
IDC
Cjo

IDC
2
Cjo Vbi
(4.35)
This value normalized with respect to VDD is shown in Fig. 4.15 for various values of
Vbi and VDD . It can be observed that there is a remarkable increase of the maximum
switch voltage compared tp the linear case.
Although this theory has been proved by experimental results [99, 109], it is not completely accurate. It lacks a frequency analysis that backs up the initial assumption of
DC power equal to output power due to the zero time-domain waveform overlapping.
This will be analyzed in the next section.
4.7
Harmonic orthogonality analysis of class-E amplifiers
Until this point of the thesis, it has been established that class-E power amplifiers
provide 100 % efficiency because there is no overlapping between the current and the
voltage time-domain waveforms, i.e., there is zero device power dissipation. Nevertheless, a further frequency-domain analysis [89] states that the condition for 100%
efficiency requires the previous time-domain condition plus the orthogonality of the
current and voltage harmonic components higher than the fundamental frequency.
In this section, this harmonic analysis for the typical class-E PA with linear output capacitance will be presented and extended to the study of the class-E PA with
non-linear output capacitance. According to the analysis presented in [110], the latter case does not fulfill the orthogonality condition and therefore can not provide
100 % efficiency despite the fact that class-E conditions are fulfilled and that the
current/voltage waveform overlapping is zero.
In order to understand the concept of harmonic orthogonality, a power balance analysis of the amplifier is necessary. This is shown in Fig 4.16. In this figure, the following power components are identified: Input power (Pin ) and output power (Pout,f )
components at the fundamental frequency. Harmonic output power (Pout,h ), that corresponds to the power of the harmonic components, different from the fundamental,
present at the output of the amplifier. Finally, DC power (PDC ) and power dissipated
in the device (Pdiss ) are the last power components. The dissipated power at the gate
(Pdiss,G ) is negligible.
102
Figure 4.16: Power balance of an amplifier
Based on these components, the power balance equation of the amplifier can be established
Pin + PDC = Pout,f + Pout,h + Pdiss + Pdiss,G
(4.36)
Considering a unilateral device, the input power Pin is dissipated at the gate and is
equal to Pdiss,G . Perfect input matching is assumed, as well, in order to have zero
reflected input power. Then equation (4.36) can be rewritten as
PDC = Pout,f + Pout,h + Pdiss = Pout,f +
Pout,kf + Pdiss
(4.37)
k=2
Applying this equation to the the drain efficiency concept
Pout
P
P out,f
=
PDC
Pout,f + k=2 Pout,kf + Pdiss
(4.38)
Therefore, in order to obtain 100 % drain efficiency, i.e., PDC = Pout,f , the following
two conditions should be met:
1. The dissipated power must be equal to zero.
103
Pdiss
1
=
T
ZT
(vS (t) iS (t))dt = 0
(4.39)
This means zero overlapping of the drain current and voltage waveforms in the time
domain.
2. The power in the harmonics must be equal to zero.
Pout,kf =
k=2
1X
|V sk | |Isk | cos(k ) = 0
2
(4.40)
k=2
where k is the frequency index, |V sk | and |Isk | are the magnitudes of the Fourier
transform of the voltage vS and current iS , and k is the phase difference between
these two components.
Then in order to have these harmonic components equal to zero, there are two alternatives:
1. |V sk | or |Isk | is zero, this condition corresponds to the class-F or inverse class-F
amplifier, in which either even or odd harmonics are null.
2. The angle k is an integer multiple of 90, this condition would correspond to
the class-E amplifier.
The last condition is what we propose as harmonic orthogonality condition for 100%
efficiency in class-E operation. To be more specific, when the harmonic orthogonality
condition is mentioned, it will refer to the harmonic orthogonality condition from the
second harmonic on.
This orthogonality condition can be verified (straightforwardly) by using any of these
two methods:
Method 1. Extracting the harmonics components of the switch voltage and current
by Fourier-series calculation and examining if these components are 90 out of phase.
This is also equivalent to state that the harmonic impedances have a phase of 90.
Zsk =
V sk
Phase(Zsk ) = k =
Isk
2
(4.41)
Method 2. Using a relationship established by B. Molnr [111] and generalized later

on by A. Teledgy et al. [112]
104
Pout = P1B
1
=
2
Z2
vS0 i0S d
(4.42)
where P1B is the power at the fundamental frequency and vS0 and i0S are the derivative
of vS and iS with respect to the angle variable . This relationship is valid only if
harmonic orthogonality condition is fulfilled. The advantage of this method is that
it does not require the calculation of all the harmonic components, but only the
fundamental component. This power should be equal to the integral indicated above
in order to guarantee the orthogonality condition fulfillment.
Given these methods, the orthogonality condition will be analyzed for the classical
class-E configuration with linear and non-linear capacitance.
4.7.1
Class-E with linear shunt capacitance
In order to perform the analysis, the basic time domain waveforms vS () and iS ()
should be recalled from chapter two, equations (2.38) and (2.39):
(
iS () =
(
vS () =
IDD
Cout
0 < ;
0,
IDD

2cos()sin(+)
2cos()
2cos()
0,
< 2
,

0 < ;
< 2
(4.43)
(4.44)
These two equations are sufficient to analyze the orthogonality condition. It should be
noticed that the class-E ZVDS (zero voltage derivative switching) condition has not
been used, keeping the analysis more general. The application of the ZVDS condition
leads to the particular case = 32.5.
The first method will be applied in this case, i.e., if the harmonic impedances have
90 phase, then the voltage and current components are orthogonal. Considering
the complex Fourier-series coefficients of the waveforms iS () and vS () as Isk and
V sk , the harmonic impedances are calculated as follow
Zsk =
V sk
Isk
(4.45)
After performing calculations by employing the symbolic calculation tool of Maple,

the following result is obtained
105
Figure 4.17: Time-domain voltage and current waveforms, and phase (in degrees) of the
harmonic impedances corresponding to class-E with linear capacitance
Zsk =
1
Cout
1
Cout k
( 2 8)cos()+j 2 sin()
j( 2 +8)cos() 2 sin() ,
k=1
2(k2 1)(1(1)k )cos()k2 (1+(1)k )sin()+jk(1+(1)k )cos()

j2(k2 1)(1(1)k )cos()k2 (1+(1)k )sin()+k(1+(1)k )cos()
k2
(4.46)
A quick examination of these expressions reveals that the phase of all the harmonics
higher than the fundamental is -90. Then the orthogonality condition is fulfilled for
all these harmonics.
For illustration purposes, Fig. 4.17 shows the phase of the impedance harmonic components (in terms of index k) corresponding to the linear case with VDD = 3 V ,
f req = 5.25 GHz, Cout = 0.32 pF , and = 52.5.
4.7.2
Class-E with non-linear shunt capacitance
The waveform equations (4.19) and (4.20) developed in section 4.6 will be used in this
case.
106
Figure 4.18: Class-E waveform with non-linear capacitance (a), the voltage and current
switch derivative (b)
For the orthogonality analysis the second method will be considered, since the first
one is more cumbersome mathematically.
As it was stated above, we have the condition that if the components are orthogonal
then the power corresponding to the fundamental harmonic should be equal to the
power defined by equation (4.42). The fundamental power is calculated based on the
complex Fourier coefficients as follow
P1 =
1
Re {V sk=1 Conj(Isk=1 )}
2
(4.47)
where V sk=1 and Isk=1 are the complex coefficients of the Fourier-series corresponding to the fundamental of the switch voltage and current.
The calculations are performed again by using a symbolic calculation program, giving
the result indicated in the following equation
P1 =
2
IDD
[192 2 Vbi Cjo sin() cos() + 584 IDD cos2 () 608 IDD ]
2 2 V
384 cos2 () 2 Cjo
bi
(4.48)
In order to apply equation (4.42), a graph showing the general class-E waveforms
for = 52.5 and their derivatives is shown in Fig. 4.18, where dV s1 and dV s2
are the switch voltage derivative values at the transition times, and 1 and 2 are
the switch current values at the transition times. It is not difficult to see that the
derivatives of the switch current (dIs1 and dIs2 ) are equal to the jump in current at
the transition multiplied by the Dirac delta function. Likewise, the switch voltage
derivative corresponds to the capacitance current divided by Cjo
107
Figure 4.19: Time-domain voltage and current waveforms, and phase (in degrees) of the
harmonic impedances corresponding to class-E with non-linear capacitance [113]
ICAP () = r
Cjo
vS
1+
Vbi
dvS
iCAP () |=0,
dvS
=
|=0, =
d
d
Cjo
(4.49)
The following relationships can be inferred

iCAP ()
Cjo
(4.50)
iCAP (2)
iCAP (0)
=
Cjo
Cjo
(4.51)
dV s1 =
dV s2 =
1 = Is () = dIs1 = Is () ()
(4.52)
2 = Is (2) = Is (0) = dIs2 = Is (2) (2)
(4.53)
Applying the above quantities to the equation (4.42), and taking into account equations (4.15) and (4.18)
108
P1B
1
=
2
Z2
vS0 i0S d =
1
I 2 tan()
(dV s1 1 + dV s1 1 ) = DD
2
2 Cjo
(4.54)
A simple observation of the equations (4.48) and (4.54) is sufficient to draw the
conclusion that these expressions do not match and that the orthogonality condition
can not be fulfilled for this non-linear case. This means that a certain amount of power
is always consumed in the harmonic components and therefore 100 % efficiency can
not be obtained. For this reason also, the classical equation establishing the equality
of the DC power consumption and the power of the first harmonic (fundamental) can
not hold in this case. Equations (4.48) and (4.54) become equal for the trivial case
IDD = 0, i.e., zero output power.
In order to verify the non-orthogonality conclusion, harmonic analysis is applied to
previous research works with non-linear capacitance. For instance, Fig. 4.19 shows the
phase of the impedance harmonic components corresponding to the work published
in [113]: VDC = 3 V , f req = 5.25 GHz, Cjo = 0.32 pF , Vbi = 0.7 V and = 32.5
(class-E optimal case, ZVDS condition is fulfilled).
The phases of the impedances are different from 90, nevertheless it can be observed
that at very high frequencies, the phase of the harmonic impedances tends to 90.
The analysis has been applied for a non-linear capacitance with a grading coefficient of
0.5, but similar results can be obtained for other grading coefficients. As an example,
Fig. 4.20 shows the results obtained based on the data provided in [99] for a grading
coefficient of 0.77, VDC = 2 V , f req = 900 M Hz, Cjo = 40.3 pF , Vbi = 1 V and
Po = 1.25 W . Here also, the phase of the harmonic impedances is different from
90. Unlike the case with a grading coefficient of 0.5, the phase of the harmonic
impedances does not converge to -90.
In conclusion, it has been demonstrated that the 100% efficiency condition established
for the classical class-E configuration with linear output capacitance, is not guaranteed
automatically in the case of a non-linear output capacitance. To check whether the
orthogonality condition is fulfilled, a harmonic analysis should be conducted. It is
shown that unlike the linear capacitance case, the orthogonality condition is not
held in case of a non-linear junction capacitance with a grading coefficient of 0.5.
Consequently, it cannot be established automatically that the DC power is equal to
the output power in case of non-linear output capacitance, since a certain amount of
power is dissipated in the higher harmonics. Nevertheless, for the case with grading
coefficient of 0.5, this condition can be applied as an initial approach taking into
account that the higher harmonic impedance phase tends to be -90 and therefore
induces minimal losses.
109
4.8. Linearity of class-E power amplifier and EER technique
Figure 4.20: Time-domain waveforms and phase (in degrees) of the harmonic impedances
corresponding to class-E with non-linear capacitance [99]
4.8
4.8.1
Linearity of class-E power amplifier and EER

technique
Class-E amplifier linearity
Linearity and class-E amplifier are antagonist terms. As was described, class-E amplifier works in cut-off and saturation regime in order to obtain high efficiency figure.
However, the linearity of the amplifier, when operating in this regime, is the poorest.
As a result, this type of amplifier is targeted to amplify signals with constant-envelope
signal, by which information is transmitted in the phase/frequency of the carrier (for
instance GSM signals). Nevertheless, outside the high efficiency region, i.e., in the
medium and low power region, the class-E amplifier behaves as an arbitrary amplifier.
It is biased in class-AB operation with a particular load, which is not the conventional
one used for class-AB amplifiers. Hence, the linearity of the class-E amplifier can be
assessed in this region and compared with the conventional class-AB amplifier. It has
to be remarked that the class-E amplifier principle does not apply in this region of
low and medium power, but for comparison purposes let us assume that it will be
employed in those regions.
The class-E and class-AB amplifier designs described in chapter six, section 6.3 are
utilized to evaluate the linearity of the former and compare it with the latter. These
amplifiers employed the same device (Filtronics FPD750) and operate at the frequency
of 3.5 GHz. The third order intermodulation product and intercept point are reported
110
Figure 4.21: Measured intermodulation products and intercept point for class-AB power
amplifier VDS = 8.3 V, VGS = 0.8 V (a) and class-E power amplifier VDS = 5.15 V, VGS =
0.8 V (b)
in Fig. 4.21. The excitation signals are two tones with frequencies of 3.4999 GHz and
3.5001 GHz and the input power is swept from -3 dBm to 17 dBm. Unexpectedly, both
amplifiers result approximately in similar values of OIP3 (31 dBm) and IIP3 (21 dBm).
This comes from the fact that the typical slope 3:1 of the third order intermodulation
product has to be fitted at small power levels and that both amplifiers have the
same gate bias voltage. Another 3:1 slope line could be defined in both graphs at
different power levels, which would result in different OIP3 and IIP3 [114]. However,
strictly speaking these slope lines have to be set at small input powers as the ones
indicated in the plots. Under this consideration, the effect of the higher harmonics and
distortion, appearing at medium to higher power levels, are neglected. As observed
in Fig. 4.21, the level of the third order intermodulation product is higher in class-E
than in class-AB over the range between 5 dBm and 17 dBm of input power. A
better way to characterize this non-linear behavior is by recurring to IMD3. At the
1 dB compression point, the IMD3 values are -25 dBc and -20 dBc for the class-AB
and class-E amplifier respectively, which reveals the actual linear behavior. A more
accurate way to compare the linear performances of these amplifiers is by using actual
RF signals (for instance IEEE 802.16e), as will be shown in chapter six, section 6.3.3.
All these tests confirm the low linearity performance of the class E amplifier.
Despite the class-E amplifier is driven in a linear region, its performance is lower
than the conventional class-AB amplifier. The time domain waveforms of the class-E
amplifier are already distorted under low/medium power due to its particular load,
which is sized for high efficiency at high output power.
111
Figure 4.22: Envelope Elimination and Restoration (EER) technique
4.8.2
Class-E amplifier linearity in EER configuration
The non-linear and high efficient class-E amplifier can be linearized by employing
the Envelope Elimination and Restoration (EER) technique. This allows that nonconstant envelope signals can be applied. A basic diagram of this technique can
be observed in Fig. 4.22. The non-constant envelope signal is decomposed into two
components: magnitude and phase components by employing an envelope detector
and limiter respectively. The phase information is applied to the class-E amplifier.
The magnitude information modulates the bias of the class-E amplifier (by means of a
DC-DC converter or class-S modulator). The conjunction of these two effects results
in an amplified replica of the input signal. However, this linearization process is not
perfect and suffers non-linearity imperfections, which will be described next.
Initial linearity assessment of this technique by using intermodulation products was
reported in [115]. This first analysis neglects any non-linearity effect of the class-E
amplifier and established that the major sources of non-linearity were the bandwidth
of the DC-DC converter and the time delay between the phase and amplitude components. The bandwidth of the DC-DC converter should be at least twice the bandwidth
of the RF signal and the time delay should not exceed one-tenth the inverse of the
RF signal bandwidth. Furthermore, the frequency of the switching amplifier (DCDC converter or class-S modulator) should be typically six times the bandwidth of
the RF signal [29]. On the other hand, an RF delay line must be introduced in the
lower path of the EER when this exceeds the limit mentioned earlier. Alternatively,
instead of changing the drain bias according to the signal envelope, this can be varied
following the rms (or average) value of the envelope signal. This technique is known
as (average) Envelope-Tracking (ET) and has the advantage of avoiding the use of
an RF delay line and requiring lower switching frequency compared with the EER
technique [116]. Additionally, the ET technique utilizes a linear amplifier instead of a
switching amplifier. As a result, a limiter circuit is not required in the ET technique.
112
Figure 4.23: simulated VDD/AM a) and VDD/PM b) characteristics of class-E power amplifier
Initial investigation of the non-linear effect of the class-E amplifier in EER technique
was reported in [117]. It was established that even with a perfect supply modulation,
amplitude distortion can be caused internally by the class-E amplifier, due to the
effect of the output load network. Recent investigations [118, 119, 120] characterize
this behavior by measuring the output amplitude of the class-E amplifier versus the
drain bias. Hence, AM/AM (VDD/AM) and AM/PM (VDD/PM) conversion figures
can be established. It was reported [118] that the AM/AM characteristic is mainly
non-linear for small drain bias, i.e., at low input power; whereas considerable AM/PM
distortion is observed over the whole range of drain bias. This behavior can be
observed in Fig. 4.23 as well, which corresponds to the simulated VDD/AM and
VDD/PM of the class-E amplifier mentioned earlier. The non-linear capacitances
and dispersion effect of the transistor are responsible for this behavior. As a result,
an additional linearization technique (for instance pre-distortion) may be applied to
correct the intrinsic non-linear effects of the class-E amplifier in EER technique.
A final aspect of this EER technique is its efficiency. This depends mainly on the
efficiency of the power amplifier and the efficiency of the envelope amplifier (DCDC converter). Current OFDM applications such as IEEE 802.16 and IEEE 802.11g
exhibit channel bandwidths in the range of 10 or 20 MHz. This would demand DCDC converters with switching frequencies of about 60 or 120 MHz. The latter could
introduce significant switching losses (which increase with the switching frequency),
degrading the overall efficiency [121]. A trade-off between efficiency (low switching
frequency) and linearity (high switching frequency) shows up in this technique. Once
more, this can be reduced by employing additional linearization techniques [118].
Based on this study, it could be argued that employing class-E amplifier in EER
configuration may not be an optimal solution without the use of an external linearizer.
Furthermore, the latter would make the solution more complex and less efficient.
Nevertheless, the low cost, high-speed processing and compactness of current DSPs
could guarantee the feasibility and applicability of this technique. An alternative
solution would be to employ class-E amplifier in linear amplification using nonlinear
113
4.9. Conclusions
components (LINC) technique, although this still has to be further investigated.
4.9
Conclusions
In this chapter, the design, simulation and measurements of high frequency class-E
power amplifiers have been shown utilizing different types of device technologies. To
this purpose, the transmission-line based class-E methodology has been applied. This
technique is the translation from the time-domain class-E into the frequency domain,
and therefore it inherits all the benefits and restrictions of the original technique.
Particularly, the maximum frequency of operation of class-E is a serious restriction
for its applicability at very high frequencies. However its use has been extended even
in this high frequency region, exceeding in this way the theoretical frequency limit.
Furthermore, legacy formulas are still applied in this frequency range giving fairly
good results. This approach is what we called direct method. Looking for the basic
ZVS condition may lead to detrimental results in these frequency ranges. Class-E
operation in these ranges is said to be operation in sub-optimal conditions or also
class-C-E or class-B-E operation.
The frequency class-E approach has been based on a very simple ON-OFF model of
a device and considering only a linear output capacitance. This can be improved
by considering other elements like the non-linearity of the capacitance. This leads to
another set of formulas, which were based on a theoretical procedure that is not exact,
but approximative. This has been shown by the harmonic orthogonality analysis
developed and proposed in this chapter.
Actual devices model for RF applications are much more complex and the simple ONOFF model with linear capacitance is a strong simplification. The actual behavior
involves current and capacitance non-linearities as well as dispersion and thermal
effects. As a result, researchers resort to optimization procedures to tune their designs
and make them optimal. On the other hand, we notice that it is possible to get classE operation using legacy formulas and without blind optimization. To this purpose,
proper device modeling is necessary and this will be the subject of next chapter.
114
Chapter 5
GaAs HEMT device modeling

5.1
Introduction
Device modeling has become an outstanding research area finding its primordial relevance in the RF/microwave circuit design area. The latter has received even more
impulses by the proliferation of many CAD softwares. Unfortunately manufacturers,
most of the time, do not put enough effort to provide a good model for their devices.
Normally these models are not accurate and limited to certain DC/RF conditions.
The modeling task is even more demanding for power amplifier purposes. This requires a model accurate enough for small and large signal conditions. The latter is
the most difficult one to obtain because of the high non-linearity of the device and
the need for expensive and sophisticated equipment for characterization.
There are mainly three approaches to realize a non-linear model for a device [122].
Physics-based modeling is the first one and it is based on device current transport
equations as well as material properties and geometries. This modeling approach is
very complex and normally requires numerical solvers with long computational times.
The second approach is the equivalent circuit modeling, which is based on a lumpedelement representation of the device. Each of these lumped elements corresponds to a
device physics characteristic. The values of these elements are obtained based on DC
and RF measurements. The third approach is the black box modeling, which consists
of a representation of the device based on mathematical transfer functions between
input and output observable variables. This approach unavoidably disconnects from
the physical nature of the device. Many mathematical approaches for the transfer
function have been proposed, with artificial neural networks one of the latest ones
and widely used nowadays.
From the three types of models described above, the equivalent-circuit is the most
115
5.2. Basic concepts: measurements, calibration and deembedding

suitable for amplifier design. Physics-based models are too time-consuming, besides
it can not be easily integrated in conventional microwave CAD tools. Black-box
modeling loses contact with the device physics and does not allow to verify device
intrinsic characteristics, which is very important for the amplifier designer. Due to
all these arguments, an equivalent circuit approach for developing a non-linear model
will be presented in this chapter. Furthermore, this will be applied and illustrated
for a specific bare-die GaAs HEMT device. This developed model will be utilized in
chapter six for the final designs of this thesis.
5.2
Basic concepts: measurements, calibration and

deembedding
The first step in the device modeling process consists of the device measurements.
These measurements can be classified in three types:
- DC measurements, to obtain the device IV characteristics. This can be static DC
measurements where effects such as self-heating effect can be observed, or pulsed-DC
measurements where self-heating and traps effects can be avoided.
- S-parameter measurements, which correspond to the characterization of the device
under small-signal regime. It is considered that the device is excited by a small signal
such that its behavior can be considered linear, i.e., there is no harmonic generation.
- Large-signal measurements, which allows collecting the fundamental plus the harmonic components generated when the device is driven in non-linear regime. This
type of measurements can be realized by last-generation instruments Large Signal
Network Analyzer (LSNA).
In order to realize a complete model, these three types of measurements should be
realized. Nonetheless, due to the high cost of the LSNA, the third measurement is
alternatively accomplished by using a power meter or a spectrum analyzer. Although
this implies collecting only the magnitude value of the harmonics because the latter
two instruments do not measure phase.
S-parameter measurements
In order to perform S-parameter measurements of the device, two concepts or processes are usually involved. These are called calibration and de-embedding. Though
they follow the same purpose, the contexts are different. In order to illustrate both
concepts, a scheme showing a typical setup for S-parameter measurements of a packaged device is shown in Fig 5.1. In this graph three different reference planes are
defined:
116
Figure 5.1: Measurement set-up with measurement (MP), calibration (CP) and deembedding (DP) planes
- MP: measurement plane

- CP: calibration plane
- DP: de-embedding plane
The measurement plane is where the actual travelling waves are sensed or measured by
the instrument. For illustration purposes this is placed at the VNA input terminals,
but actually it is located somewhere inside the instrument.
The calibration plane is where the instrument, with the connecting cables, makes
contact with the device test structure. This calibration plane can be either physically
located at the ends of the VNA cable connectors (connectorized devices) or at the
end of the probe contacts (on-wafer measurements). The latter case is shown in Fig
5.1. Although the definition is obvious, a calibration process involves the correction
of the measurements at the MP such that they are translated to the CP.
The de-embedding plane corresponds to the actual device plane. A de-embedding
process is necessary to translate the measurement values from the CP to the DP. For
the case of a packaged device, the DP coincides with the package terminal, while for
on-wafer measurements DP is located at the intrinsic device.
Normally, calibrations as well as de-embedding processes are comprised of two steps.
The first step is to calculate a matrix or model of all the (parasitics) elements in
between the corresponding planes. The second step is to correct the measurements
with this matrix/model, which results in a translation of the reference planes.
117
Figure 5.2: Calibration and de-embedding techniques
To determine the matrix/model for the corresponding process, standard structures,

which characteristics are precisely known, are required. These standards are placed
in between the reference planes and measured sequentially. These standards can be
reflective loads such as short and open circuits, transmission lines, or 50 loads
(matched load).
The combination of these structures defines a specific calibration or de-embedding
process.
SOLT, this method stands for Short Open Load (50 ) and Thru, which are the
standards used in this case (see Fig. 5.2). These standards are characterized by the
manufacturer and provided as a calibration kit. This comprises information such as
the inductance of the short, the capacitance of the open, the resistance and inductance of the load, and the length and characteristic impedance of the thru. This
calibration is quite well spread in VNA measurements with coaxial connectors or
probes. Though it is a broadband technique, its applicability at frequencies above 20
GHz depends on a good characterization of the standards beforehand. The distance
between probes during calibration is constant, which is an advantage due to the ease
of probe placement.
TRL, stands for the Thru, Reflect and Line standards of this method (see Fig. 5.2).
The thru standard is pictured as a direct connection between the calibration planes.
118
Figure 5.3: First test fixture proposal for packaged SiGe BFP620
The standard thru could be also replaced by another line, turning into a new calibration method called LRL. The line standard is conventionally assumed to be a
90 line at the centre frequency, and its phase difference over the frequency range
should be kept between 20 and 160 [123]. If broader frequency ranges have to be
covered, additional lines should be used. Due to this last fact, its application at
very low frequencies is excluded because of the physical length of the transmission
lines required. Nevertheless this can be overcome by the use of an additional shortopen-load standard set. Unlike with SOLT, the probe distances are not fixed during
calibration. Two remarks are important to mention for the legacy TRL algorithm. It
is not necessary to have a complete characterization of the reflect standard () as this
value can be calculated from the algorithm. The reference impedance is determined
by the characteristic impedance of the lines which may not be 50 , in which case a
renormalization could be required.
Multiline TRL uses multiple, redundant transmission lines besides the reflect load and
thru standard (see Fig. 5.2). This redundancy allows reducing the effects of random
errors caused, for instance, by incorrect contact repeatability. Unlike the conventional TRL, the algorithm calculates the complex frequency-dependent characteristic
impedance of the transmission lines utilized in the calibration, and the reference
impedance can be set to the characteristic impedance of the line, to 50 , or to
any real impedance value. This technique was developed by NIST (National Institute
of Standards and Technology) who provides two software programs [124] containing
the algorithm: MultiCAL (or NISTCal, Windows version) and StatistiCAL. The former can process up to 4 different transmission line measurements besides the thru
and the reflect. The latter can process up to 40 different standards simultaneously,
among which transmission lines, reflects, and loads. It can use different combinations
of standards. An additional feature of the latter software is that it determines the
uncertainties of the calibration process over the frequency.
119
5.3. Test structures

Any of the above-mentioned techniques can be used for calibration or de-embedding
processes. Normally, SOLT and TRL techniques are utilized for VNA calibration
because the manufacturer provides high-quality, adequately characterized standards.
TRL and multiline TRL are normally used for de-embedding as these do not require
precise standards and they usually can be implemented in-house.
5.3
Test structures
Test structures are the interface between the calibration plane of the measurement
equipment and the actual device. They have to be properly structured in order to
avoid unwanted distortion in the measurements, for instance spurious oscillations.
This last effect can be detected when the DC IV characteristics are measured. In the
following, two test structures, utilized during the development of this thesis, will be
described.
5.3.1
Test fixture for packaged SiGe BFP620
This text fixture was designed at the earliest stage of this research. The goal was
to provide a structure for measuring DC and S-parameters of the Infineon BFP620
packaged transistor. DC measurements were for checking the maximum ratings of
the device and S-parameters for extracting the output capacitance as described in
chapter four, section 4.3.
The algorithm chosen for de-embedding the device measurements was multiline TRL,
due to its robustness and flexibility for the standards. Then, in order to reduce
problems of repeatability for the measurements of the different standards, microwave
probes (800 um pitch) were chosen instead of coaxial connectors. The latter are more
vulnerable to uncertainty due to soldering and handling. Nevertheless one problem
arises from this configuration as can be seen in Fig. 5.3. The propagation mode of
the probe is a CPW mode, while the base-emitter or collector-emitter terminals are
set to receive a slot-line mode signal. As a result, the package cannot be connected
to the probe without further ado. In order to interface a CPW mode to a slot-line
mode, a launching structure is proposed which comprises a CPW transmission line,
microstrip transmission line and a transition between both by using via-holes. The
dimensions of the via holes and the transition characteristics were optimized using an
EM structure simulator (HFSS) such that the insertion and return loss were minimum
at the operating frequency of 5.25 GHz.
Once the transition has been optimized for 50 ports and minimum losses, the
question remains how long the CPW and microstrip lines should be. Apparently there
is no restriction since they are 50 lines. According to the technical report [125], these
should be two times the wavelength () corresponding to the operating frequency.
120
Figure 5.4: Test fixture and DC measurements
The reason of using 2 is to have sufficient distance for the attenuation of higher
order modes generated in the transitions CPW/microstrip or connectors, such that
the distortion in the measurements and de-embedding process would be small. The
material used for the test fixture and de-embedding structures were Rogers Corp 3010
with = 10.2 and 650 m thickness. Since 2 is too long (52 mm), we decided to work
with approximately 1 for both the CPW and microstrip transmission lines. When
these transmission lines with such long dimensions are used for DC testing, problems
arise, as reported in Fig. 5.4. The device becomes unstable (prone to oscillation) at
high voltages and low current. A second test fixture proposal with reduced CPW
transmission line length was tested with improved performance, but there are still
some instabilities in the measurements. A third test fixture with reduced CPW and
microstrip transmission line lengths was designed and tested with optimal results for
DC measurements (no spurious oscillation). One of the reasons of the instabilities
of the transistor, under DC testing, could be understood considering the transition
CPW-microstrip as a load different from 50 , which is transformed to another value
at the transistor terminal. This load may drive the transistor into an unstable region
for a specific bias condition, since the S-parameters of the transistor change with the
DC bias point.
In order to perform a proper de-embedding of the device package, correct measurements of the multi-line TRL standards have to be carried out. These standards are
a thru, reflect (open) and two transmission lines of 60 and 90 at 5.25 GHz. An
observation arisen during the measurements of these transmission lines is that certain
measurements do not correlate with each other, as reported in Fig. 5.5a. Three out of
four measurements correlate quite well, but there is one that presents a deep atten121
Figure 5.5: Measurements of 90 calibration standard (a) and modes at the input port (b)
uation at low frequencies. If this uncorrelated measurement is assumed correct, this

could lead to a wrong de-embedding processing since it will generate a de-embedding
matrix intended to compensate this attenuation. After performing additional testing,
it turned out that the origin of the problem was the unintended excitation of the
higher modes (see Fig. 5.5b) when the probes are not correctly positioned. If the
central tip of the probe is not positioned at the center of the CPW central conductor,
then CPW higher order modes are excited causing the lines to present an attenuation
at low frequencies (around 4 GHz).
Once the issues regarding DC and standard measurements have been solved, the next
step is to do S-parameter measurements. This allows extracting the actual transistor
capacitances, which for instance can be used in class-E designs. Nevertheless, new
problems arose when S-parameter measurements were carried out using the shortest
transmission lines version of the test fixture. As reported in Fig. 5.6a), S21 measurements present high attenuation at certain frequency bands and not the classical
smooth response curve over the frequency range. Once again, there is a problem of
higher modes-excitation. In this case, this is because the transition from a CPW mode
to a slotted mode is not correct, since this slotted mode termination inherently generates higher order modes. A solution to overcome this issue was changing the slotted
mode termination to a quasi CPW mode. This implied adding one more ground connection to the input and output of the device. By realizing this, the termination of
122
Figure 5.6: S21 parameter for different test fixtures at the same bias condition
the transmission line will be a quasi-CPW, which is closer to the excitation mode at
the probe tips. As it can be seen, in order to add an effective ground connection, the
ground connection of the output has to be used, otherwise this new ground connection
will be floating. Then, a new version of test fixture based on this idea is presented
with the corresponding output measurements. As it can be seen in Fig. 5.6b), there
are no more major distortions over the whole frequency range. Only, there is a problem with a high attenuation at low frequency. After revising the layout connections,
it turned out that one via hole for ground connection at the input was not properly
metalized, so there was a floating ground, which forced a slotted mode at the input.
Ultimately, based on this idea, a final test fixture was proposed Fig. 5.6c). This omits
via holes and consists of a direct connection between the probe tip and the packaged
device by means of CPW lines. The input and output grounds are tied together to
avoid slotted mode spurious. This solution turned out to be the best as well as the
simplest one. Furthermore, the de-embedding process could be reduced to de-embed
only two CPW transmission lines.
5.3.2
Test fixture for bare-die GaAs FPD750
The development of the test fixture for the GaAs FPD750 transistor was somehow
more straightforward than in the case of the packaged device. The experiments and
results obtained for the BFP620 test fixture helped as knowledge base for this case.
The device to be tested is a Filtronic bare-die GaAs HEMT. This device has to be
wire bonded to the test fixture. Due to the same reasons as for the BFP620 device,
123
Figure 5.7: FPD750 bare die and test fixture
Figure 5.8: Measurements of the FPD750 transistor in the test fixture (Fig. 5.8): DC IV
characteristics (a) and S21 parameter for VDS = 5 V and VGS = -0.6 V (b)
microwave probes of 800 um pitch were used in this case. In order to avoid unnecessary
transitions, CPW was used without further ado. As a result, a simple test fixture was
proposed, which is shown in Fig 5.7.
For this fixture, an Aluminum oxide (Al2 O3 ) ceramic substrate was used. It exhibits a
dielectric constant r of 9.8 and loss tangent of 0.0001. The thickness of the substrate
is 600 m. The grounds of the input and output CPW transmission lines are joined
together beneath the device. This ground also serves to conduct the device heat to the
wide fin areas (CPW grounds). The CPW transmission lines were tailored for 50 and
their lengths were set to 2.5 at 1 GHz. Besides the CPW transmission lines, there is
no additional variable to be tailored, because the bonding wire lengths are limited by
the device and CPW transmission line dimensions. Nevertheless, a tolerance of about
20% should be considered since the exact placement position depends on the technical
skills of the operator. First DC and S-parameter testing of the test fixture with the
device do not show major distortions or spurious oscillations (see Fig. 5.8), so these
124
5.4. Small signal modeling

results were used without modification for the characterization of the device. The
small resonance observed in the S21-parameter would correspond to a self-resonance
of the board (Eigen mode). As this resonance is at high frequency and out of the
model scope, it will not affect or distort the modeling procedure.
5.4
Small signal modeling
Once the test fixture has been verified to work properly, the characterization of the
bare-die GaAs FPD750 can start. For this purpose, initial description can be accomplished by extracting the intrinsic characteristics of the device under small signal
regime. Therefore S-parameters of the device should be obtained. Nevertheless this is
not straightforward since the intrinsic device is embedded in the test fixture. This can
be characterized by an extrinsic network that includes the effect of the CPW transmission lines, bonding wires and parasitic capacitances. All these elements should
be subtracted from the measurements. Conventional de-embedding procedures such
as SOLT, TRL and Multi TRL are not possible in this case, since this will require
counting on de-embedding standards (open, short, lines) processed in a GaAs material with similar characteristics as the Filtronic device. As a result, two alternatives
approaches were applied [126]:
Modeling of the test fixture by an equivalent circuit and de-embedding of each
of the circuit elements. This implies constructing a model in terms of lumped
components and transmission lines, based on the physical characteristics of the
elements.
Modeling of the test fixture by a four-port network and the corresponding deembedding of this network.
Both approaches have been studied and developed in this research. These will be
presented next.
5.4.1
Equivalent circuit of extrinsic network
An identification of the parasitic elements is necessary to establish a topology for the

extrinsic network. The topology defined for this test fixture is reported in Fig. 5.9
along with the physical elements they represent.
The following elements can be identified:
CPW_g and CPW_d correspond to the CPW transmission lines at ports 1 and 2
respectively.
125
Figure 5.9: Equivalent circuit of FPD750 test fixture
Lgp, Ldp and Lsp correspond to the parasitic inductances of the bonding wires.
These include the transistor metallization as well. Additonally, these inductances can
be modeled using transmission lines, which gives better fitting with measurements.
Cpg and Cpd correspond to the parasitic capacitances between the transistor contact
pad (gate and drain) and the metallization underneath the bare die.
Cpgs, Cpgd and Cpds correspond to the parasitic intrafinger capacitance as well as
the capacitance between pads (gate, source and drain).
Ultimately, the short CPW lines and bonding wires have also associated parasitic
resistances. Nevertheless these are negligible in comparison with the access or contact
resistances. These resistances are not indicated in the test fixture (Fig. 5.9) because
they are physically inside the bare-die transistor. These resistances Rgp, Rdp and
Rsp are dependent on the technology and processing (Ohmic or Schottky resistance).
For clarification and completeness they are shown in Fig. 5.10 with the final extrinsic
network.
Different topologies with larger numbers of elements could be used as well. Though
this would lead to higher precision, the determination of the element values would be
more cumbersome. On the other hand, the reported topology showed to be sufficient
for the intended frequency range (up to 10 GHz) of the model. This will be presented
126
Figure 5.10: Complete equivalent circuit including contact resistances for the FPD750
mounted on the test fixture of Fig. 5.8
later on.
In the following, procedures to estimate the values of the extrinsic network parasitics
will be developed. These values serve as a starting value for the optimization of the
complete network to improve the fitting with measurements under small signal regime.
For the CPW transmission lines, the electrical length can be determined using for
instance the LineCalc ADS tool, by using the physical dimensions and the substrate
characteristics already described in subsection 5.3.2. Then, a value of 2.5 at 1 GHz
is determined. The characteristic impedance is 50 .
Bonding wires can be modeled as pure inductances or transmission lines. For a wire
inductance, the rule of thumb of 1 nH/mm1 can be used to determine its value, once
the physical length is estimated. The average length of the bonding wires is 500 m,
then the estimated inductance values would be 0.5 nH for the drain and gate bonding
wires and 0.25 nH for the source bonding wire. However, these values are too rough
and not accurate enough for the de-embedding process. Better approximation can be
obtained if they are modeled as transmission lines. They can be considered as lines
suspended in air and in parallel to a ground plane. The distributed capacitance and
inductance can be calculated as indicated in Fig. 5.11, considering a wire diameter (d)
of 30 m and a heigth (h) above the ground of 75 m (die thickness). Subsequently,
the characteristic impedance and electrical length can be determined by the following
expressions:
r
Z=
p
Ld Cd
Ld
Cd
(5.1)
= lbw
(5.2)
where Z is the characteristic impedance, is the phase constant, is the electrical

1 As a matter of fact, this value can be estimated based on the self inductance value of a wire or
by using 3D EM simulations as the one realized in [127] using FDTD technique.
127
Figure 5.11: Bonding wire interpreted as a transmission line
length and lbw is the physical length of the bonding wire. A characteristic impedance
of 145 and a length of 0.77 at 1 GHz is determined for the bonding wires at gate
and drain. Since the bonding wire at the source terminal is much shorter, it can be
kept as a pure inductance. Moreover this simplifies the de-embedding calculation. Its
value can be calculated based on the distributed inductance of the transmission line
model instead of the rule of thumb. Given a calculated distributed inductance of 0.46
nH/mm, then its value would be about 0.115 nH.
All these bonding wire values can be further tuned considering cold-FET conditions
[128], as described next in the calculation of the parasitic resistances.
Parasitic Resistances
Parasitic resistances can be determined based on the classical procedures found in
[128], which are widely known as the cold-FET method. For this particular case the
device is driven in saturation with VDS = 0V and VGS = 0.8V . The intrinsic model to
be considered under this condition is reported in Fig. 5.12. Unlike what is established
in [128], the gate capacitance Cgate is not neglected and is included in the model as
suggested in [129][130] for the weak forward conduction (Cgate plus Rgate). Besides
the extraction of the resistance values, this cold-FET condition can be used to verify
and correct the values of the bonding wires modeled either as transmission lines (Lgp,
Ldp) or as pure inductance (Lsp). The following expressions can be established in
terms of Z -parameters:
Z11 Z12 = Rgp +
Rgate
+ jLgp
1 + jCgate Rgate
(5.3)
Z12 = Rch1 + Rsp + jLsp
(5.4)
Z22 Z12 = Rch2 + Rdp + jLdp
(5.5)
As can be deduced from equations (5.4) and (5.5) inductances Lsp and Ldp can be
solved without further ado. This is what is known as a well-conditioned problem.
128
Figure 5.12: Equivalent circuit (a) and extracted inductance (b) and resistance (c) values of
FPD750 under weak forward cold-FET condition
As a first approach, the inductance Lgp can be assumed equal to Ldp taking into
account the geometry of the problem. As a matter of fact, initial characterization
of these inductances was already performed as transmission lines (Lgp, Ldp) and an
inductance itself (Lsp). A de-embedding of the CPW transmission lines and inductances Lgp and Ldp (as transmission lines) are performed before the application of
the equations (5.3), (5.4) and (5.5). As a result, if the bonding wires Lgp and Ldp
are well modeled, the inductance values should be zero when these formulas are applied, otherwise the characteristic of the transmission lines should be modified till zero
values are obtained. This is possible for Ldp, but not for Lgp due to the influence
of Cgate. However, this is not so relevant because the characteristic of the bonding
wires Ldp and Lgp can be considered similar. The inductance Lsp can be extracted
straightforwardly and its value (0.085 nH) is close to the estimated value indicated
before (0.115 nH). The corrected values for the transmission lines and bonding wires
are reported in Table 5.1.
Unlike the inductances case, the resistances can not be solved in a direct way as it is
an ill-conditioned problem. There are six unknowns for a set of three equations. Then
some assumptions or alternative approaches should be taken. The channel resistances
corresponding to the junction gate-source (Rch1) and gate-drain (Rch2) could be
considered similar and therefore both are taken as half of the total channel resistance
[128, 130]. A rough estimate of Rsp, Rdp, and Rgp can be obtained using another cold129
Figure 5.13: Cold-FET condition for VGS = 0 V and VDS = 0 V
FET condition in which the effect of the channel resistance and forward conduction
impedance are removed. For instance, a cold-FET condition corresponding to the bias
VDS = 0 V and VGS = 0 V (open channel condition) can be used to determine Rgp.
The equivalent circuit is reported in Fig. 5.13 [129]. It can be inferred that by taking
the real part of the factor Z11 Z12 of this network, an initial value of Rgp can be
obtained. On the other hand, Rsp and Rdp can be considered approximately equal as
a first approach, given that the geometry of the physical contacts is approximately the
same. This can be also verified by observing Fig. 5.12. The values of Rsp+Rch1 ( Rch
2 )
Rch
and Rdp+Rch2 ( 2 ) coincide up to about 3 GHz. Finally, to determine separate
values for either Rsp or Rdp, a cold-FET condition with VDS = 0 V and VGS =
-1.4 V is used. The equivalent circuit for this condition can be observed in Fig. 5.14.
Based on this, it can be deduced that the real part of the Z -parameters could be
used for extracting a first value of the resistances Rsp or Rdp. It is important to
remark that this value is not accurate as this value changes with VGS lower than
pinch-off. However, the chosen bias point gives a coherent value that is constant over
the frequency range. Finally, the flyback method [131, 132] is a more accurate method
to determine the value of the resistances Rsp and Rdp. The complete set of values of
these parasitic extrinsic resistors is reported in Table 5.1.
Parasitic Capacitances
In order to determine proper values for the extrinsic capacitances, the devices have to
be driven again in cold-FET conditions, i.e., VDS = 0 V and VGS equal or lower than
the pinch-off voltage. Under this condition, the intrinsic device can be represented
by its depletion capacitances Cgs and Cgd plus an additional capacitance Cds. These
elements form a delta network as shown in Fig. 5.14. The imaginary parts of the Y parameters were used for the determination of these capacitances. At low frequencies
the following relationships can be established:
Im(Y11 Y12 ) = (Cpg + Cpgs + Cgs)
130
(5.6)

Table 5.1: Extrinsic network elements values extracted for the FPD750 transistor
Characteristic
CPW characteristic impedance at gate ()
CPW characteristic impedance at drain ()
CPW phase delay at gate (degrees)
CPW phase delay at drain (degrees)
bonding wire characteristic impedance at gate ()
bonding wire characteristic impedance at drain ()
bonding wire phase delay at gate (degrees)
bonding wire phase delay at drain (degrees)
pad-ground parasitic capacitance at gate (fF)
pad-ground parasitic capacitance at drain (fF)
bonding wire inductance at source (nH)
interdigital capacitance gate-source (fF)
interdigital capacitance gate-drain (fF)
interdigital capacitance drain-source (fF)
contact resistance at gate ()
contact resistance at drain ()
contact resistance at source ()
Symbol
Zog
Zod
Eg
Ed
Zobg
Zobd
Ebg
Ebd
Cpg
Cpd
Lsp
Cpgs
Cpgd
Cpds
Rgp
Rdp
Rsp
Value
52
52
2.55
2.55
155
155
0.9
0.8
32
32
0.085
64
44
60
0.27
0.6
0.6
Im(Y12 ) = (Cpgd + Cgd)
(5.7)
Im(Y22 Y12 ) = (Cpd + Cpds + Cds)
(5.8)
However, these equations are not enough in number to obtain all the capacitance
values. There are eight unknowns for only three equations. Furthermore, it is not
possible to separate the values of the parallel capacitances Cpg, Cpgs and Cgs. Therefore, additional concepts or approaches have to be used in order to sort out these
non-trivial conditions. In particular, the capacitances Cpg and Cpd could be characterized by using the parallel plate capacitance concept. As the bare-die pads area (A),
the thickness (t) and electrical permittivity (r ) are known, the following equation
can be applied to determine the capacitance value
C = o r
A
t
(5.9)
where o is the permittivity in vacuum.

Nevertheless this formula has to be corrected due to the presence of fringing fields,
which increase the apparent width of the capacitor plates by an amount proportional
to the thickness of the dielectric [70], in this case a GaAs substrate. The final values
131
Figure 5.14: Equivalent circuit (a) and extracted capacitances (b) (c) for the FPD750 under
cold FET conditions for voltages VGS lower than pinch-off voltage
obtained for Cpg and Cpd are reported in Table 5.1. Although the determination of
Cpg relaxes the number of unknowns in equation (5.6), the capacitances Cpgs and
Cgs still can not be solved separately, as well as Cpgd and Cgd in equation (5.8). In
order to separate these variables, other tests have to be performed [129]. If the gatesource voltage is decreased, the corresponding depletion capacitance Cgs will decrease
as well. Then in the limit when VGS=-, Cgs becomes equal to zero. As a result,
the only remaining capacitance will be Cpgs. In practice, a plot of the extracted
capacitance Cpgs-Cgs versus VGS is extrapolated for VGS=-. As a matter of fact,
curve fitting procedures are performed in order to find this extrapolated value. Another important factor to take into account when this fitting is performed is that Cgs
is equal to Cgd for these cold-FET conditions. The graph reported in Fig. 5.14 shows
this characteristic for Cpgs-Cgs and Cpgd-Cgd. On the other hand, the separation
of Cpds and Cds is more difficult since this does not follow this characteristic, but
it remains approximately constant. Then this value can be assumed a constant and
unique parasitic value. The values for all these extrinsic capacitances are reported in
Table 5.1.
132
Figure 5.15: Device and test fixture with four-port network definition, local ground is associated to ports three and four (a). Conventional four-port definition of extrinsic parasitic,
common ground is used for all the ports (b).
5.4.2
Four-port representation of extrinsic network
Another strategy to do the characterization of the test fixture is by utilizing a four-port

network definition [133, 134]. In this case, most of the extrinsic parasitics, studied in
the previous subsections, are embedded in a black-box four-port network or matrix.
The positions of the ports in the test fixture are indicated in Fig. 5.15. Port 1 and 2
correspond to the measurement planes and port 3 and 4 to the intrinsic device plane.
In this case, the intrinsic device plane can not go deeper and surpass the contact
resistances, and therefore these resistances have to be de-embedded later. In previous
research works, [133, 134], applied to on-wafer devices, the four-port network matrix
has been successfully determined by using a 3D EM simulator or a set of standard
structures. Nevertheless, the determination of the four-port matrix based on 3D
EM simulation fails when it is applied to large structures such as the present test
fixture. This is mainly due to two factors: the effect of the local ground plane, i.e.,
[135] the ground of port 1 and 2 is different from the ground of port 3 and 4, while
the general definition of a four-port network considers only one common ground (see
Fig. 5.15b). The second factor is the accuracy of the 3D EM simulator. The effect of
the local ground can be overcome by using a 5-port network characterization [136],
where the local ground becomes a fifth port. However, this approach is not feasible
or applicable with a 3D EM characterization. Furthermore EM calibration and deembedding techniques such as double-delay or short-open-calibration (SOC) [135, 137]
do not provide good results in this case, due to the complexity of the test fixture.
An alternative four-port characterization of the text fixture that corrects the effect
of the local ground, without the recourse to a five-port characterization nor a EM
calibration/de-embedding technique, has been developed in this research[138, 139]
and will be described next.
133

Four-port network characterization with local-ground effect correction
As was already described, the four-port network matrix can be determined by using
a 3D EM simulator such as HFSS. However the internal ports, used for this 3D EM
analysis, have their own local ground, which is not a common ground. Then this
four-port network matrix solution has to be corrected in order to transform it into
one that has a common ground.
Using the definition of variables indicated in [133], the network can be represented by
its Y -matrix, with a common ground reference (see Fig. 5.15b)

I1
Y11
I2 Y21

I3 = Y32
I4
Y41
Y12
Y22
Y32
Y42

Y14
V1
V2
Y24
Y34 V3
Y44
V4
Y13
Y23
Y33
Y43
(5.10)
By defining vectors Ve and Ie as the extrinsic vectors and Vi and Ii as the intrinsic
ones
Ie
Ii
I1
I2
I3
I4

and
Ve
Vi
V1
V2
V3
V4
equation (5.10) can be rewritten as
Ie
Ii
Y11 Y12 |
Y21 Y22 |

Y32 Y32 |
Y41 Y42 |

Ie
Ii

=
Yee
Yie
Y13
Y23
Y33
Y43
Yei
Yii
Y14
Y24
Y34
Y44

Ve
Vi

Ve
Vi
(5.11)
(5.12)
where Yee , Yei , Yie and Yii are four 2x2 matrices.
Noting that Ie = YEXT .Ve and Ii = YIN T .Vi , where YEXT and YIN T are the
extrinsic and intrinsic devices Y -parameters respectively, the following relationships
can be established from equation (5.12)
Y EXT Ve = Yee Ve + Yei Vi
Y IN T Vi = Yie Ve + Yii Vi
134

(5.13)
Figure 5.16: Intrinsic device models used to obtain Y IN T data at two cold-FET bias conditions: pinch-off bias condition (a) and forward conduction condition (b)
Solving the simple set of equations (5.13) for Y EXT provides

Y EXT = Yee Yei (Y IN T + Yii )1 Yie
(5.14)
As a matter of fact, Y EXT coincides with the device measurements (including test
fixture) at the calibration plane and Y IN T with the intrinsic device Y -parameters.
Then, the idea of the developed four-port technique [138, 139] is to have input data
for Y EXT and Y IN T for different bias conditions in order to solve for Yij (Yee , Yei ,
Yie and Yii ), which are the Y -parameters of the four-port parasitic model. An initial
solution for the four-port network has already been obtained from a 3D EM simulator.
However, this needs to be corrected in order to eliminate the local-ground effect.
Y EXT input data are collected by doing S-parameter measurements at port 1 and
2, which are the only physically accessible ports. Y IN T input data can be obtained
by driving the device in bias conditions where its behavior can be easily defined and
modeled, and these correspond to the cold-FET bias conditions (VDS = 0).
On the other hand, in order to solve for the 16 unknown variables of the four-port
network Yij (Y11 , Y12 , Y13 .. Y44 ), 16 equations are needed or four different conditions
for Y EXT and Y IN T have to be known. Each condition provides four equations.
These four conditions can be reduced to two conditions or eight equations, taking
into account the following observations:
The four-port network corresponds to a passive network, implying that the
matrix should be reciprocal, i.e., Yij = Yji .
Since the losses are minimal, the phase of the Y -parameters should be very
close to 90.
Due to the physical layout, a symmetry approach can be considered for Y11 and
Y22 (Y11 = Y22 ), which is not true for Y33 and Y44 . The same argument holds
for Y23 and Y14 (Y23 = Y14 ).
135
Figure 5.17: Flow diagram of the algorithm used to correct the Y -parameters of the four-port
de-embedding circuit (at a single frequency)
Therefore, only two conditions are needed to solve the problem. The two conditions
used in this technique are two cold-FET conditions: cut-off and forward conduction
condition. These two conditions are chosen because the intrinsic parameter (Y IN T )
values determination and the Y EXT measurements can be realized straightforwardly.
The intrinsic device models used for obtaining Y IN T input data at these bias conditions are indicated in Fig. 5.16 (see also Fig. (5.12) and (5.14)) . These models are
extracted at low frequencies where the influence of the devices inductive parasitics
can be neglected.
For these two cold-FET conditions, two matrix equations can be established from
(5.14)
EXT
IN T
1
Ypinchof
Yie
f = Yee Yei (Ypinchof f + Yii )
(5.15)
IN T
1
YfEXT
Yie
orward = Yee Yei (Yf orward + Yii )
(5.16)
This set of equations cannot be solved straightforwardly due to the matrix inversion
operation that includes one set of variables. Therefore, this has to be solved by
136

numerical methods. The two equations (5.15) and (5.16) plus the considerations
indicated above are used to solve the Y-parameters by using a differential evolution
optimization process [140] and by taking as initial values the ones given by the EM
simulator. In order to explain the process followed to solve this problem, a flow
diagram of the algorithm as implemented in Matlab, is shown in Fig. 5.17.
The algorithm starts by initializing the values of the variables Yij (Y11 , Y12 , Y13 ..Y44 )
with the values given by the 3D EM simulator. At the same time, the values for
IN T
IN T
Ypinchof
f and Yf orward are obtained from the simulation performed with the model
EXT
indicated in Fig. 5.16. Then, all these values are combined to calculate Ypinchof
f
and YfEXT
orward using equations (5.15) and (5.16). If the latter values coincide with
the values obtained from measurements then the algorithm exits. Actually, what
is calculated is the difference between the theoretical values and the measured ones
using the following formula
error =

2 X
2
X
YDU T labmeas(i, j) YDU T extrinsic(i, j)

YDU T labmeas(i, j)
(5.17)
j=1 i=1
where YDU T labmeas corresponds to the measured Y -parameters and YDU T extrinsic
corresponds to the calculated Y -parameter based on the four-port network. Both
YDU T labmeas and YDU T extrinsic are set at calibration plane.
This error is calculated for each bias condition. Then YDU T extrinsic of equation
EXT
EXT
(5.17) can be either Ypinchof
f or Yf orward . The sum of the errors for both bias
conditions is the total error, which should be minimized. If this total error is greater
than a threshold value, then the assumed solution is not valid and a new set of values
for Yij is calculated based on the differential evolution (DE) optimization algorithm.
With the latter operation, the algorithm returns to the beginning of the program,
establishing in that way an iterative loop that will end when the error is lower than or
equal to the threshold value. This algorithm is repeated for all the analysis frequencies.
To illustrate the validity of the method, measurement data of the device mounted on
the test fixture are collected at different bias conditions. Additionally, a 3D EM model
of the structure is realized, as according to Fig. 5.15a. Simulations performed on this
3D EM model provide a set of four-port Y -parameters that defines the extrinsic model
of the test fixture [134]. Simple models of the intrinsic device are extracted at the
two cold-FET conditions as explained above. Y -parameters of these models can be
obtained straightforwardly and by applying (5.14), the corresponding extrinsic Y parameters can be obtained and compared with the measurements. This is shown in
Fig. (5.18)a and (5.19)a. As it can be seen, the extrinsic S-parameters based on the 3D
EM four-port extrinsic model start to diverge from measurements at high frequencies
(around 6 GHz) and this difference increases with frequency. As it was mentioned
above this is due to the local ground effect. The described technique corrects this
problem. By realizing the algorithm described above, a new set of four-port Y parameters that models the extrinsic parasitics, is obtained. The calculated extrinsic
137
Figure 5.18: S-parameters with 3D EM 4-port values (a) and with the proposed technique
(b) at cold-FET forward condition.
Figure 5.19: S-parameters with 3D EM 4-port values (a) and with the proposed technique
(b) at cold-FET pinch-off condition.
138
Figure 5.20: Test fixture equivalent circuit and de-embedding planes
Y -parameters, and corresponding S-parameters, are compared with the measurements

in Fig. 5.18b and 5.19b. It can be observed that the agreement with the measurements
is remarkably better in the second case and this up to 20 GHz.
5.4.3
De-embedding and extraction of device intrinsic parameters
In order to construct the small-signal and subsequently large-signal model of the

bare-die FPD750 device, the intrinsic parameters have to be extracted under different
bias conditions. S-parameter measurements are performed on the test fixture for this
purpose. The bias points are chosen in order to cover the saturation, cut-off and linear
regions. As the model is intended for power amplifiers, S-parameter measurements
under forward-conduction bias are collected as well. The final set of bias points was
the following:
VGS from -1.4 V to 0.8 V with 0.1 V steps and VDS from 0 V to 2 V with 0.2 V
steps.
VGS from -1.4 V to 0 V with 0.1 V steps and VDS from 2 V to 6 V with 0.5 V
steps.
The S-parameters collected at these bias points have to be de-embedded in order to
translate them to the intrinsic device plane. This de-embedding process can be realized in two ways, depending on how the extrinsic network (test fixture plus additional
139

parasitics) is modeled. If the extrinsic network is modeled as an equivalent circuit
such as the one already described in sub-section (5.4.1) and reported in Fig. 5.20 for
further explanation, then the sequence of de-embedding is as follows:
1. For moving from calibration plane 1 to plane 2, first a transformation of measured S-parameters into ABCD-parameters (ABCD1 ) is performed. Then the
following operation to de-embed the CPW transmission lines is done:
ABCD2 = ABCDg1 ABCD1 ABCDd1
where

cos(Eg)
j Zog sin(Eg)
j
cos(Eg)
Zog sin(Eg)
cos(Ed)
j Zod sin(Ed)
j
sin(Ed)
cos(Ed)
Zod
ABCDg =
ABCDd =
2. From plane 2 to plane 3, the following operation to de-embed the bonding wires
at gate and drain is performed
1
1
ABCD3 = ABCDbg
ABCD1 ABCDbd
where

ABCDbg =

ABCDbd =
cos(Ebg)
j Zobg sin(Ebg)
sin(Ebg)
cos(Ebg)
cos(Ebd)
j Zobd sin(Ebd)
j
sin(Ebd)
cos(Ebd)
Zobd
j
Zobg
3. From plane 3 to plane 4, first a transformation of ABCD-parameters (ABCD3 )

to Y -parameters (Y3 ) is done followed by an operation to de-embed capacitances
Cpg and Cpd

Cpg
0
Y4 = Y3 j
0
Cpd
4. From plane 4 to plane 5, first a transformation of Y -parameters (Y4 ) into Z parameters (Z4 ) is done, then the following operation is performed to de-embed
the source inductance

Lsp Lsp
Z5 = Z4 j
Lsp Lsp
5. From plane 5 to plane 6, first Z -parameters (Z5 ) are transformed to Y -parameters
(Y5 ), then the operation to de-embed capacitances Cpgs, Cpgd and Cpds is performed

Cpgs + Cpgd
Cpgd
Y6 = Y5 j
Cpgd
Cpds + Cpgd
140
Figure 5.21: Basic small-signal equivalent circuit (a) and extended circuit including forward
conduction resistances (b)
6. From plane 6 to plane 7, first Y -parameters (Y6 ) are converted to Z -parameters

(Z6 ), then resistances Rgp, Rdp and Rsp are de-embedded

Rgp + Rsp
Rsp
Z7 = Z6
Rsp
Rdp + Rsp
This last set of Z -parameters (Z7 ) can be transformed into S-parameters (S7 ) again,
which would become the intrinsic device S-parameters.
This de-embedding procedure can be realized using the four-port network approach
as well. In this case, steps 1 to 5 are replaced by the following single operation (based
on equations (5.13))
Y6 = Yie (Y1 Yee )1 Yei Yii
where Yie , Yee , Yei and Yii are the 2x2 matrices of the four-port network, as defined
above (see equations (5.11) and (5.12)).
Then, in order to complete the de-embedding process using the four-port network,
step 6 of the equivalent-circuit procedure has to be applied as well.
Once the intrinsic device S-parameters are obtained, the elements of the small signal
model indicated in Fig. 5.21a can be determined. For this purpose, closed-form relationships already exist to determine each of these elements based on Y -parameters.
These equations can be found in [141] and it is not necessary to rewrite them since
more complete relationships will be described next. The typical small-signal model reported in Fig. 5.21a is valid only for negative VGS , which is an insufficient description
for a device aimed to operate under very large signal conditions (power amplifier). As
a result, the characterization and modeling of the device for positive VGS is required
as well. A small-signal model covering negative and positive VGS bias conditions is
141

reported in Fig. 5.21b. The major difference with the one reported in Fig. 5.21a is
the addition of two resistances which account for the weak/mild/strong conduction of
the gate junctions (gate-source and gate-drain) when a positive VGS is applied. The
determination of these resistances is not straightforward and it is better to obtain
them from S-parameters at low frequencies (for instance 50 MHz), instead of from
DC measurements. Closed relationships to determine these resistances along with the
typical intrinsic elements can be found in [142] and are reported here for completeness
Cgd
gf d = Re(Y12 )
(5.18)
gf s = Re(Y11 ) gf d
(5.19)
Im(Y12 )
=
Rgd =
Cgs
Im(Y11 ) + Im(Y12 )
=
Ri =
gm =
r
1
arcsin

1+
Re(Y12 ) + gf d
Im(Y12 )
2 !
(5.20)
Re(Y12 ) + gf d
Cgd Im(Y12 )
(5.21)
1+
(Re(Y11 ) + Re(Y12 ) gf s )
(Im(Y11 ) + Im(Y12 ))
!
(5.22)
Re(Y11 ) + Re(Y12 ) gf s
Cgs (Im(Y11 ) + Im(Y12 ))
2
(Re(Y21 ) Re(Y12 )) + (Im(Y21 ) Im(Y12 ))
(5.23)
D1
Im(Y12 ) Im(Y21 ) Cgs Ri (Re(Y21 ) Re(Y12 ))

gm
(5.24)

(5.25)
Im(Y22 ) + Im(Y12 )
(5.26)
gds = Re(Y22 ) + Re(Y12 )
(5.27)
D1 = 1 + 2 Cgs2 Ri2
(5.28)
Cds =
where
142
Figure 5.22: Extracted device intrinsic values for Cgs, Cgd and gm versus frequency and
bias voltages VGS and VDS
Finally, the extracted intrinsic parameters Cgs, Cgd and gm of the small-signal model
are shown in Fig. 5.22. These parameters are constant over frequency up to 12 GHz.
Above this frequency, board resonances take place and distort their behavior. Using
four-port techniques, the influence of these board resonances can be reduced [138] and
make the extracted values constant over almost the whole frequency range (20 GHz).
At the end, this is not critical since only one value, taken at one specific frequency or
averaged over a frequency range, is necessary. The variation of these intrinsic values
with the bias voltages VGS and VDS is more relevant for the non-linear modeling and
this is also reported in Fig. 5.22.
143
5.5. Large-signal modeling using empirical Angelov FET model
5.5
Large-signal modeling using empirical Angelov

FET model
There are several approaches to realize a large-signal FET model. These approaches
have evolved over time, starting from Curtices model, passing by Materka, Triquint
[122], and reaching the most complete approach developed by EESOF [143]. The Angelov or Chalmers FET model [104, 105, 144] could be placed in the upper half/quarter
of this evolution of FET models. This model is a quite stable and robust large signal
model when it is used with harmonic balance simulators. It presents a high rate of
convergence due to the derivatives continuity of the mathematical expressions used
to define the non-linear currents and capacitances. The extraction of the non-linear
parameters can be realized in a methodical way as will be described in the next
subsections. Thermal and dispersion effects are considered in the Angelov model as
correction factors of the corresponding current and capacitance parameters. This
gives more precision and flexibility when the model is tuned. This modeling approach
is called empirical since the utilized mathematical expressions do not follow a physics
principle or derivation. On the contrary they are chosen in a descriptive way, i.e., they
are aimed at describing device phenomena, and at the same time being compatible
with current processing and simulation tools.
The small-signal model, shown in Fig. 5.21b, can be used as a reference to build the
basic configuration of the large-signal model. The first step is to identify the main
elements that change their behavior with the voltages applied to the device. The
forward-conduction resistances Rf s and Rf d depend on the bias voltages, and this
dependency can be modeled properly by two diodes (see Fig. 5.23), which somehow
corresponds with the physical characteristic of the device gate. The drain current
depends on the transconductance gm and VGS . As gm moreover varies with VGS and
VDS (see Fig. 5.22), the drain current has to be modeled with a non-linear dependency on VGS and VDS (see Fig. 5.23). As can be observed from Fig. 5.22 as well,
capacitances Cgs and Cgd are also dependent on the voltages VGS and VGD , and
therefore they have to be modeled as such (see Fig. 5.23).
The mathematical equations that represent the non-linear behavior of these elements
are what makes a specific model unique and different from others. These mathematical
expressions for the non-linear drain current and capacitances of the Angelov model
will be presented next together with simple procedures to obtain initial parameter
values.
5.5.1
Angelovs drain current expression
The drain current model is centered and optimized for the saturation region (VDS >
Vknee ) and specifically at VGS equal to the value at which the peak transconductance
is obtained.
144
Figure 5.23: Basic configuration of a large-signal model
The current expression for Angelovs model [104] is based on tanh-functions and its
dependence on VGS and VDS is given in separate expressions, as is indicated next:
IDS = Ipk0 (1 + tanh (P1m (VGS Vpk0 ))) tanh (VDS ) (1 + VDS )
(5.29)
where the parameters related to the VGS variable are defined as follows: Vpk0 is the
gate voltage for which the maximum transconductance is obtained. Ipk0 is the drain
current corresponding to the maximum transconductance bias condition. P1m is the
coefficient equal to the ratio of the maximum transconductance gm over Ipk0 .
The second set of parameters related to the VDS variable will be defined in another
paragraph to make it clearer.
In order to extract the values of the first set of parameters defined above, the following
graphs are necessary
DC IV characteristics obtained by conventional measurements or by using pulsed
DC instrumentation.
Transconductance gm .
Then the procedure to extract these values is simple and is indicated in Fig. 5.24a.
First, on the gm chart, the maximum transconductance value is read along with the
corresponding bias condition (Vds and VGS = Vpk0 ). Then in the IDS versus VGS
145
Figure 5.24: Angelov drain current with parameter definitions: VGS dependence (a), VDS
dependence (b)
chart, the drain current is read for the bias condition of maximum gm . This value is
Ipk0 . Finally, the division of maximum gm by Ipk0 gives the P1m parameter.
Additionally from the gm chart, the gate voltage corresponding to the minimum gm
can be obtained. The difference between Vpk0 and the latter voltage becomes the
parameter 4Vpks which is a complementary parameter in the extended Angelov model
[144]. Likewise, the factor P1m (VGS Vpk0 ) in equation (5.29) can be generalized
to control the second and third harmonic components of the current, (and therefore
power harmonics) in the following way:
P = P1m (VGS Vpk0 ) + P2 (VGS Vpk0 )2 + P3 (VGS Vpk0 )3
(5.30)
This coefficient P would replace the expression P1m (VGS Vpk0 ) in equation (5.29).
HEMT devices show typical values between 1 and 3 for P1m [143], P2 and P3 can be
tuned iteratively based on the shape of gm and/or the power measurements of the
harmonics.
The second set of current parameters depending on VDS (equation (5.29)) can be
defined and determined as follows: is the coefficient that controls the slope of IDS
for small VDS (see Fig. 5.24b), VDS < Vknee . Actually this slope is also influenced
by the device intrinsic resistance and additional resistance due to DC cables during
measurements. Therefore it is important to measure and de-embed these external
cables DC resistances in order to properly estimate the value. Furthermore, for
146
Figure 5.25: DC measurements and modeling results for VGS from -1.4 V to 0.8 V and VDS
from 0 V to 2 V (a), and VGS from -1.4 V to 0 V and VDS from 2 V to 6 V (b)
tuning improvement, this factor is also dependent on two coefficients r and s

[144]:
= r + s (1 + tanh(P ))
(5.31)
Then by changing these two values r and s , the drain current at small VDS is
adjusted till it matches the measurements. P has been defined in equation (5.30).
An initial value between 1 and 3 can be assumed for s [143].
is the coefficient that controls the slope of IDS for large VDS (see Fig. 5.24b) i.e.,
VDS > Vknee . However this parameter is difficult to extract since the devices selfheating changes the slope of IDS for large VDS . To sort out this issue, pulsed DC
measurements are required. Nevertheless the instrumentation for this testing is not
normally available. Then an alternative solution is to use the slope data for small
current IDS , which is less influenced by device self-heating.
The procedures, just described, allow to obtain initial values of the current model.
Parameters that do not fit measurements at first can be improved by tuning of these
values manually or by optimization routines. After performing several iterations, a
simulation response as the one reported in Fig. 5.25 can be obtained. As can be
observed, the fitting is quite well at low VGS . However, it starts to deviate as VGS
increases, and it is even more visible at high VDS . This disagreement region correlates
with the self heating of the device. This can be corrected by tuning thermal coefficients
manually. Nevertheless, this can not be done at this stage because thermal coefficients
influence intrinsic capacitances as well. So we will come back to this in section 5.5.3.
147
Figure 5.26: Angelov capacitance expression with parameter definitions for Cgs (a) and Cgd
(b)
5.5.2
Angelovs capacitance expressions
The non-linear capacitance Cgs and Cgd can also be implemented as non-linear charges
Qgs and Qgd in the Angelov model. However the first and straightforward option was
to define them as capacitances, given the available data shown in Fig. 5.22. In this
case, the tanh-function is again used to define the non-linear capacitance equations,
in their most basic form, without cross coupling [104, 143]:
Cgs = Cgsp + Cgs0 (1 + tanh(1 )) (1 + tanh(2 ))
(5.32)
Cgd = Cgdp + Cgd0 (1 + tanh(3 )) (1 + tanh(4 ))
(5.33)
where 1 , 2 , 3 and 4 are functions of VGS and Vds , as follows:

1 = P10 + P11 VGS
(5.34)
2 = P20 + P21 VDS
(5.35)
3 = P30 P31 VDS
(5.36)
4 = P40 + P41 VGS
(5.37)
Coefficients Cgsp and Cgs0 of equation (5.32) can be obtained without further ado,
as is shown in Fig. 5.26a [126]. To understand this graphical approach, it has to
148
Figure 5.27: Modeled Angelov capacitances () compared with extracted values from small
signal measurements ( ), for VGS from -1.4 V to 0.8 V and VDS from 0 V to 2 V.
be taken into account that the tanh-function goes to minus one when its arguments
tends to . Therefore if VGS goes to large negative values in equation (5.34) then
1 will follow the same behavior, as a result the factor 1 + tanh(1 ) equals zero
in equation (5.32) and Cgs becomes Cgsp . Another characteristic of the hyperbolic
tangent function is that its value goes to zero, i.e., to the middle value of its range
[-1,1] when its argument becomes zero. Then in the middle range of one of the Cgs
curves (see Fig. 5.26a) the very rough approximation that tanh(1 ) and tanh(2 ) are
equal to zero can be made, and therefore Cgs in equation (5.32) becomes Cgsp + Cgs0 ,
as indicated in Fig. 5.26a. The same graphical approach can be assumed for the
coefficients Cgdp and Cgd0 of equation (5.33) as is shown in Fig. 5.26b as well.
The first consideration to determine the P -coefficients of equations (5.34), (5.35),
(5.36) and (5.37) is the charge conservation principle. This implies that the following
condition has to be fulfilled
Cgs
Cgd
=
VGD
VGS
(5.38)
which, at the same time, leads to the following relationships

P11 = P41
149
(5.39)
Figure 5.28: Modeled Angelov capacitances () compared with extracted values from small
signal measurements( ), for VGS from -1.4 V to 0 V and VDS from 2 V to 6 V.
P21 = P31
(5.40)
Problems of non-convergence in harmonic balance simulators could arise if this charge

conservation principle is omitted [143].
Equations (5.39) and (5.40) are not sufficient to solve all the P -coefficients. Additional
relationships can be obtained taking into account the consideration for determining
Cgs0 as explained above. In the middle range of the Cgs curves in Fig. 5.26a, the
argument of the tanh-function could be approximated by zero. Furthermore this
argument is zero for a specific bias condition. In Fig. 5.26a, the bias condition VGS =0.8 V and VDS =1 V is selected, therefore the following relationships can be established
[126]:
P10 + P11 (0.8) = 0
(5.41)
P20 + P21 (1) = 0
(5.42)
The same approach can also be applied to Cgd curves in Fig. 5.26b, which gives two
relationships for P30 , P31 , P40 and P41 . At this point, there are only six equations
for eight unknown P -coefficients. Ultimately, the following two approximations can
be made:
150
P30 = P20
(5.43)
P40 = P10
(5.44)
Finally after solving all these equations, initial values for all P -coefficients are obtained. The next step is to tune these values in order to match with the extracted
intrinsic values indicated in Fig. 5.22. This tuning again can be performed manually
or by an optimization procedure. The main restriction on these tuning processes is
that equations (5.39) and (5.40) should always be fulfilled. After doing some iterations, the results obtained for the non-linear capacitances are reported in Fig. 5.27
and 5.28. Like in the case of current modeling, the most difficult region to model
is the region where self-heating of the device is more preponderant (large value of
VDS and VGS , Fig. 5.28). Moreover, at this region, the gate drain space charge region (depletion region) is larger (with approximately the same transversal area), and
therefore the capacitance Cgd tends to be very small. This makes the tuning at this
region even more difficult, since the modeled Cgd value can easily fall to a negative
value. Ultimately, the challange is to make the tuned P coefficients obtained for the
first region (Fig. 5.27), lead to coherent values for the second region (Fig. 5.28). At
the end, compromised P coefficients valid for both regions were found.
5.5.3
Add-on parameters and power performance
Although correct non-linear current and capacitances modeling is fundamental for

large-signal operation, this is insufficient to make the model robust under different signal excitations. Particularly, one of the most difficult tasks is to make the
model work at high output powers for both low and high frequencies without major
convergence issues. Model fitting at low frequencies does not demand an accurate
characterization of the model parameters, for instance power measurements and simulations matching at 900 MHz are reported in Fig. 5.29a, which was obtained after
few iterations. Nevertheless a good fitting at 5.4 GHz was impossible to obtain by
changing the parameters described in subsections 5.5.1 and 5.5.2. Furthermore the
model exhibits non-convergence issues when simulations are performed at such high
frequencies.
To perform a finer tuning the following two aspects have to be taken into account.
Thermal effects do have an influence on the power behavior of the device and its model.
Even though thermal measurements were not performed for this modeling procedure,
thermal coefficients were obtained in an empirical way by tuning DC characteristics
under self-heating conditions, i.e., for the largest values of VDS and IDS . Nevertheless
thermal coefficients obtained from DC characteristics will not be the final solution,
since these coefficients also influence the capacitance characteristics under self-heating
151
5.6. Conclusions
Figure 5.29: Angelovs model power performance and LSNA measurements at 900 MHz (a)
and at 5.4 GHz (b)
conditions [143]. Therefore, a second round of iterations has to be performed in order

to have a simultaneous fitting in DC and capacitance characteristics.
Cross capacitance is another issue to be taken care of. This feature of the model can
be understood as the shared or common capacitance between Cgs and Cgd. As a
matter of fact, it is very difficult to have an absolute and precise separation of both
capacitances given that they come from a single physical characteristic, which is the
gate charge [143]. Then as a way to compensate and correct this effect, the cross
capacitance parameter P111 is provided as an additional parameter for the angles i
in equations (5.32) and (5.33) [143]. A typical range for this parameter is between
zero and 0.1, where zero corresponds to a null shared capacitance.
In order to have a better control and understanding of the effect of these last two
parameters at high frequency, it is recommendable to realize a manual tuning. Finally
after several iterations, the power performance response, shown in Fig. 5.29b, was
obtained at 5.4 GHz. Additional parameters to tune Angelovs model can be found
in [143]. Nevertheless the ones described until now were sufficient for the current
research purposes. Besides it does not make sense to strive for 100% accuracy when
commercial devices present tolerances in their characteristics.
5.6
Conclusions
In this chapter several device modeling aspects have been covered. The design of the
test fixture is the first step in the modeling process. It has been shown that correct
knowledge of propagation modes and oscillation conditions are crucial to construct a
152
5.6. Conclusions
trouble-free test board as well as to avoid instabilities and distortion during DC- and
S-parameter measurements. Test fixtures for two different devices have been studied. Once the test board is working properly, a good characterization of the board
is required in order to remove the parasitics from the measurements and to obtain
the actual intrinsic device features. For this purpose, two methods to describe the
extrinsic network have been developed: equivalent circuit and four-port networks.
The de-embedding of this extrinsic network can be realized afterwards, giving as a
result the S-parameters of the intrinsic device. The small-signal intrinsic parameters
are extracted using these S-parameters and conventional relationships. A large signal
model has been constructed using the empirical Angelov approach using DC measurements and the intrinsic device parameters. The developed model has proved to
have a good power performance at two different frequencies. Nevertheless the high
frequency response demands a fine tune of the model parameters as well as add-on
elements such as thermal coefficients and cross-capacitance. The modeling efforts of
this chapter are crucial for optimal power amplifier design, as will be shown in the
next chapter.
153
Chapter 6
WiMAX RF power amplifier

6.1
Introduction
Wireless communications pose a major challenge on RF amplifiers of current and

advent applications. First of all, requirements of higher data speeds have led to
the use of complex digitally modulated signals in OFDM mode, with the WiMAX
standard one of the most prominent representative applications nowadays. These
OFDM signals are famous for having a high peak to average power ratio (PAPR).
This means that in order to amplify them properly, amplifiers with a large linear
range (typically of class A) have to be utilized. On the other hand, most of the
current wireless applications are required to be portable, and therefore the power
consumption of the circuitry should be minimal. Then, the use of highly efficient
amplifiers, inherently non-linear, is also needed. One legacy solution opted for by
the industry is to use class-AB amplifiers, which represent a compromise solution for
these two antagonist requirements: linearity and power efficiency. Nevertheless this
has shown not to be enough, and therefore recent and abundant researches [145, 146,
118] have been realized to find better solutions by recurring to the use of linearizer
techniques in combination with non-linear high efficiency amplifiers. In this direction,
the class-E amplifier has been one of the main candidates for linearization due to its
high efficiency figure. This amplifier has been incorporated in envelope elimination
and restoration [118, 147] schemes to accomplish the target. Another approach is to
improve the efficiency of a linear amplifier, such as a class-AB, by utilizing dynamic
loads. In this direction, major research effects have been conducted on applying
Doherty techniques.
In this chapter, linear (class-AB) and non-linear amplifiers (class-E) will be designed
for WiMAX applications at 3.5 GHz. The device, employed for these designs, is the
GaAs HEMT FPD750, which has been modeled in chapter five. Conventional design
155
6.2. WiMAX standard

methodologies will be reviewed and a new method based on the concept of equivalent
capacitances will be developed. The efficiency of the linear amplifier will be improved
by using Doherty techniques aimed at fulfilling the stringent requirement of 9 dB
PAPR for WiMAX signals. A final comparison between the linear class-AB amplifier
and the Doherty amplifier, in terms of efficiency and linearity, will be conducted at
the end of the chapter.
6.2
WiMAX standard
WiMAX, which stands for Worldwide Interoperability for Microwave Access, is a

last-generation standard and technology for broadband wireless access. It is based on
the IEEE 802.16 standards. As a matter of fact, there are two standards: the first one
approved in June 2004, IEEE 802.16-2004, is targeted to fixed wireless access; and
the second one approved in December 2005, IEEE 802.16e-2005, is aimed to address
mobility.
The WiMAX Forum, established in 2001 and formed by a group of industry leaders
(including Intel, AT&T, Cisco, Samsung, Motorola), has been in charge of support
and promotion of the technology. The groups workforce is divided into multiple
working groups, which focus on regulatory, technical, and marketing aspects. The
certification working group has developed a WiMAX product certification program to
ensure interoperability between WiMAX equipment from different vendors worldwide.
This technology is expected to have a target range of up to 31 miles (50 km) and a
target transmission rate exceeding 100 Mbps, which would compete with legacy DSL
and E1/T1 lines (both expensive technologies to deploy and maintain) especially in
emerging markets [148]. Nevertheless, in practice these figures are different, WiMAX
Forum certified products will support downlink data rates of 65 Mbps (at close range)
to 16 Mbps (at distances of 9 to 10 km) in a typical 20-MHz channel bandwidth
deployment scenario.
6.2.1
Applications
The WiMAX forum describes WiMAX as "a standards-based technology enabling

the delivery of last mile wireless broadband access as an alternative to cable and
DSL". As such, this technology can provide a rapid and cost-effective broadband
access to sceneries that lack infrastructure (fiber optics or copper wire), such as rural
zones in developing countries. The deployment of broadband data and carrier-class
voice in this area can be achieved swiftly by placing strategically base station towers
which provide superior LOS (Line-of-Sight) or NLOS (Non-LOS) radio links to the
CPE (customer premise equipments), see Fig. 6.1. WiMAX features such as subchanneling, smart antenna systems and space-time coding, allow operators to deliver
156
6.2. WiMAX standard
Figure 6.1: WiMAX fixed and mobile wireless access scenarios
high-quality data and voice in NLOS links with limited spectrum.

In these days, many hotels, universities, transportation hubs and coffee shops have
Wi-Fi access points which provide wireless Internet access to the customers. Wi-Fi,
based on the IEEE 802.11 standards, is a short range system, typically tens of meters,
that uses unlicensed spectrum to provide access to the network. In this context,
WiMAX becomes a complement of this technology in the sense that it can serve as
a backbone for these 802.11 hotspots [148], see Fig. 6.1. Alternatively, customers
can connect mobile devices such as laptops and handsets directly to WiMAX base
stations without using 802.11. This configuration will provide users with broadband
connectivity over large coverage areas compared with 802.11 hotspots small coverage.
Mobile devices connected directly to WiMAX base stations likely will achieve a range
of 7 to 9 km, because the mobility factor makes the radio links more vulnerable.
Fixed wireless access technologies, before WiMAX, have already existed for many
years, but most of them did not succeed because of economic, capacity and compatibility issues. Those technologies were proprietary, and they were expensive because
they use chipsets from adjacent technologies, of which they use the physical layer
and bypass the medium access control layer by designing a new one. Additionally,
they required LOS conditions with the respective high tower infrastructure in many
cases. The data throughput was low and non-competitive with DSL and cable capacity. However, fixed wireless technology is making its comeback with the introduction
of WiMAX, and unlike those predecessor proprietary solutions, WiMAXs standardized approach offers economies of scale to vendors of wireless broadband products,
significantly reducing costs and making the technology more accessible [148]. Many
companies, that were offering proprietary solutions, now offer WiMAX based solutions.
157
6.2. WiMAX standard
6.2.2
IEEE 802.16-2004, fixed wireless access
The first draft of this WiMAX standard established operating frequencies in the range
between 10 and 66 GHz. At these frequencies, broad bandwidth is available and high
data rates can be achieved, however the propagation conditions are not optimal:
the propagation losses are high and line-of-sight condition is necessary. As a result,
the installation of a large number of base stations with high tower infrastructure is
demanded and the cost of deployment is accordingly high. Hence, a new frequency
range between 2 and 11 GHz was added to the standard to relieve the stringent
propagation conditions. Diffraction phenomena (propagation paths bending around
obstacles) and lower propagation losses are some of the advantages in this frequency
range. More specifically, the following allocated bands in the range between 2 and 6
GHz are being or will be exploited in the near future:
Licensed 2.5 GHz: the bands between 2.5 GHz and 2.7 GHz have been allocated
in Brazil, Mexico, US, and some Southeast Asian countries.
Licensed 3.5 GHz: this is the main band allocated for fixed WiMAX access in several
countries in Europe, Asia and South America. Covering 300 MHz of bandwidth, from
3.3 GHz to 3.6 GHz, this band offers great flexibility for large-pipeline backhauling
to wide area networks.
Unlicensed or licensefree 5 GHz: the Unlicensed National Information Infrastructure (U-NII) bands have three major frequency bands: low and mild U-NII bands
(5150 5350) (802.11a), WRC (new) (5470 5725), and upper U-NII / ISM band
(5725 5850). Wi-Fi exists in the lower and middle U-NII bands, most WiMAX activities are in the upper U-NII 5725 to 5850 bands because there are fewer competing
services and less interferers there.
Physical layer
The transmission modes- that determine the burden on the RF power amplifier - that
can be found in this standard are the following [148]:
WirelessMAN-SC and MAN-SCa: this consists of only a single carrier modulation.
SC is mainly applied in the range between 10 and 66 GHz and SCa is applied in the
range between 2 and 11 GHz.
WirelessMAN-OFDM: this specifies a 256-carrier OFDM multiplexing scheme and
the multiple access of different subscriber stations (SSs) is time-division multiple
access (TDMA) based.
WirelessMAN-OFDMA: this considers a 2048-carrier OFDM scheme and the multiple access is provided by assigning a subset of the carriers (subchannelization) to
an individual receiver, so this version is often referred to as OFDM multiple access
158
6.2. WiMAX standard

(OFDMA).
Each of the above-mentioned carriers can be modulated using BPSK, QPSK, 16QAM or 64-QAM. The modulation is adapted to the specific transmission requirements and/or propagation conditions. The combination of the multicarrier with a
modulation mode can provide a maximum rate of 75 Mbps.
Medium access layer

The WiMAX standard was aimed mainly for point-to-multipoint topologies, in which
a base station distributes traffic to many subscriber stations. This configuration
uses a scheduling mechanism that is much more efficient because subscriber stations
transmit in their scheduled time slots and do not contend each other. However,
subscriber stations need to contend when they access the channel for the first time.
Unlike IEEE 802.11, WiMAX does not require subscriber stations to listen to each
other. This scheduling design suits WiMAX networks because subscriber stations
might gather traffic from several computers and have steady traffic. In contrast,
IEEE 802.11 stations usually have bursty, or intermittent traffic and contend every
time before transmitting.
In addition to the point-to-multipoint mode, IEEE 802.16 provides a mesh mode
(see Fig. 6.1), in which the subscriber stations can communicate with each other.
The mesh mode can help relax the line-of-sight condition and lower the deployment
costs for high-frequency bands by allowing stations to relay traffic to each other. In
this case, a subscriber station that does not have line-of-sight with the base station
can transmit/receive its traffic from another station that does have line-of-sight (see
Fig. 6.1).
Bidirectional communication can take place by using either Time Division Duplexing
(TDD) or Frequency Division Duplexing (FDD). The MAC layer also provides Quality
of Service (QoS) to each connection by means of an adaptive allocation of the uplink
and downlink channels. Finally, the MAC layer supports many transport technologies,
such as Ethernet, ATM, IPv4, and IPv6. This gives flexibility to the service providers
to incorporate WiMAX in their transport technologies.
6.2.3
IEEE 802.16e-2005, mobile wireless access
As a matter of fact, this is not a new IEEE standard, but it is an amendment of the
IEEE 802.16-2004 for fixed wireless access. This more complete version comprises
corrections to the original IEEE 802.16-2004 as well as it provides the characteristics
to support subscriber stations moving at vehicular speeds, and herewith specifies a
system for combined fixed and mobile broadband wireless access.
159
6.2. WiMAX standard

Physical layer
The main contribution on this level is an enhanced version of OFDMA called Scalable OFDMA (SOFDMA). OFDMA uses a multicarrier modulation in which the
carriers are divided among the users to form subchannels. For each subchannel, the
coding and modulation are adapted separately, so that in conditions of good signal, a highly efficient 64-QAM coding scheme is used, whereas where the signal is
poorer, a more robust BPSK coding mechanism is used. In intermediate conditions,
16-QAM and QPSK can also be employed. SOFDMA supports channel bandwidths
between 1.25 MHz and 20 MHz, with up to 2048 sub-carriers. Other physical features
include support for Multiple-in Multiple-out (MIMO) antennas in order to provide
good NLOS (Non-line-of-sight) characteristics (or higher bandwidth).
Medium access layer

For the mobility scenario, highly efficient power amplifiers are required. Additionally
in this layer, power-saving mechanisms and sleep modes to prolong the battery life
of the mobile terminal were established in this standard. IEEE 802.16e also supports hard and soft handoffs mechanisms to provide users with seamless connections
as they move across coverage areas of contiguous cells. Another improvements for
mobile terminals comprise a real-time polling service to provide enhanced QoS, a hybrid automatic repeat request (H-ARQ) scheme to retransmit erroneous packets, and
privacy key management schemes to help distributing encryption keys.
6.2.4
WiMAX transmitter
A simplified block diagram corresponding to a WiMAX transmitter is reported in

Fig. 6.2, based on [149]. The digital information coming from the upper layer is
first randomized in order to avoid long sequences of 0s or 1s. Then, a forward error correction (FEC) coding is applied to correct bit errors happening during signal
transmission. After that, an interleaver rearranges the bit sequence with the purpose
to protect against block (or burst) errors that come along with fading or signal level
drops or other similar RF conditions. The serial bit sequence coming from the interleaver is converted in a parallel sequence and a modulation (BPSK, 16QAM, etc) is
applied next. For the OFDMA case, the carriers to be transmitted are a subset of
the available carriers, and therefore a mapping of part of these carriers is performed
in the OFDMA burst mapper. Until this point, the data is in the frequency domain
and comprised of a set of complex-valued symbol-based carriers. The next step is
to convert it into time domain which is realized in the Inverse FFT block. In this
block, these data carriers plus additional pilot carriers are combined to form an FFT
block, to which the IFFT algorithm is applied. Pilot carriers are necessary in order to
extract the symbols absolute phase as well as the phase and the state conditions of
160
6.2. WiMAX standard
Figure 6.2: WiMAX transmitter block diagram [149]
the transmission channel. Guard periods are added to the time-domain IQ sequence,
obtained from the IFFT block, with the purpose of reducing multipath distortion.
After that, a baseband filter is applied to the IQ sequences and passed to the digital
to analog converter (DAC). Finally the signal is upconverted to the carrier frequency
by a quadrature modulator, and transmitted by the antenna.
Power classes
The output power of a subscriber station (SS) or base station (BS) is normalized in the
standard IEEE 802.16-2004 [150] by defining power classes. For a station operating
in a WirelessMAN-OFDM air interface, the power classes are reported in Table 6.1.
The term PT x,max refers to the maximum average transmit power considering all
non-guard subcarriers. Likewise, for stations operating in WirelessMAN-OFDMA
mode, the power classes reported in Table 6.2 are established. A specific power class
associated to a particular MAC profile, RF profile and duplexing selection mode [150]
becomes the system profile of a WiMAX station.
161
6.2. WiMAX standard

Table 6.1: WirelessMAN-OFDM power classes profiles
Identifier
profC3_0
profC3_14
profC3_17
profC3_20
profC3_23
Transmit power performance

PT x,max < 14 dBm
14 PT x,max < 17 dBm
PT x,max 23 dBm
Table 6.2: WirelessMAN-OFDMA power classes
Class identifier
Class 1
Class 2
Class 3
Class 4
6.2.5
Transmit power
PT x,max 30 dBm
WiMAX OFDM PAPR and CCDF
The benefits and advantages of using OFDM in WiMAX is challenged by the requirement of an amplifier capable of handling the large crest factor (CF) or PAPR that
these OFDM signals exhibit.
Given x(t) as the time-domain representation of an OFDM symbol, composed of N
orthogonal sub-carriers within the period [0, T >, the PAPR of this symbol can be
defined as:
2
max |x(t)|
P AP R =
t[0,T >
Pav
max |x(t)|
=
t[0,T >
n
o
2
E |x(t)|
(6.1)
where E{.} is the expected value operator, which is used to calculate the average
power (Pav ) of the OFDM symbols.
A first theoretical analysis tells us that the maximum PAPR value is equal to the
number of subcarriers N [151]. This means, for instance, that for a 256 OFDM system,
a maximum PAPR of 24 dB could be expected. Nevertheless, large-value PAPRs occur
relatively rarely since most of the transmitted power is concentrated in signals of low
amplitude. Therefore, the statistical distribution of the PAPR should be considered
as well. The Complementary Cumulative Distribution Function (CCDF ) can be used
to evaluate this power distribution. The CCDF is defined as the probability that a
variable is higher than a specific value. Hence, if the variable is PAPR, then the
CCDF of a determined P AP R0 value, can be defined as:
162
6.2. WiMAX standard
Figure 6.3: IEEE 802.16e-2005 WiMAX OFDM time domain signal (a) and complementary
cumulative distribution function (CCDF) (b)
CCDFP AP R (P AP R0 ) = P r[P AP R > P AP R0 ]
(6.2)
CCDF plots use units of percentage for the y-axis and relative power (dB) for the
x-axis. Power on the x-axis is relative to the signal average power, so 0 dB is the
average power of the signal. Then, for instance a marker value in the plot of (4 dB,
10%) means there is a 10-percent probability that the signal power will be 4 dB or
more above the average power.
To illustrate these concepts the CCDF of a WiMAX signal is obtained using the
simulation tools of Agilent for WiMAX IEEE 802.16e-2005. The simulated OFDM
signal has the following parameters: input power= -10 dBm, carrier frequency=3.5
GHz, modulation technique 16-QAM, code rate= 1/2, and bandwidth= 10 MHz.
The corresponding CCDF as well as the time-domain signal are reported in Fig. 6.3.
In order to define the PAPR, the marker is placed in the point corresponding to a
0.1% probability, which gives an x-value of 8.2 dB (PAPR). This means that there
is a probability of only 0.1% that the signal power will be 8.2 dB or more above the
average power. This 0.1% probability is utilized conventionally to define the PAPR
[152, 153]. There is not a unique value that characterizes the PAPR in WiMAX
application since this depends on the specific parameters of the utilized OFDM signal
such as number of subcarriers, modulation, bandwidth, etc. However, it is normally
reported to be about 10 dB to 12 dB [151, 152].
In case of a compressed signal, clipping reduces the PAPR, and the CCDF curve
shifts to the left as large PAPR-values become less likely. An uncompressed OFDM
163
6.3. WiMAX class-AB and class-E power amplifier design using equivalent
capacitance concept
signal approximates a white Gaussian noise process by the central limit theorem as
the number of OFDM subcarriers increases. The PAPR for such a Gaussian noise-like
signal is itself a random process exhibiting a chi-square distribution with one degree
of freedom. The CCDF for this process is defined as:
CCDFAW GN (P AP R0 ) = exp[(P AP R0 )]
(6.3)
The CCDF corresponding to this Gaussian noise input provides a reference curve
called AWGN_ref in Fig. 6.3b. The CCDF curve of a compressed signal will fall to
the left of this reference.
The technique of backing off from an amplifiers full output power is often used to ensure linear operation and minimum distortion. Under WiMAX conditions, this would
imply to operate the amplifier 10 dB below its maximum output power. However
at this level the power efficiency is very poor. Therefore, an efficiency enhancement
technique, such as a Doherty amplifier can be used to compensate the low efficiency
at and above the 10 dB back-off range. These two techniques will be presented in the
following sections.
This first technique of backing off will be presented with the design of a class-AB
power amplifier using the concept of equivalent capacitance. This concept will also
be applied to the design of a class-E amplifier aimed at being utilized in an EER
amplifier system. The second technique will be described with the design of two
Doherty amplifiers aimed at providing 6 and 9 dB of power efficiency improvement.
In the abscence of back-off for the linear amplifier or of an efficiency improvement
range in the Doherty amplifier would cause signal clipping and compression. This
produces two types of distortion: in-band distortion would result in a distorted Error
Vector Magnitude (EVM) and consequently in Bit Error Rate (BER) degradation.
The out-of-band distortion would affect the ACPR performance by increasing the
adjacent channel interference level. Then in order to validate the applicability of
these designs for WiMAX, the EVM and the ACPR have to be verified at the end.
6.3
WiMAX class-AB and class-E power amplifier

design using equivalent capacitance concept
Many of the techniques to design class-AB and class-E amplifiers come from procedures applied successfully at low frequencies. Nevertheless, there has been a trend to
keep using these procedures also at high frequencies. The general approach in this
case is to use low frequency solutions as initial design values, and then by the application of optimization procedures with non-linear simulations, to correct or to tune
these values to obtain high output power and/or efficiency [118, 154, 155, 156, 157].
164
capacitance concept
Figure 6.4: Simplified device model for class-AB (a) and class-E (b)
Alternatively load pull measurements/simulations may be used, as well. The point

is that after these blind optimization or iteration procedures, a legacy class-AB
amplifier may end up being a class-F amplifier, or a class-E amplifier may turn into
a class-FG amplifier, if time domain waveforms or load-lines are not checked.
It is also well known that simplified transistor models such as a current source (classAB) or switch (class-E) used in low frequencies methodologies can no longer be applied
at high frequencies, because the devices intrinsic non-linear capacitances, non-linear
currents and dispersion effects play a crucial role at high frequencies [143].
What is proposed in this section is to design a class-AB and class-E power amplifier
by determining an equivalent capacitance value that gathers most of the devices
non-linearities and non-idealities. Once this value is determined, the procedure to
design the amplifier is straightforward and classical class-AB or class-E operation
with their unique characteristics is guaranteed at high frequencies without recurring
to optimization procedures.
6.3.1
Simplified models and legacy design procedures for classAB and class-E amplifiers
The two cases will be presented and analyzed separately in the following paragraphs:
Class-AB amplifier and device-current model

Low frequency methodologies assume a simplified device model for class-AB operation:
a current source shunted by a constant output capacitance (generally only Cds ) and
resistance (Rds ) is all what is required, see Fig. 6.4a. A constant transconductance
gm is usually considered. Then, in order to design an amplifier in class-AB operation,
the device is biased slightly above cut-off (25%) [14] or in a sweet spot bias region
to reduce distortion. The optimal load to obtain the maximum output power is
determined as follows:
165
capacitance concept
The real part is calculated based on the maximum current and voltage excursions:
RoptAB =
4v
Vbreakdown Vknee
=
4i
Imax
(6.4)
This is also known as Cripps method [14]. Nevertheless, strictly speaking the optimal
real value indicated above corresponds to class-A and class-B operation. This value
has to be corrected by a factor of approximately 0.95 (see Fig. 2.15) to have the proper
value for class-AB operation. The imaginary part is calculated as the negative of the
reactance value of the output capacitance, by which usually only Cds is considered:
XoptAB =
1
jo Cds
(6.5)
where o is the angular frequency in radians/second.

The impedances at the harmonic frequencies are set to short-circuits in order to suppress the higher harmonics generated by the truncated sinusoidal current waveform.
As it was mentioned above, these values are considered to be initial values since they
are based on a simplified current-model of the device. Then, an optimization procedure starting from these values is performed in order to obtain maximum output
power and/or efficiency. The actual model of the device shown in Fig. 6.5 (see also
chapter 5, section 5.5) raises several questions about this procedure. First of all the
device is not unilateral, but bilateral due to the effect of Cgd . The intrinsic capacitance seen at the output of the transistor is influenced not only by Cds , but also by
Cgd and Cgs . The two latter are even non-linear depending on VDS and VGS . Nevertheless there has been an effort to account for Cgd as part of the output capacitance
[158], assuming Cgd has a constant value. On the other hand, the intrinsic output
resistance Rds may not be constant over the frequency range since it presents dispersive effects in some cases. Additionally, the non-linear capacitance Cgs has a large
influence on the actual conduction angle and waveform shape at the intrinsic device
gate [14]. This justifies the idea of employing an equivalent bias-dependent output
capacitance as a way to combine all effects into one parameter.
Class-E amplifier and switch model
In class-E amplifiers the device is overdriven such that it behaves more like a switch
than as a current source, and it is therefore modeled as such (see Fig. 6.4b). A
network, added to this switch, is tailored such that ZVS (zero voltage switching) and
ZDVS (zero derivative voltage switching) class-E conditions are fulfilled and therefore
the highest efficiency is obtained [15, 16], see also chapter two section 2.6.2.
Class-E amplifier configurations based on lumped components have been used in applications with frequencies up to 2 GHz approximately. At higher frequencies, an alterna166
capacitance concept
Figure 6.5: Angelovs FET device model (see section 5.5)
tive methodology based on distributed elements [23, 24] has been proposed and widely
used in later works for frequencies up to and around 10 GHz ([118, 154, 155, 156, 157]).
Like in the class-AB methodology, most of these recent class-E design procedures make
use of an optimization process to correct initial assumptions and idealizations, which
may unintentionally lead to an other class of operation.
Design procedures [118, 154, 155, 156, 157] using distribute element techniques have
the following common steps:
The device output capacitance is considered linear and it is estimated from Sparameter measurements or simulations. Usually only Cds is considered and
Cgd is neglected. The bias point(s) used for this extraction is (are) usually not
indicated.
The optimal load at the fundamental frequency is obtained by using the formula
developed in chapter four section (4.2.1) and indicated again in equation (6.6)
[23, 24]:
Zopt =
0.28 j49
e
o Cout
(6.6)
where o is the angular frequency in radians/second and Cout is the output

capacitance, conventionally assumed to be equal to Cds . The loads at higher
harmonics are considered open circuits or alternatively they can be considered
to be reactive components.
167
capacitance concept
Since these loads do not give the optimal power amplifier figures (because these
loads were based on ideal conditions), an optimization procedure on the load
values (usually till the third harmonic) is performed by using a non-linear model
of the device.
There are several remarks on this procedure that arise again from observing the actual
nonlinear device model (Fig. 6.5). First of all, the output capacitance to be used is
not solely determined by Cds , but also by Cgd [159, 160], which is mainly a nonlinear capacitance. Therefore it is very unlikely that a linear capacitance, usually
Cds , obtained from a specific bias point and under small conditions (S-parameters)
represents the actual output capacitance of the device under an over-driven regime.
Moreover, the equation indicated in (6.6) is obtained by assuming an ideal switch. In
reality, the actual active device has an associated on-resistance and finite transit time,
which makes that this device behaves differently from an ideal switch. Relatively
new research works have been oriented to deal with these issues. Research works
oriented to define formulas specific for non-linear output capacitance can be found in
[96, 99, 109, 161]. There also have been efforts to include the effect of Cgd capacitance,
considering this latter as a linear capacitance [159, 160]. Other research works have
been oriented to include the effect of the on-resistance and finite DC-feed inductors
[161]. Nevertheless none of these works deals with all the effects at once, although
a major effort on this can be found in a paper by Choi [159]. On the other hand,
an interesting idea of replacing this non-linear capacitance by an equivalent linear
capacitance can be found in research work by Suetsugu [96], although this leads to
cumbersome formulas.
From all the above, it can be noticed that a common issue of the legacy design procedures for class AB and class E power amplifiers is the inaccuracy to determine the
output capacitance. This cannot be defined in an accurate/straightforward way by using formulas due to the complexity of the network and the non-linearities dependency
on the involved elements. What is proposed, and described in the next subsection, is
an alternative way to calculate these values by using a non-linear device model and
test bench.
6.3.2
Equivalent capacitance for class-AB and class-E power

amplifier modes
What is proposed in this paragraph is a way to find an equivalent capacitance that

takes into account most of the non-linear and non-ideal features of the device and
that can still be used in equation (6.5) (for class AB) or equation (6.6) (for class E).
In contrast to previous research works [96, 158], this procedure only requires a very
simple simulation test bench in order to obtain this value. Although this procedure
may be evident for class-AB operation, it has not been clearly established before for
use in class-E designs, to our knowledge. For this purpose, a test procedure, which
168
capacitance concept
Figure 6.6: Test bench to determine equivalent capacitance
uses a non-linear model of the device from the start on, is elaborated and described
below.
First of all, the device is biased for class-AB or class-E operation and is driven such
that the maximum excursion is reached for class-AB (or cut-off and saturation region
for class E) by applying a high-power sinusoidal waveform at the input (see Fig. 6.6).
It has to be remarked that all the extrinsic parasitics have to be disabled during this
simulation, because otherwise this will influence the value of the equivalent capacitance. Then shunt loads, consisting of a resistive plus an inductive part, are presented
at the intrinsic lead of the device. For class AB, the initial value of the resistive part
is calculated according to equation (6.4) in order to reach the maximum excursion.
For class-E operation, this value is chosen such that cut-off and saturation regions
are reached. Next, the inductive part values are chosen such that they eliminate the
reactance of the output capacitance of the device. First trial values give the load line
as indicated in Fig. 6.7 (line with circles), which looks like an ellipsoid. As it can be
observed, this value does not compensate completely the reactive part of the device.
If the value of the shunt inductive part is increased, a point will be reached where the
load line will not longer show hysteresis, indicating that the global non-linear output
capacitance has been compensated by a linear inductive reactance (line with squares
in Fig. 6.7). Notice that the looping may not be cancelled completely by just adding
a linear inductance. Then the following relationship can be established:
XCeq = XL
1
= o L
o Ceq
(6.7)
In this way the equivalent capacitance can be determined and used later for designing
a class-AB or class-E power amplifier. The added value of the proposed approach as
169
capacitance concept
Figure 6.7: Load line at the intrinsic drain for class-E operation and for a starting load
(circles) and the optimal load (squares)
compared to the classical design procedures has been demonstrated in detail for the
case of the class-E amplifier in [97].
6.3.3
3.5 GHz class-AB and class-E power amplifier design
The method will be applied to a FPD750 GaAs HEMT to design a class-AB and classE power amplifier at 3.5 GHz. The Angelov non-linear model developed in-house for
this device and already described in chapter five, section (5.5) will be used in this
section.
For class-AB operation, the real part of the optimal load is calculated as:
Ropt =
4v
Vbreakdown Vknee
15 1
=
=
= 38.8
4i
Imax
0.36
(6.8)
As indicated in section 6.3.1, this value has to be corrected by a factor of 0.95, giving
the value of 37 . Then in order to calculate the equivalent capacitance, different
inductive loads are presented till the reactive part is cancelled. This process can be
observed for two different loads in Fig. 6.8a, by which the device has been biased for
class AB operation. The equivalent reactance turned out to be -170j . As a result,
the optimal load can be defined as 37 //170j , which converted in series impedance,
becomes 36+8j . Providing this load at the fundamental frequency plus short-circuits
at the harmonics, the typical class-AB time domain waveform (intrinsic sinusoidal
drain voltage and truncated sinusoidal drain-source current) can be observed as shown
170
capacitance concept
Figure 6.8: Dynamic load line (a), and time domain voltage and current waveforms (b) at
the intrinsic drain for the class-AB amplifier
in Fig. 6.8b.
For class-E amplifier design, a similar test is performed as described above with the
device biased for class -E operation, obtaining XCeq =188 at 3.5 GHz, and therefore
Ceq =0.24 pF. A graph showing this procedure has been already shown in section
6.3.2 (Fig. 6.7). Based on this value, the optimal load for class-E operation can be
determined utilizing equation (6.6):
Zopt =
0.28 j49
e = 0.28(XCeq @o )ej49 = 34.7 + j40
o Ceq
(6.9)
Providing this optimal load at the intrinsic drain, i.e., without extrinsic parasitics,
the time domain voltage and current waveforms shown in Fig. 6.9a) are obtained.
Unlike in class-AB operation, in class E, the harmonics are kept as open-circuits as
is stated in the original work [23, 24].
As we can see, the ideal class-E waveforms are not completely realised. This is due
to the fact that the exciting source generates a sinusoidal signal, which rise time is
not short enough to provide the right excitation for a class-E waveform. This can
be improved by increasing the power, therefore shortening the rise time, but at the
expense of degrading the PAE. If the excitation signal is changed from sinusoidal to
a trapezoidal input signal, better class-E waveforms can be obtained. A trapezoidal
excitation signal is used with rise and fall time of 14 ps. (theoretical class E assumes
transition times equal to zero). As it can be observed in Fig. 6.9b, this resembles
more like the ideal class-E waveforms. The major difference is due to the fall-time
effect in the current waveform and the on-resistance in the drain voltage.
171
capacitance concept
Figure 6.9: Time domain voltage and current waveforms at the intrinsic drain for the class-E
amplifier using a sinusoidal excitation signal (a) and a trapezoidal excitation (b).
Table 6.3: Class AB and class E design load values
Operation mode
class-AB
class-E
load at f0
36+j8
34.7+j40
load at 2f0
zero (short-circuit)
infinite (open-circuit)
load at 3f0
zero (short-circuit)
infinite (open-circuit)
As it has been shown, the optimal load calculated using the equivalent linear capacitance concept provides a class-E operation without requiring major optimization
processes. Nevertheless, it is necessary to make an important remark regarding the
use of this procedure: it is only valid and applicable when the frequency of operation
is lower than the maximum allowable frequency for class-E operation [23, 24].
The following step is to implement this load with distributed elements. To realize this,
matching networks providing the loads for class-AB and class-E operation, indicated
in Table 6.3, are designed.
Two harmonics are sufficient to guarantee class-AB and class-E waveforms. Higher
harmonics are inherently short-circuited due to the intrinsic/extrinsic capacitances.
It has to be indicated that in the process of designing the matching networks the effect
of all the extrinsic parasitics have to be absorbed in the matching network. For these
particular designs, an additional stabilization network was defined in order to make
the amplifiers unconditionally stable over a broad frequency range. The stabilizations
of the device and amplifier were realized using series and shunt gate resistors (see
Fig. 6.10). Unfortunately, these networks introduce losses at the input that degrade
the PAE.
The input matching is then determined, which is basically the complex conjugate of
172
capacitance concept
Figure 6.10: Stabilization network for class-AB and class-E amplifier
Figure 6.11: Comparison of measured and simulated Class-E, VDS = 5.15V, VGS = 0.8V
(a) and class-AB, VDS = 8.3V, VGS = 0.8V (b) amplifier performance figures
the load seen at the gate lead. It is very important also to include in this calculation
the effect of the stabilization network.
The complete circuit, including all the parasitics and matching/biasing/stabilizing
networks, was initially simulated using ADS. The waveforms were verified and are
very much like the ones calculated at the intrinsic drain, that are given in Fig. 6.8b
and 6.9. The performance figures, based on this simulation, are presented in Fig. 6.11a
and 6.11b, for class-E and class-AB respectively. On the other hand, the actual implementation of the complete amplifier including biasing networks and input/output
matching can be observed in Fig. 6.12a for class AB and 6.12b for class E during LSNA
measurements. The measurement results, which can also be observed in Fig. 6.11a
173
capacitance concept
Figure 6.12: 3.5 GHz Class-AB power amplifier (a), and class-E power amplifier during
LSNA testing (b)
and 6.11b, present good agreement in output power, gain, drain efficiency and PAE
with simulation results for class-E. At 17 dBm of input power, the average difference
between simulated figures of merit and measured ones is 3%. As expected from theory,
the drain efficiency of the class-E amplifier (65.2%) outperforms the drain efficiency
of the class AB amplifier (42%) at the same input power (17.5 dBm). For the classAB amplifier, good agreement between simulation and measurements is obtained for
output power and gain (an average difference of 1% at 18 dBm of input power) while
efficiency figures tend to deviate more (10.5% at 18 dBm of input power), mostly
due to the tolerance values of the device and bonding wires. Nevertheless, this gives
enough arguments to state that the intrinsic waveforms are quite correct and correspond to class AB and class E respectively, whereas optimization process applied in
other research works in order to improve efficiency might lead to a different class of
operation, if no proper care is taken.
Finally, the performance under 16-QAM WiMAX signals is presented. As proper
equipment to test the amplifier was not available, only the simulated performance will
be presented based on last-generation simulation tools of Agilent ADS for WiMAX
IEEE 802.16e-2005. The test conditions for both amplifiers were the same. These are
the main values for the test simulations: input power= 10 dBm, carrier frequency=
3.5 GHz, modulation= 16-QAM, code rate= 1/2 and bandwidth= 10 MHz. The
simulated output constellation with the corresponding relative constellation RMS
error (RCE or EVM), averaged over subcarriers, OFDMA frames, and packets are
shown in Fig. 6.13 for both class AB and class E power amplifiers. This relative
constellation error (RCE) in dB should not exceed 20.5 dB for the testing conditions.
The class-E power amplifier does not fulfill this condition. As it can be evidently
expected, the class-AB amplifier has better EVM performance compared to classE operation. To make its use feasible under this scenery, this amplifier has to be
linearized using pre-distortion for instance, or it can be included as part of an EER
amplifier system [118].
174
6.4. Doherty power amplifier
Figure 6.13: EVM performance of the class-AB (a) and class-E amplifiers (b)
6.4
Doherty power amplifier
As it was described in chapter two, section 2.5.1 and 2.5.2, the optimal load Ropt
for class-A and class-B power amplifiers is determined by the maximum voltage and
current ratings of the device (see Fig. 6.14a). The output power and efficiency reach
their maximum when this load is presented to the device. Nevertheless this maximum
performance only takes place when there is enough input power to produce maximum
current excursion and therefore maximum voltage excursion. The theoretical 50%
or 78% (class-A, class-B) efficiency are only obtained at this peak input power. In
order to have high efficiency at other input power levels, it is important to keep the
maximum voltage excursion, as in the maximum output power case. For instance,
when the current is half of the peak current, the voltage must have maximum excursion
as in the case of maximum output power. However, it is noticed that the voltage
excursion is only half of the maximum. In order to get this maximum voltage span,
the load has to change from Ropt to 2Ropt . This means that the load cannot be kept
constant, but should be dynamic in order to keep high efficiency. It is precisely this
characteristic of changing dynamically the load from Ropt to 2Ropt (or vice versa)
that is the unique and distinguishing feature of the classical Doherty amplifier which
will be described next.
175
Figure 6.14: Doherty amplifier: dynamic load behavior (a) and basic circuit (b)
6.4.1
Basic theory
The basic configuration of the Doherty amplifier can be observed in Fig 6.14b. It
is composed of two active devices connected by a quarter wavelength inverter at the
output and a 1:1 divider at the input. Additionally a 90 transmission line is added
in the lower branch in order to compensate the phase difference due to the 4 inverter
of the upper branch. The upper transistor is always active, for low and high input
power, i.e., current i1 = [0, i1max ]. That is the reason why it is known as the main
or carrier transistor. The bottom transistor is operative only for the peak output
power levels, i.e., when i1 = [ i1max
2 , i1max ], and is known as the auxiliary or peaking
transistor. The load of the amplifier is equal to the optimal load (Ropt ) for maximum
output power at the main transistor. The main transistor is normally biased in classAB in order to have a compromise between linearity and efficiency, and the peaking
transistor is biased in class-C in order to control the transistor and make it operate
only during peak conditions, and of course because its efficiency is high.
The operation of this amplifier is based on two electrical mechanisms:
Inversion
This takes places at low power levels, i.e., i1 = [0, i1max
2 ], in which case only
the main transistor is working. The current in the auxiliary transistor is zero
(i2 = 0). Therefore R3 = Ropt , and the impedance seen by the main amplifier,
due to the inverter, is:
R1 =
RT2
R2
= T
R3
Ropt
176
(6.10)

with RT being the characteristic impedance of the inverter. Since in the range
[0, i1max
2 ] the optimal load has to be 2Ropt (see Fig. 6.14a), then R1 has to be
equal to this value. As a result, we can solve the value of RT :
2Ropt = R1 =
RT2
Ropt
RT =
2 Ropt
(6.11)
Load Pull
For the upper range of the signal, i.e., [ I1max
2 , I1max ], it is required that the
load of the main transistor changes from 2Ropt to Ropt . To achieve this, the
auxiliary transistor has to start operating. This transistor provides a current
i2 that modifies the value of the resistance R3 , and subsequently resistance R1 .
R3 is not longer Ropt due to the load pull effect of the current i2 . R3 can be
determined from the output node, as:
vo = io Ropt = i2 R2 = i3 R3
= R3 =
where: =
io
Ropt
Ropt = R3 =
i3
(6.12)
(6.13)
i3
io
The resistance R3 is transformed to R1 at the main amplifier by means of the

inverter, so:
R1 =
2
2 Ropt
RT2
= 2Ropt
=
R3
Ropt /
(6.14)
Since the goal is to provide R1 = Ropt , when i1 = i1max , then must be equal
to 1/2. This means that currents i2 and i3 must be equal. The way to relate i3
with i1 is by means of power conservation:
i1 v1 = i3 v3
i1
v3
v2
=
=
i3
v1
v1
(6.15)
Then, in the peak condition:

i1max
v2max
=
i3max
v1max
(6.16)
Considering that the main and the auxiliary transistors use the same drain bias,
v2max = v1max = VDD , and therefore i1max = i3max . As a conclusion it can be stated
that the peaking amplifier has to deliver as much current as the main amplifier (in
the peak condition) to pull the load from 2Ropt to Ropt . The possibility of utilizing
different drain bias in Doherty amplifiers has been investigated in [162].
177
Figure 6.15: Basic Doherty amplifier: current characteristics (a) efficiency versus output
power (b)
Similar maximum currents for the main and auxiliary transistors do not imply that
both transistors have to be of the same size. While the main transistor swings from
zero to Imax for an input voltage going from zero to vinmax , the auxiliary transistor
has to go from zero to Imax for a reduced voltage range going from V inmax /2 to
V inmax (see Fig. 6.15a). As a result, the transconductance gm2 of the auxiliary
transistor has to be twice as much as the transconductance gm1 of the main transistor.
Therefore the use of a larger transistor for the auxiliary device is necessary. By the
time this amplifier was invented [163], transconductance was not an issue as the
active devices were vacuum tubes, whose transconductance could be controlled easily
by additional grids. This tunable transconductance feature is not possible in modern
active devices.
In terms of performance, there are two conditions of maximum efficiency for a Doherty
amplifier: these are when the main transistor is driven at half and at full maximum
current. In these two conditions the main transistor exhibits maximum efficiency.
The efficiency in between these two conditions is lower because of the operation of
the auxiliary transistor, whose efficiency is low to moderate until it reaches maximum current. The output power range, ER, in which the efficiency is high, can be
determined as:
ER = PT otal (dBm)|i=i1max PT otal (dBm)|i=i1max /2

VDD imax /4
VDD imax

PT otal (dBm)|i=i1max /2 =
=

8
2
2 dBm
dBm
178
(6.17)
(6.18)
PT otal (dBm)|i=i1max

VDD imax /2
VDD imax
VDD imax /2

+
=
=

2
2
2 dBm
2
2 dBm
dBm
(6.19)
= ER = 6 dB
(6.20)
This is the output power range of a basic Doherty amplifier. This means that the
amplifier can operate 6 dB backoff from its maximum and still exhibits moderate
efficiency figures over this range. A theoretical diagram of this response is reported
in Fig. 6.15b.
6.4.2
Generalization of two-stage Doherty amplifier
The basic Doherty amplifier, just described, can provide 6 dB of efficiency improvement. Nevertheless in view of the PAPR values mentioned earlier (10-12 dB) it would
be very useful to extend this range to any theoretical value. The following is a generalization of the analysis presented in the previous section.
The variables are the same as the ones utilized in subsection 6.4.1. Additionally, let
us define i1T as the current of the main transistor at transition time, i.e., when the
auxiliary transistor starts to operate. This current is also the current associated to
the first maximum voltage excursion of the main transistor (see Fig. 6.14). Recalling
3
that is iio3 = i2i+i
, then this variable can take any of the following values:
3
i1 6 i1T
1
= < 1, p > i1T < i1 < i1max
p
i1 = i1max
(6.21)
3max
1max
where p = iiomax
= iiomax
considering both transistors have the same drain bias
voltage, and i1max , i3max and iomax are the maximum current values of i1 , i2 and io
respectively. Let us define also the factor k as
k=
i1T
i1max
As for the basic case we again consider two distinct cases:

Inversion
179
(6.22)

Only the main transistor is operating. Then the resistance R1 due to the inversion effect is:
R1 =
p
RT2
= RoptT = RT = Ropt RoptT
Ropt
(6.23)
where RoptT is the optimal load at the transition time and this must be
RoptT
2VDD
2VDD
1
=
=
=
i1T
k i1max
k
2VDD
i1max

V RoptT =
Ropt
k
(6.24)
Replacing equation (6.24) in equation (6.23)

Ropt
RT =
k
(6.25)
Load Pull
The auxiliary transistor starts to inject current i2 , changing the value of resistance R3 . This current increases till it reaches the maximum, and under
this condition the optimal load Ropt is obtained at the main transistor. In this
condition, due to the load pull effect:
R3 =
Ropt
p
(6.26)
then taking into account inversion effect and equation (6.25)

R1 =
2
Ropt
RT2
RT2
p Ropt
=
=
=
R3
Ropt /p
k Ropt /p
k
(6.27)
And this resistance R1 must be Ropt at the main transistor

R1 =
p Ropt
= Ropt = p = k
k
(6.28)
This equation means that the ratio between i1T and i1max is the same ratio
needed for i1max and iomax .
The values of R1 and R2 over the whole power range can be summarized as
Ropt
p
R1 = p Ropt
Ropt
i1 6 i1T
i1T < i1 < i1max
R2 =
i1 = i1max
180
Ropt
1
Ropt
1p
i1 6 i1T
i1T < i1 < i1max
i1 = i1max
(6.29)
Figure 6.16: 10 dB basic Doherty amplifier: current characteristics (a) and efficiency (b)
The efficiency range can be determined as in section 6.4.1:

ER = PT otal (dBm)|i=i1max PT otal (dBm)|i=i1T
PT otal (dBm)|i=i1T

VDD i1T /2

=
2
2 dBm

VDD i1max /2
VDD i2max /2
PT otal (dBm)|i=i1max =
+
2
2 dBm
2
2 dBm
(6.30)
(6.31)
(6.32)
Then, taking into account equation (6.28), equation (6.30) reduces to:
ER = 20 log(p )
(6.33)
Although this analysis is based on an oversimplification of the device characteristics,

it gives a first approach to define the devices characteristics when an efficiency range
is specified. In WiMAX, for instance, to keep an optimal efficiency over its 10 dB
of PAPR, a Doherty amplifier with 10 dB of efficiency range can be used. By using
equation (6.33), a value of p = 0.3 is determined. This implies that the auxiliary
transistor starts to operate when the main transistor is at one third of its maximum current, and also the maximum current of the auxiliary transistor is twice the
maximum current of the main transistor (see Fig. 6.16a). Additionally, the transconductance of the auxiliary transistor has to be three times the transconductance of the
main transistor. The theoretical efficiency characteristic is reported in Fig. 6.16b as
well. Broader high-efficiency ranges can be obtained with this generic two-stage configuration. However the efficiency between the two maxima drops with the increase of
the range. This approach has been used in practice to obtain up to 10 dB of efficiency
181
Figure 6.17: Asymmetric Doherty amplifier: basic schematic (a), current characteristics (b)
range. Following this procedure, a 10 dB two-stage Doherty amplifier at 950 MHz

was reported in [164], in which case two HBTs were used, one HBT of 840 m2 and
one of 3360 m2 emitter area. As a matter of fact, these device sizes correspond to
12 dB efficiency range, however 10 dB was finally obtained.
6.4.3
Asymmetric power divider for device size compensation
Up to this point, it has been concluded that the auxiliary transistor has to be several
times larger than the main transistor. Nevertheless, it is also possible to obtain
Doherty operation using devices of similar sizes. For this purpose, it is necessary to
employ an asymmetric power divider, which provides more power to the auxiliary
transistor than to the main transistor. The effect will be like having an auxiliary
transistor with higher transconductance. Moreover, asymmetric power dividers are
even required for devices properly sized according to Doherty size [164, 165]. The
lower gain of the class-C biased transistor, used as peaking transistor, has to be
compensated for in order to provide a flatter gain at the output.
A first estimation of the power divider ratio can be obtained based on the results
presented in [165], and this will be explained next.
A simplified Doherty amplifier is shown in Fig. 6.17a. It is assumed that an unequal
power divider 1 : n is used at the input, a constant transconductance gmm is realized
for the main transistor and gma for the auxiliary transistor. The input voltage is
normalized as is indicated in Fig. 6.17b, the maximum voltage for
the main transistor
is one, and the maximum voltage for the auxiliary transistor is n.
The following power relationship can be established at the input:
P in = P inm + P ina
182
(6.34)

P in = P inm + n P inm
1
P inm = 1+n
P in
n
P ina = n+1 P in
(6.35)
Then, this last relationship can be put in terms of voltages

(
=
1
vinm = 1+n
vin
q
n
vina = n+1 vin
(6.36)
To find the output current, the voltages in equation (6.36) have to be multiplied by
the corresponding transconductances. Additionally, it has to be considered that the
auxiliary transistor starts to conduct with a net voltage equal to vina p , see
Fig. 6.17b.
i1 = gmm vinm = gmm
r
i2 = gma (vina p ) = gma
vin
n+1
n
vin p
n+1
(6.37)

(6.38)
Then using equations (6.37) and (6.38) to find the ratio

i1
gmm
q
=
i2
gma
vin
n+1
n
n+1 vin
(6.39)
p
And this last equation is evaluated for maximum input voltage vinmax =
maximum currents i1 and i2

1
i1
p
gmm
pn 2
=
=
i2 max
1 p
gma
2 p
n+1
2 ,
i.e.,
(6.40)
Then, solving this equation for n

1 gmm 1 p
+ p
n=2
p
2 gma
2
(6.41)
Although this formula is based on a simplified device model, it can be used to make
a first estimation of the power ratio. For instance, for the legacy Doherty amplifier
(6 dB, p = 0.5) with two similar devices, the power ratio would be 1 : 2.9. For 10
dB and similar devices, a power divider 1 : 6.7 would be required.
183
Figure 6.18: Doherty amplifier with offset lines
6.4.4
Doherty technique using built-in amplifiers
As in the case of a class-E amplifier, when the Doherty amplifier was proposed, it
was applied at low frequencies where device parasitics are negligible. Nevertheless, its
application at very high frequencies brings up issues like extrinsic parasitic effects and
complex optimal loads instead of pure resistive loads. The application of the theory
described so far is no longer applicable. One solution would be to use complete
amplifiers instead of transistors. In this case, the optimal load would be a purely
resistive 50 and the theory described in earlier subsections could be applied again.
Another advantage would be that the carrier and peaking amplifiers can be designed
in a conventional way and integrated as a Doherty amplifier afterwards. However the
application of the Doherty technique in this case is not straightforward: compensation
transmission lines have to be added at the output of the carrier (CA) and peaking
amplifiers (PA) (see Fig. 6.18) [166, 167] in order to obtain a proper operation. This
compensation technique will be explained next.
The Doherty amplifier reported in Fig. 6.18 is a classical one with 6 dB of efficiency
range. The carrier and peaking amplifier have been matched for maximum output
power and 50 load. During impedance inversion operation, only the carrier amplifier works and sees a resistance R1 equal to 502 /25 = 100 (2Ropt ). During load pull
operation, the peaking amplifier injects current, pulling up the resistance R3 from 25
to 50 , by which the last value is reached when the currents are equal and maximum.
This resistance R3 keeps its value after the inversion, i.e., R1 = 50 . Likewise, the
25
peaking amplifier will see an impedance R2 of 10.5
= 50 at the maximum current.
The operation just described follows a Doherty characteristic, however some points are
missing from the analysis. The matching of the main amplifier has been sized for 50
load. This is the value which must be transformed internally, towards the drain, as
a resistance for maximum device power (Roptdevice ). Nonetheless, during inversion,
when 100 is presented to the carrier amplifier, this will not be reflected as twice
the resistance for device maximum power (2Roptdevice ), due to the effect of all the
184
Figure 6.19: Compensation lines effect at the carrier amplifier (a) at the peaking amplifier
(b)
lumped components in between. This has been simulated and can be observed in the
load line shown in Fig. 6.19a. In order to correct this response, a compensation/offset
transmission line can be added at the output. The length of this transmission line
can be tuned until a proper load line is observed as shown in the same figure. The
characteristic impedance of this line is set to 50 , such that it becomes transparent
when R1 becomes 50 due to the load-pull effect. The same correction can be
performed observing the intrinsic load value on the Smith chart [166].
A compensation line is also required at the peaking amplifier. During inversion operation, the load seen into the peaking amplifier must be infinite such that no power is
leaking from the main to the peaking amplifier. To this purpose an offset-line is tuned
to assure that the impedance is large enough to resemble an open circuit. This is realized by observing the output return loss (S22 ) in the Smith chart (see Fig. 6.19b).
Like the main amplifier, the impedance of this offset-line is set to 50 in order not
to affect the peaking amplifier during load pull operation.
6.4.5
Inverted Doherty power amplifier
A new configuration called inverted Doherty power amplifier has been introduced in
recent years with the aim to make this type of amplifier more compact [6, 168]. A
schematic of this configuration is shown in Fig. 6.20. In the inverted Doherty, the
load is connected to the carrier amplifier instead of to the peaking amplifier, and
the impedance inverter is connected to the peaking amplifier instead of to the main
amplifier.
The carrier amplifier and the peaking amplifier, indicated in Fig. 6.20, have both been
designed for a 50 load. At the output of the inverted Doherty amplifier there is a
25 load, that is converted properly when this amplifier is working.
185
Figure 6.20: Inverted Doherty amplifier schematic
The inversion and load pull mechanisms of a conventional Doherty amplifier are also
found in this inverted version, nonetheless these concepts are applied in a different
way.
Before explaining the functional characteristic, it has to be noted that this configuration also needs offset lines, as indicated in Fig. 6.20. These offset lines are 50
transmission lines. The offset line at the peaking amplifier is to guarantee that a low
impedance (or short circuit) is presented at the inverter (R2 ). If Ropt is the optimal
load to obtain maximum power at the carrier amplifier, the offset line at this carrier
amplifier is to assure that a load of 2Ropt is presented at the intrinsic device during
low power operation, i.e., when the peaking amplifier is not working. As a matter of
fact, the combination of this offset line with the delay, introduced by the matching
network of the carrier amplifier, behaves as it were an intrinsic impedance inverter.
Once the offset line functions have been explained, it is easier to understand how this
sort of Doherty amplifier operates. During low power operation, the function of the
inverter is to convert the low impedance value of the peaking amplifier (R2 ) to a high
value or ideally infinity (R3 ) such as that power from the carrier does not leak to the
peaking amplifier. When the peaking amplifier starts to operate, the impedance seen
at the carrier (R1 ) and peaking amplifiers (R3 ) will change due to the load pull effect.
When both amplifiers reach their maximum, these loads (R1 and R3 ) become 50 .
Since inverter and offset lines are 50 transmission lines, they are transparent for a
50 load, therefore resistances R11 and R22 are 50 as well, resulting in the correct
loading for the amplifiers.
After presenting this theory, we consider that this inverted Doherty amplifier could
be reduced to a conventional Doherty amplifier. If the offset line of the peaking
amplifier with the inverter is considered to be a single offset line, and the offset line
of the carrier is considered to be the net effect of the inverter plus the offset line of a
conventional Doherty, then this inverted Doherty amplifier could be seen as a normal
Doherty amplifier.
186
6.4.6
Three-stage Doherty amplifier
It was already mentioned in subsection 6.2.5 that WiMAX signals exhibit about 10
dB of PAPR, hence an amplifier with a efficiency range of 10 dB would be desirable to
obtain an acceptable overall efficiency. A generic two-stage Doherty amplifier could
provide this efficiency range, however its efficiency drops moderately when the output
power is below the middle range and therefore this design is not so optimal. A better
solution was suggested by Raab in [169]. This is a three-stage Doherty amplifier that
consists of two peaking amplifiers (P A1 and P A2 ) and one carrier amplifier (CA), see
Fig. 6.21a. Its efficiency response is flatter than for a two stages version as illustrated
in Fig. 6.21b.
This three-stage Doherty amplifier can be seen as the combination of two two-stage
Doherty amplifiers. One two-stage Doherty would be the conjunction of CA with
P A1 , and the other would be the conjunction of P A1 with P A2 . As it is observed in
Fig. 6.21b, three power regions can be distinguished. During low and medium power
conditions, CA and P A1 work as a conventional Doherty amplifier, while during high
power condition P A1 and P A2 work as another two-stage Doherty amplifier. In this
last case, P A1 behaves as a carrier and P A2 as a peaking amplifier for the carrier
P A1 . This also can be described in terms of inversion and load pulling effect. In
the low power region, only an inversion mechanism is exhibited since both peaking
amplifiers are off. In the medium power region, P A1 injects current, pulling down
the load seen by CA. In high power region, P A2 injects current pulling down the
load seen by P A1 , making this last one to reach saturation. Actually, there is also an
inversion mechanism in the medium power region as the load seen by P A1 is affected
by one impedance inverter.
Though the mathematical analysis for this Doherty amplifier was not presented in
the original work [169], this was developed thoroughly later in [170, 171]. The design
parameters can be determined based on the values of the factors 1 and 2 (see
Fig. 6.21b). These factors are also related to the target efficiency range ER2 in dB,
and the intermediate efficiency range ER1
1 = 10
ER1
20
2 = 10
ER2
20
(6.42)
(6.43)
For instance, ER1 can be chosen as the classical 6 dB efficiency range and ER2 would
be 10 dB in order to fulfill the WiMAX requirements. Hence, the corresponding
values are: 1 =0.5 and 2 =0.3.
The values of the characteristic impedance of the inverters are sized as follows
187
Figure 6.21: Three-stage Doherty amplifier schematic (a), efficiency range (b), currents
characteristic (c)
RL
1
(6.44)
RL
1 2
(6.45)
RT 1 =
RT 2 =
where RL could be 50 , or an intermediate value which is matched with 50 load

after all.
The devices sizes of the carrier and peaking amplifier P A1 and P A2 are related in
the following proportion:

1:

1
1
1
1 :
1
2
2 1
(6.46)
For the assumed values of 1 and 2 , this will imply device ratios in the proportion
of 1 : 2 : 3. These design values are initial values and should be tailored later by
optimizations and simulations.
An important detail of the mathematical analysis developed in [170, 171] is that the
current of the carrier amplifier reaches its peak at the first backoff ER1 (1 ) and stays
at this maximum value within the high power region (see Fig 6.21c). This means that
the linearity figure will be degraded more in this range due to the additional harmonics
generated by the carrier amplifier, which is sustaining a constant peak current.
188
6.4.7
Design of two-stage and three-stage Doherty amplifiers
All the theory, described so far, will be applied in this section to design a two-stage
and a three-stage Doherty amplifier. These amplifiers are aimed at complying with
the WiMAX 802.16e standard. It has been described that the peaking amplifier
needs a larger device than the one utilized in the carrier amplifier. However, for these
particular designs we had only one-size of devices at our disposition, which are the
Filtronics GaAs HEMT devices (FPD750). The modeling of this device has been
already explained in chapter five, section (5.5). Under this scenery, two alternatives
were proposed and developed:
- A two-stage Doherty amplifier using an asymmetric power divider in order to compensate for the device sizes. Though this alternative only provides 6 dB of efficiency
range, it is interesting to evaluate the performance of this amplifier with a WiMAX
signal of 10 dB PAPR.
- A three-stage Doherty amplifier using an asymmetric power divider as well as an
inverted Doherty technique. As a matter of fact, this is a new approach developed in
this thesis and it has not been reported before. Although this configuration allows us
to reach 10 dB of efficiency range, its complexity brings up gain and linearity issues.
In the following paragraphs a description of these two designs will be presented.
Two-stage Doherty amplifier

The methodology will be based on the technique developed for Doherty amplifiers
with built-in amplifiers, which has been already described in subsection 6.4.4.
carrier amplifier
The carrier amplifier is a class-AB amplifier already described in section 6.3 along
with the equivalent capacitance method.
peaking amplifier
The peaking amplifier is a class-C amplifier. Its design procedure follows a similar
methodology as for class AB and this will be explained next.
The real part of the optimal load in class C can be estimated based on the value
indicated for class AB in equation (6.8). In chapter two, the variation of the optimal
load (real part) with the conduction angle has already been presented in section
(2.5.2). For a conduction angle of about 3
4 , the optimal resistance in class C is about
189
Figure 6.22: Class-C amplifier intrinsic load line (a) and time domain voltage and current
waveforms (b)
1.3 times the optimal resistance in class B. As a result, based on the value indicated
in equation (6.8), the optimal resistance in class C would be around 49 .
The reactive part of the optimal load is found based on the equivalent capacitance
method. After performing simulations, this is found to be around 140j , the corresponding load line can be seen in Fig. 6.22a). As a result, the optimal load can be
defined as 49 // 140j , which is equal to 43+15j . Providing this load at the
fundamental plus short-circuits at the harmonics, the class-C time domain waveform
can be observed in Fig. 6.22b. Additional simulations were performed with other bias
conditions around the bias corresponding to 3
4 rad., giving load lines close to the one
shown in Fig. 6.22a), however the input power has to be varied accordingly. These
last simulations were done to verify the sensitivity of the class-C amplifier with bias,
since the final bias point has to be tuned within the complete Doherty amplifier.
A stabilization network such as the one indicated in Fig. 6.10 was added to guarantee
the amplifiers stability over a broad range. The input matching was calculated based
on the complex conjugate of the input impedance seen at the gate. A bias network
similar to the one used for class-AB was utilized also in this case. A first layout of
this class-C amplifier can be seen in Fig. 6.23 along with simulated performance. The
final layout has been completed when it was integrated within the Doherty amplifier.
Measurements of the class-C amplifier as such are not available.
Once the carrier and peaking amplifier have been designed, the connecting elements,
indicated in Fig. 6.24a, have to dimensioned.
It is important to remember that the reference impedance is 25 Ohm at the output
of the Doherty amplifier. However it is converted to 50 by utilizing a quarter wavelength transformer. 25 is used as a reference because when the peaking amplifier
reaches its maximum current, this resistance will become 50 due to the load pull
190
Figure 6.23: Class-C power amplifier layout (a) and simulated performance (b)
effect. In the following, a description of the connecting elements will be presented.

Power divider
Based on the formulation developed in subsection 6.4.3, the power divider should
have a 1:3 ratio for a Doherty amplifier with devices of the same size. However,
this ratio is too high as it would mean a drastic drop in the gain and PAE of the
complete amplifier. The class-AB has a gain of about 9 dB; and the power divider
would introduce 6 dB of insertion-loss, resulting in a Doherty amplifier of only 3 dB
of gain. Therefore this power ratio was reduced to 1:2, although this change still
introduces 4.8 dB of insertion loss. To implement this power divider, three options
were analyzed. These are the Wilkinson power divider, the rat race coupler and the
branch line coupler. The Wilkinson divider required a 103 transmission line. When
this is implemented in Rogers material RO4003C (r = 3.55, thickness=200 m) this
would need a line of 75 m width, which is impossible since the minimum track width
for the process used is 200 m. Therefore this option was discarded. The rat race
divider would require a transmission line of 87 (130 m) and it was discarded as
well. Finally the branch line divider requires transmission lines of 29 and 35 , which
are feasible and we opted for this solution.
Impedance inverter
This is the easiest element to design and implement: it is a 90 microstrip transmission
line with 50 impedance, since it is with this value that the load presented to the
carrier amplifier is 100 at average power and 50 at maximum power.
Offset lines (c ,p )
191
Figure 6.24: 6 dB Doherty power amplifier scheme (a) intrinsic device load lines (b)
The length of the offset line at the carrier amplifier is determined based on simulations
as explained in subsection 6.4.4 and indicated in Fig. 6.19a. This length was found to
be -20 (or 340). Since this line has the same impedance as the impedance inverter,
these lines can be joined in one transmission line of 70. The offset line for the peaking
amplifier was around -3, and therefore it was neglected.
Phase compensation line
According to the basic theory, this line has to be as long as the impedance inverter,
i.e., 90. This would be a good approximation if the matching circuits of the amplifiers
were implemented with lumped components, but this was not the case. The matching
circuits introduce additional delays that should be accounted for as well. The best
way to estimate the phase difference of the branches is by simulating the phase output
of both amplifiers. This difference is compensated with a line at the peaking amplifier.
This turns out to be a 112 transmission line. Additionally the branch line coupler
introduces a 90 delay difference between outputs, so the total compensation line
would be 202.
Auxiliary lines
The FET devices on the board are placed on a metallic strip. For this reason, an
additional straight transmission line at the carrier amplifier branch and a meander
line at the peaking amplifier branch were needed in order to put the FETs in line.
These straight and meander lines have the same electrical length.
A Harmonic Balance simulation of the complete amplifier was realized to verify Doherty operation. The intrinsic device loadlines of the carrier and peaking amplifier are
reported in Fig. 6.24b. As it can be observed, the carrier amplifier reaches maximum
192

voltage excursion at half of the maximum current, then it changes its load line due
to the load pull effect of the peaking amplifier. A notorious looping in the intrinsic
device loadline of the peaking amplifier can be observed. This could be justified considering that the load presented to the peaking amplifier is only 50 at maximum
current.
A final modification was performed before the circuit was fabricated. In order to
improve the gain and the PAE, the power divider ratio was decreased down to a 1:1
proportion. However the drop of the gain at high input power was steeper, as will be
shown in the final simulations and measurements further on.
Three-stage Doherty amplifier

In order to reach 10 dB of efficiency range, the Doherty configuration reported in
Fig. 6.25a was proposed. This configuration is composed of a carrier amplifier and
two peaking amplifiers as the conventional three-stage Doherty amplifier described in
subsection 6.4.6, nevertheless there are some differences. The proposed configuration
uses devices of identical size, while the conventional one requires three different size
devices. The two peaking amplifiers are connected to the carrier amplifier, while in
the conventional set-up only one peaking amplifier is directly connected to the carrier
amplifier. In the conventional configuration the power divider has a ratio 1:1:1, i.e.,
equal power division. In our configuration the ratio is 1:1:2. Actually this last factor
is what also makes the proposed scheme different from the one developed in [172].
In the present configuration, the carrier amplifier reaches its first voltage saturation
at about one third of the maximum current (see Fig. 6.25b). This is due to the
effect of the impedance inverter (50 ) and the load of 16 . As a result the carrier
sees a load of about 150 . Then, the first peaking amplifier injects current at the
inverter node, pulling down the load seen by the carrier amplifier. The second peaking
amplifier remains inactive. This first peaking amplifier injects current till it reaches
voltage saturation at about two third of its maximum. At this moment by the effect
of the inversion and load pulling, the carrier amplifier also reaches about two thirds of
its current. At the last stage, the second peaking amplifier becomes active injecting
current to the inverting node. This current will pull down the load seen by the carrier
amplifier as well as the peaking amplifier. At peak input power, the three amplifiers
reach their maximum current, and by the load pull effect, all the amplifier see 50 as
an effective load. Actually, the second peaking amplifier does not reach its maximum
current (see Fig. 6.25b), due to the power divider ratio. This ratio should be higher
for the second peaking amplifier, nevertheless this would be too detrimental for the
gain and PAE. Finally a compromised ratio had to be chosen. An alternative way to
increase the power at the second peaking amplifier is by increasing its drain bias.
A disadvantage of the conventional three-stage topology is that the carrier amplifier
stays at maximum current during the complete high power region (see Fig. 6.21c)
193
Figure 6.25: Three-stage Doherty amplifier scheme (a) intrinsic device load lines (b)
and, as it was explained earlier, this current saturation introduces unwanted harmonic distortion in the conventional three-stage amplifier. This effect is avoided with
the proposed topology since the carrier amplifier reaches maximum current only at
maximum input power, due to the load pull effect of the peaking amplifiers (see
Fig. 6.25b).
The carrier and peaking amplifiers are as the ones used by the two-stage Doherty
amplifier, however the connecting elements have to be redefined. For a 10 dB efficiency
range, a current and impedance factor of 0.3 is utilized. The load at the output of
the Doherty is 16 ( 50 0.3) and then a 28 /4 impedance transformer is used
to do the matching to 50 . The impedance inverter is a 50 /4 transmission line.
The 50 offset lines are defined as described in section 6.4.4, giving approximately
the same values as the two-stages Doherty amplifier. Initially, the power divider
ratio was set to 1:2:3, however this introduces too high insertionloss (7.8 dB), and
subsequently low gain and PAE. At the end, the power ratio was changed to 1:1:2
(-6 dB), sacrificing the current excursion of the second peaking amplifier. This power
divider was implemented by cascading a branch line coupler (1:1 ratio) similar to the
one used for the two-stage amplifier and a Wilkinson power divider (1:1 ratio). The
phase compensation lines were calculated based on harmonic-balance simulations.
Finally, auxiliary lines of the same electrical length were needed at the three branches
to place the three devices in line in the lay-out. The substrate material is Rogers
laminate RO4003C (r = 3.55, thickness=200 m). The final layout along with the
measurements are presented in the following sections.
194

Stability loop condition, Rollets proviso
Conventionally, the stability of a single stage amplifier is verified by using the k 4
stability factors (k > 1 and 4 < 1) or factor ( > 1) [39]. These conditions
guarantee that the impedance seen looking into either port of the device/amplifier
has a positive real part no matter what passive impedance terminates the other port
(i.e., in , out < 1). However, besides the fulfillment of those conditions, a more
fundamental system stability requirement has to be achieved. The two-port network
itself has to be stable, which, in terms of Control theory, means that no poles are in
the right half plane (RHP). Hence, a separate test is required to determine whether
the network contains any poles in the RHP. This condition is also known as Rollets
proviso.
The necessary and sufficient condition for unconditional stability can be restated as
follows [173, 174]
1. If the network is described using S-parameters defined with respect to the real
impedances Z01 , Z02 , then there must not be RHP poles when the network is terminated with Z01 , Z02 . Alternatively in term of Z-parameters, there must not be any
RHP poles if the network is terminated with open circuits.
2. k > 1 and 4 < 1, or alternatively > 1, for all frequency .
The first condition assures the stability of the system when it is terminated with the
impedance that defines the scattering matrix. The second condition assures stability
for all other passive terminations provided the first condition is true.
The first condition can be simply fulfilled if the S parameters can be measured, i.e.,
the device is stable in the measurement system. This is perhaps the reason why this
condition has been normally omitted. Nonetheless, this omission proceeds when the
design involves only one device (the measured device). Hence, when more than one
active device is involved in the network (or amplifier) the first condition can not be
assured [174, 175], and alternative methods have to be applied [173, 176, 177]. On
the other hand, a specific method to detect instability condition (first condition) has
been developed for the specific case of an amplifier with parallel devices exhibiting
symmetric layout. In this case, the first condition is analyzed by checking the presence
of potential odd-mode instabilities [178, 179, 180, 181]. However this method can not
be applied to a Doherty amplifier, which presents an asymmetric structure per se.
A method developed in [176] can be applied for Doherty amplifiers. This method is
based on Nyquists criterion. This is a graphical method that verifies the feedback
loop stability from how the complex locus (or Nyquist plot) of the open loop G(jw)
encloses the point 1 + j0. If the number of poles in the RHP of G(jw) is zero,
then the system is stable if the number of clockwise revolutions of G(jw) around the
point 1 + j0 is zero, i.e., if it does not enclose the point 1 + j0 in a clockwise sense.
The condition that the number of RHP poles must be equal to zero is superseded
195
Figure 6.26: Verification of Doherty amplifier stability by the Nyquist-criterion[176]
in the method by considering that the active devices are stable on their own and by
performing the Nyquist plot several times under different conditions. For instance,
this test has to be performed four times for the case of a 6 dB Doherty amplifier, as
is indicated in Fig 6.26. An ideal circulator is introduced at the interface port 1 and
the parameter S11 looking from the port I of this circulator corresponds to G1 (jw).
Then, this ideal circulator is moved to interface port 2 and an isolator is introduced
at port 1. Again S11 looking from the port I of the circulator is G2 (jw), and so forth.
At the end, none of these Gi (jw) has to enclose 1 + j0 in order to guarantee amplifier
stability. The ideal isolator can be implemented with a circulator, in which port I is
terminated with the reference impedance (50 ).
Another method that could be useful to analyze Doherty amplifier stability is the
one based on return ratio (RR) [173, 177]. To find a return ratio, let us consider a
network which includes N devices that can be modeled as dependent current sources.
One of these sources is selected, i1 = gm v1 , where i1 depends on the node voltage
v1 and this is then made independent by redefining i1 = gm vaux , where vaux is an
auxiliary voltage. Hence, a return ratio is determined as RR1 = v1 /vaux . The
same procedure is applied for a second source (keeping the first one independent or
inactive) giving another factor RR2 . This process can be continued for all N devices.
At the end, these factor RRi can be used to calculate the normalized determinant
function (N DF ) as
N DF =
N
Y
(RRi + 1)
(6.47)
i=1
Following the Nyquist criterion, it is established that the network (amplifier) is unstable if the locus of N DF encircles the origin in the clockwise direction. When the
device model does not allow access to the current source, the model can be replaced
by a small-signal model.
These last two methods were applied to the designed Doherty amplifier to verify the
196
Figure 6.27: Layout and actual implementation of the 6 dB Doherty amplifier
Figure 6.28: Layout and actual implementation of the 10 dB Doherty amplifier
197
Figure 6.29: Doherty performance: 6 dB DPA, VDS = 8.1 V , VGSc = 0.85 V and VGSp =
3.6 V (a); 10 dB DPA VDS = 8.1 V , VGSc = 0.85 V , VGSp1 = 2.8 V and VGSp2 = 4.2 V
(b)
stability. In both cases, there was no indication of instability. In Fig. 6.26, one of the
outputs for the first method is reported.
6.4.8
Performance and WiMAX compliance
The final layout of the 6 dB and 10 dB DPA can be seen in Fig. 6.27 and 6.28, along
with a picture of the final circuit during LSNA measurements.
The power and efficiency figures of merit (FoM) for the 6 dB and 10 dB Doherty
power amplifiers (DPA) are reported in Fig. 6.29a and 6.29b respectively. For the
6 dB DPA an efficiency range of about 6 dB is obtained, the PAE at peak power
is 31.3% and at 6 dB input backoff (IBO) it is 32%, while for the 10 dB DPA an
efficiency range of about 10 dB is obtained, however the PAE values are low due to
the high power drop in the power divider. The PAE at peak power is about 14% and
at 10 dB IBO is 15%, over this 10 dB range, the peak PAE is 29%. The maximum
output power is 30 dBm and 32 dBm for the 6 dB and 10 dB DPA, respectively.
The device model developed in chapter five was used for the design of the DPAs.
However, when measurements were performed, the correspondence between simulation and measurements were not good enough. The test fixture used for the extraction
of the model did not represent the actual physical conditions of the device when it
is mounted in the DPA. The device, in the test fixture, has source bonding wires
connected to a copper track, while the devices, in the DPAs, have source bonding
wires connected to a metallic carrier. As a result, a test fixture was developed to
duplicate those real conditions. The first difference found is that the source parasitic
198
Figure 6.30: Measured results for the class-AB PA (one device), the 6 dB DPA (two devices)
and the 10 dB DPA (three devices): PAE (a) and Gain (b)
inductance is much higher that in the original test fixture, while gate and drain parasitic inductances remains the same. The source inductance had to be changed from
0.18 nH to 0.42 nH. Additionally, the device Rds dispersion was added to the model
developed in chapter five. As a matter of fact, it results that Rds dispersion is a
more preponderant factor than the crosscapacitance (see Chapter 5, section (5.5.3)).
Therefore, the crosscapacitance was set to almost zero, and instead of this, the Rds
dispersion was used to correct the final model. It has to be noted that the simulations shown along the measurements in Fig. 6.29a and 6.29b are the ones with the
corrected device model. The agreement is more accurate for the 6 dB than for the 10
dB DPA. There is an additional factor that should be taken into account, which is
the grounding path among the devices. The ground path in the case of the 6 dB DPA
and 10 DPA is different and it should be taken into account somehow. Therefore, a
0.1 nH was added to the source inductances of the DPA devices in order to consider
this effect that is not present in the model of the test fixture.
A comparison of the PAE versus output power of the class-AB amplifier and Doherty
amplifiers is reported in Fig. 6.30. A remarkable increase of the efficiency range is
obtained in the DPAs, however at the expense of efficiency and gain. This could be the
main disadvantage of this efficiency improvement technique. Nonetheless this could be
attenuated by using power dividers with equal proportions at the output and devices
with different sizes, which would compensate the gain and efficiency. Alternative
solutions would be devices with higher gain or pre-amplifier stages, although this last
one would decrease the overall efficiency.
The performance of the amplifier at 3.3 GHz, 3.4 GHz and 3.5 GHz is presented in
199
Figure 6.31: measured PAE for three different frequencies: 6 dB DPA (a) 10 dB DPA (b)
Fig. 6.31. As it can be observed the matching network was broad enough to allow
Doherty operation at lower frequency. As a matter of fact, 3.3 GHz and 3.4 GHz are
also center frequencies of WiMAX bands. The performance figures increase at lower
frequencies, which is obvious due to the natural characteristic of the device gain.
Until this point, only one side of the problem has been evaluated. Linearity is the
other critical factor that has to be assessed. Normally, AM/AM and AM/PM behavior
as well third order intercept point are the reference FoMs. However, this is realized
with sinusoidal signals. A more relevant and realistic assessment could be achieved
if actual WiMAX signals were utilized. Hence, EVM and ACPR have to be used
as linearity FoM instead. To this purpose the WiMAX 802.16e simulation toolkit of
Agilent is used, since actual WiMAX instruments were not available at the moment of
the evaluation. The DPA models were co-simulated with the Ptolemy and envelope
simulators of ADS. The DPA model is an equivalent circuit model based on the
nonlinear device model and passive elements model. In order to reduce the processing
time, the ADS passive element models were replaced with small-signal models. The
performance and characteristic did not change with this replacement. The linearity
evaluations were done for the class-AB design and the 6 dB DPA. The 10 dB DPA
was not assessed due to its low efficiency figure. The signal used for this testing is a
64-QAM with 1/2 code rate, 10 MHz bandwidth and 8.2 dB PAPR at 0.1 % CCDF
( or 10.2 dB PAPR at 0.01% CCDF). This signal exceeded the efficiency range of the
6 dB DPA. The input powers for the class-AB and 6 dB DPA are set to 14 dBm and
17 dBm, such that both amplifiers have approximately the same average peak power
(27.5 dBm) and average output power (20 dBm). This is about 8 dB backoff from
the peak power. The simulation time was about 50 hours for the class AB-amplifier
and 90 hours for the 6 dB DPA, on a PC with a Pentium 4 CPU at 2 GHz.
200
Figure 6.32: EVM performance of the class-AB amplifier (a) and DPA (b)
Figure 6.33: Spectrum of the output signal for the class AB amplifier (a) and DPA (b)
201

It could be expected that the DPA suffers of linearity problems due to the compression of the class-C amplifier and the non-precise phase overlapping with the class
AB amplifier. Hence, the class-AB amplifier is expected to outperform the DPA in
terms of linearity. Surprisingly, the simulation shows opposite results. The output
constellation with the corresponding relative constellation RMS error (RCE or EVM),
averaged over subcarriers, OFDMA frames, and packets are reported in Fig. 6.32 for
both the class-AB amplifier and the DPA. The relative constellation error (RCE)
in dB should not exceed 26 dB for the testing conditions. Both amplifiers comply
with this specification, however the DPA has a better RCE value (-34 dB) than the
class AB amplifier (-26 dB). In terms of spectral regrowth, the spectral density of
the output signal shall fall within the spectral mask, according to the specification
5.3.3 ETSI EN 301 021 V1.6.1(2003-07). The simulation results reported in Fig. 6.33,
show that both output spectra comply with the specification, nonetheless the DPA
output signal exhibits reduced spectral regrowth as compared to the class-AB amplifier. This unexpectedly good linearity performance of the DPA was also reported in a
recent paper [182], in which the results were based on measurements. The reason of
this linearity improvement results from the cancellation of the third-order harmonic
generation (coefficient gm3 ) between the carrier and peaking amplifier [166, 167, 182].
Finally the average efficiency of the class-AB and 6 dB DPA will be calculated considering the WiMAX signal statistics and the efficiency responses of the amplifier by
using the following formula:
ave
R
Pout p(Pout ) dPout
R
= 0
P
DC (Pout ) p(Pout ) dPout
0
(6.48)
where p(Pout ) corresponds to the probability distribution function (pdf ) of the output
power.
This equation corresponds to the average drain efficiency and it has been used in
earlier publications [164, 169]. A more representative FoM would be the average
PAE, which can be formulated as
P AEave
R
(Pout Pin ) p(Pout ) dPout
= R0
0
(6.49)
The probability distribution is obtained from simulations (see Fig. 6.34) and using
the same excitation signal as the one for the linearity testing. The values of DC power
and output power are measured values. However simulation values had to be added
in the low power region where measured data were not available (see Fig. 6.29 and
6.30). The average efficiency values are reported in Table 6.4 along with the linearity
figures.
As one can observe from Table 6.4, there is only an improvement of 3% in terms of
202

Table 6.4: Comparison between class AB and 6 dB DPA with similar average output power
Amp.
class AB
DPA
Pin
(dBm)
14
17
Poutave
(dBm)
20
20
Poutpeak
(dBm)
27.7
27
ave
(%)
16.7
20.7
P AEave
(%)
14.7
14.3
RCE
(dB)
-26
-34
Figure 6.34: Probability distribution function of the output power of the class AB (a) and
DPA (b)
nave and no improvement considering P AEave . This is because of the lower gain and
higher losses of the DPA in comparison with the class AB. Another important reason
for the low efficiency is that the peak output power only reaches 27 dBm while its
maximum is about 30 dBm, losing 3 dB of optimal efficiency range (see Fig. 6.34b,
pdf for 20 dBm output power). When the DPA is driven such that the output signal
covers most of its optimal efficiency range (see Fig. 6.34b, pdf for 23 dBm output
power), better efficiency figures are obtained, as indicated in Table 6.5. In this case,
DPA exhibits a more pronounced improvement with an average efficiency and PAE of
31% and 21% respectively. However, its linearity performance in terms of RCE drops
to -26 dB, although it still complies with the WiMAX standard.
Table 6.5: Comparison between class AB and 6 dB DPA under peak power condition
Amp.
class AB
DPA
Pin
(dBm)
14
20
Poutave
(dBm)
20
23
Poutpeak
(dBm)
27.7
30
203
ave
(%)
16.7
31
P AEave
(%)
14.7
21
RCE
(dB)
-26
-26
Figure 6.35: AM-AM (a) and AM-PM (b) characteristics of Doherty and class-AB amplifier
AM-AM and AM-PM response of Doherty amplifier

It has been just described that the superior linearity performance of the two-stage
Doherty amplifier comes from the cancellation of the third-order harmonic generation
(gm3). To verify this characteristic, the intermodulation products of the class-AB
and class-C amplifier have to be measured. However the class-C amplifier was built
in the DPA and it was not possible to measure it separately. Alternatively, the linearity behavior can be characterized by measuring the AM-AM and AM-PM conversion
figures of the amplifier. This is reported in Fig. 6.35 along with the class-AB characteristics, for comparison purposes. These values correspond to the measured values
under the bias condition reported in Fig. 6.11b and 6.29a for class-AB and Doherty
amplifier respectively. The AM-AM characteristic of the Doherty amplifier is superior
to the class-AB amplifier at large input amplitudes. While the former stays approximately linear, the latter suffers of amplitude compression. That is the reason, why
class-AB amplifier has to be operated several dB backoff from the maximum output
power, and with the consequent low power efficiency. Meanwhile, the Doherty amplifier stays roughly linear, combined with high efficiency over this high range. In terms
of AM-PM characteristic, the response for both amplifiers is approximately the same.
However, it has to be noticed that the phase delay of the DPA is negative. This is
because of the effect of the power splitter, offset and compensation transmission lines,
which add more than 270 of phase delay. At the end, the range of phase distortion of
both amplifiers remains approximately the same. Ultimately the most representative
way to verify the linearity performance is by employing actual signals and measuring
EVM and ACPR as was done earlier.
State of the art of 3.5 GHz WiMAX power amplifiers

Most of the 3.5 GHz WiMAX amplifiers, developed for research or commercial purposes, fall in the profC3_23 (= 23 dBm) or Class 4 (= 30 dBm) power class (see
section 6.2.4). The main characteristics of these state-of-the-art WiMAX amplifiers
204

Table 6.6: State of the art of 3.5 GHz WiMAX power amplifiers (I)
Description
Ref.
[185]
[184]
[182]
[183]
this
work
Device
GaAs
pHEM T
Si
LDM OS
GaN
HEM T
GaN
HEM T
GaAs
pHEM T
CW performance
Gain
(dB)
(%)
Amp.
type
Pout
(dBm)
P AE
(%)
class-AB
44.7
10
60
class-AB
44.6
26
36.7
Doherty
51
35
Doherty
47.8
11
Doherty
30
5.5
55
32
are reported in Table 6.6. All the reported designs, except our work, were intended
to establish a milestone in terms of output power and efficiency using GaAs HEMT,
Si LDMOS and GaN HEMT technology. As a matter of fact, these three technologies
are competing to be the dominant one in the market of WiMAX base stations at
3.5 GHz. That is the reason why the output power was at least 30 W for all these
investigations. The output power of these designs is, by far, higher than in our work
and will not be used as a comparison parameter. The design of this PhD thesis is the
third Doherty WiMAX amplifier reported at 3.5 GHz to our best knowledge. Considering CW performance, our design achieves efficiency figures ( = 55%, PAE=32%)
comparable to the other research works presented in Table 6.6. Under WiMAX test
signal (see Table 6.7), all the Doherty investigations exhibit superior efficiency performance compared to the class-AB amplifiers. Furthermore, our investigation exhibits
better average efficiency figures than [182], however less than in [183]. Nevertheless,
the latter does not specify completely the type of test signals and whether it complies
with the standard. Except for this investigation, all the reported designs comply
with the linearity requirement (RCE or EVM) according to the utilized test signal
(see Table 6.7). Finally, these efficiency figures can be further improved by using a
predistortion linearizer, as reported in [183, 184]. Care has to be taken not to mix up
results with and without linearizer. The reported values in Table 6.7 do not include
the effect of these linearizers, since this would make the comparison more complex.
On the other hand, the integration of this linearizer in base-band or RF level is an
aspect that still has to be pondered properly in terms of complexity and cost.
6.4.9
Conclusions
In this chapter, the challenge of providing an amplifier with acceptable linearity and
efficiency at the same time has been undertaken by using a Doherty technique. To
205

Table 6.7: State of the art of 3.5 GHz WiMAX power amplifiers (II)
Description
Amp.
Ref.
type
[185]
class-AB
[184]
class-AB
[182]
Doherty
[183]
Doherty
this
work
Doherty
WiMAX performance
T est
Poutave
ave
signal
(dBm)
(%)
3.5 M Hz
64 QAM
34
16
9.5 dB at 0.01%
7 M Hz
64 QAM 3/4
36
14
9.5 dB at 0.01%
28 M Hz
64 QAM 3/4
43
27.8
8.9 dB at 0.01%
not specif ied
not specif ied
40
45
9.8 dB
10 M Hz
64 QAM 1/2
23
31
10 dB at 0.01%
P AEave
(%)
-
21
this purpose the Angelov non-linear model, developed in chapter five, has been used
from the onset. Classical class-AB, class-C and class-E amplifiers have been designed
using the concept of equivalent capacitance. All these amplifiers were targeted to a
WiMAX application at 3.5 GHz. Class-AB and class-C amplifiers were used as carrier
and peaking amplifiers for the Doherty amplifier. Two Doherty amplifiers were designed aiming to provide 6 dB and 10 dB of efficiency range. Despite these efficiency
ranges were obtained, the PAEs were relatively small due to the power drop in the
power dividers. Higher gain devices or different-size devices could help to improve
the efficiency values. Besides the improvement in efficiency range, Doherty amplifier
exhibits better linearity figures in comparison with a legacy class-AB amplifier. Finally, device modeling is a crucial task to be able to design advanced amplifiers such
as the ones described in this chapter. Class-E and Doherty amplifiers were invented
decades ago, when the applications were at very low frequencies and device behavior
was simpler as well. Those techniques were based on time domain waveforms and
intrinsic load lines. Therefore, to keep using those techniques nowadays, these waveforms and load lines have still to be verified, and the way to do it is by checking the
intrinsic parameters in the device model. Hence, it can be stated that the success of
designing an RF power amplifier is tightly linked to the accuracy and robustness of
the device model.
206
Chapter 7
Conclusions
There is worldwide need and trend for saving energy, and communications systems
have not been exempted from this current requirement, even if saving battery power is
not the same as saving energy delivered by a power plant. Among all the components
of an RF transceiver, the power amplifier takes a big share of the total energy and its
design should be done wisely. Methodologies to design highly efficient amplifiers have
existed since the tubes ages. The application of these methods with last-generation
transistors operating at microwaves frequencies is not straightforward. Furthermore,
due to the stringent time-to-market requirement, methods based on load pull measurements or optimization procedures have proliferated. Normally, solutions obtained
from old methods are used as a starting point for a subsequent optimization of the
design. During this process, the real principle of a particular technique may be completely lost in the overwhelmingly complex mathematical algorithms and computer
processing. For instance, this has been the case at least to some degree for the
high efficiency class-E amplifier. Complex transistor behavior at microwave frequencies does not allow a direct application of class-E closed-form relationships. Efforts
have been oriented to modify these formulas to include more realistic device characteristics. At the end, an optimization is normally performed in order to get higher
efficiency figures.
Efficiency is not the only requirement for on-going and advent applications. Higher
data throughput is a goal as well, and this is achieved by utilizing complex modulation
techniques and orthogonal multiplexing. However, this demands highly linear amplifiers. Hence, classical high efficiency amplifiers can not be used due to their high
non-linearity features. On the other hand, linear amplifiers are highly inefficient.
As a result, investigations have been centered on developing efficiency enhancement
techniques for linear amplifiers or linearity improvement techniques for non-linear
amplifiers.
207
It is in this context that the research work for the before lying PhD has been done. It
is also with this context in mind that the main contributions and conclusions of this
PhD are summarized in the following paragraphs.
- After the introduction general power amplifier techniques and figures of merit have
been exposed in Chapter 2.
- In Chapter 3 dominant and new device technologies for RF power amplifiers have
been investigated. Unlike mainstream electronics, which is driven by one technology
(Si CMOS), RF or microwave electronics has followed its own path pushed by different technology developments. However, the global market, which is characterized by
economics of scale, demands minimization of cost for new developments and products.
As a consequence, major research efforts have been undertaken aiming at extending
the application area of Si technologies well into the microwave frequency range. This
has been done successfully in the last couple of years: Si technologies have reached
frequencies that were only possible by GaAs/InP technology in the past. Nonetheless, this comes at the cost of a reduction in the breakdown voltage. This reduction
becomes an Achilles-heel for this technology in the RF power amplifier arena. RF
power amplifiers demand devices with high voltage, high current, and high frequency
capabilities. These conditions have been fulfilled by legacy GaAs/InP technologies,
although these are more expensive. On the other hand, the brand-new GaN technology arises as an interesting competitor with outstanding breakdown voltages as
well as high frequency capabilities. Nonetheless, its reliability and maturity are still
under discussion and under investigation. As long as this discussion does not lead to
a positive outcome, a widespread utilization of GaN will remain uncertain.
- In Chapter 4, methodologies for high efficiency RF amplifiers have been reviewed
and evaluated, particularly the conventional linear class-E technique has been studied.
It has been found that a more proper class-E formulation for microwave frequencies is
required. Including device non-linear effects has been incorporated in recent research
work. The specific case of a single non-linear capacitance has been analyzed in this
PhD, which has led to a new set of class-E formulas. However, during the derivation of these equations, an important condition has been omitted. Orthogonality of
the (second, third, . . . ) harmonic components of the current and voltage is a condition that guarantees 100% theoretical efficiency in class-E. We have shown that this
condition is only fulfilled in class-E amplifiers with linear capacitance. Nevertheless,
equations for class E with non-linear capacitance are still valuable as far as the phase
difference between voltage and current harmonic components approach 90 [110]. On
the other hand, a method to design class-E amplifiers, that avoids complicated formulation and optimization procedures, has been proposed, implemented and verified.
An equivalent linear capacitance that represents the effect of the non-linear Cgs and
Cgd is estimated based on load line observation [97]. By obtaining this equivalent
value, the transmission-line-based class-E method can be applied without further ado
[94]. However it is important to remark that the accuracy of the capacitance value,
and therefore the success of this method, relies on a proper device modelling.
208
- As a logical continuation, different aspect of building a device model have been studied, and device modeling procedures have been developed and described in Chapter 5.
The modeling process starts with the design of an adequate test fixture. Knowledge
of propagation modes and oscillation conditions are fundamental. Moreover, the use
of full 3D electromagnetic simulation tools is highly recommended as this will provide information about the self-resonance modes of the structure. These self-resonant
modes should appear at frequencies higher than the maximum frequency of interest,
otherwise the test fixture should be modified. After the completion of this task, the
parasitics introduced by this test fixture should be determined so that they can be
removed from any subsequent measurement. A compact de-embedding method based
on a four port network description has been proposed and verified [138, 139]. Furthermore, this method corrects the local-ground effect associated to an electromagnetic
solution with internal ports. The next step is to collect DC and S-parameter measurements which are the minimum information required to construct a non-linear device
model. With this information, non-linear current and non-linear intrinsic capacitance
characteristics are extracted [126]. Angelovs description of these elements has proved
to be robust in harmonic balance simulations, and this is because of its continuityof-derivatives feature. Thermal effects on current and capacitance parameters are
preponderant on RF power devices and must be included. Although measurements
have not been specifically conducted for this purpose, thermal factors have been pondered by analyzing the self-heating effect on the drain current and capacitances. The
optimal case is the one taking into account pulsed DC and S-parameter measurements.
The thermal coefficient may not be sufficient to have a complete device characterization, additional factors as cross-capacitance and dispersion phenomena are very
important as well, and they were used as ultimate resources to tune the final model.
Finally, bringing all the above knowledge together in Chapter 6, a Doherty efficiency
enhancement technique was applied and assessed for the case of 3.5 GHz WiMAX
OFDM signals. It is found that the Doherty efficiency enhancement technique does
not only improve the overall efficiency but also the linearity. Classical Doherty amplifiers demand a peak transistor (twice or three times) larger than the carrier transistor.
Although this requirement could be superseded by using asymmetric power dividers,
this causes a drop in the gain and in the power added efficiency, even for the symmetric
divider. A Doherty amplifier with 6 dB of efficiency range using two identical devices
has been successfully designed and measured. Despite the smaller gain and PAE in
comparison with the class-AB amplifier, the designed Doherty amplifier exhibits superior overall drain efficiency and PAE, as well as linearity figures when tested with
WiMAX OFDM signals. 10 dB of efficiency range can also be reached by using a
carrier and two peak amplifiers, all of them using identical devices. Nonetheless, the
high drop in gain and PAE makes this impractical. High gain pre-stage amplifiers
or larger devices for the peak amplifiers have to be used in order to improve the
performance of this amplifier configuration.
Class-E and Doherty amplifiers are two of the most representative RF power amplifiers
utilized and investigated nowadays. However, their operating principles are not new,
209
they were proposed and described in the 70s and 40s respectively, when the state
of the technology was different. A proper contemporization of this technique requires
that these principles of operation remain irrespective of the technology or device
complexity. In other words, the zero-voltage-switching and zero-voltage-derivativeswitching class-E principle as well as the load pull and impedance inversion of the
Doherty technique must still be observable. Since these characteristics have to be verified at the intrinsic device terminals, they are not measurable; consequently the only
way to control it is by constructing a reliable equivalent circuit model of the device.
Hence, the success of an amplifier design is highly dependent on a well-constructed
model of the involved components. Furthermore, the modeling approaches should not
remain invariant, but they should evolve with the frequency range in which they are
applied. So instead of being based only on electrical elements only, electromagnetic
elements or characteristics should be included as well. This is the nature of the active
devices, passive components and interconnections working at microwaves frequencies
or above. It is by including these that we have been able to successfully conclude our
designs.
Based on the described conclusions, the main contributions of this investigation can
be summarized as follows:
The equivalent capacitance concept has been introduced and successfully applied
to the design of class AB, C and class-E RF amplifiers.
The harmonic orthogonality concept has been applied to class-E amplifiers.
Former researches omitted this analysis.
An alternative technique to perform four-port de-embedding on test fixtures has
been developed successfully.
A complete HEMT large signal model was developed. This is a crucial task to
be able to design advanced RF amplifiers.
The potential benefits of using Doherty amplifier to improve efficiency and linearity at microwave frequencies have been demonstrated.
Final aspects and hereafter investigation

- In this thesis, relevant investigations have been realized on high-efficiency class-E
amplifiers aiming at an integration in an EER-system. The integration task is still
pending and should be mainly focused on finding a proper technology and architecture
for the DC-DC converter, which is the most critical element of this linearization system
and theme of on-going researches.
- It has been shown that a critical element in the efficiency performance of Doherty
amplifiers is the power divider. Hence, a smarter way to distribute the power between
210
the carrier and peak amplifier should be investigated. Its integration within the passband or base-band transmission block should be considered as well.
- Size reduction of the Doherty amplifier can be realized by using lumped-componentsbased matching circuits and impedance inverters. However this approach reaches its
limits very quickly. Circuit equivalent based models of commercial lumped components are normally valid up to 6 GHz. At higher frequencies the size of the lumped
components approaches the signal wavelength and their EM behavior becomes preponderant. Furthermore, a design and implementation based on distributed elements
would be more reliable, controllable and compact at those frequency ranges.
- Most of the research developed in this thesis has been oriented to high efficiency
amplifiers and efficiency enhancement of linear amplifiers, leaving the linearity factor
to the defaults that can be obtained from classical amplifiers. Further investigation
can be conducted to analyze in detail the linearity performance of different Doherty
topologies. For instance, an optimal linearity performance with WiMAX signals has
been observed due to the cancellation of the third harmonic distortion when the carrier
and peak amplifiers present similar size devices. However this performance will differ
when a larger device is used for the peak amplifier (to increase the efficiency range).
It could be expected that for this last case the cancellation effect would be lower due
to the device size difference. Hence, a trade-off between efficiency range and linearity
improvement could be established.
- The amplifier designs developed in this thesis have been optimized considering sinusoidal signals and their performance under actual signals is evaluated afterwards.
An ultimate methodology would be to consider the actual signal statistics instead of
a sinusoidal signal from the very beginning. However, this approach brings up issues
like the integration of classical device models into a system (or symbolic) simulator, as
Ptolemy of ADS (comparable to Simulink and Matlab). This integration would make
the design process very time and computer-resources consuming. Black box modeling
may help to reduce this processing time, however it is not design oriented, i.e., the link
with the physics underneath the amplifier elements is missing. Anyhow, the concept
of using statistical signals is very appealing and potentially fruitful. Nevertheless, for
this type of investigation there is still a long way to go.
Finally I would like to finish my thesis dissertation with a quote I cited when I finished
the first-year doctoral program.
_
I know not what I appear to the world, but to myself I seem to have been only like a boy
playing on the sea-shore, and diverting myself in now and then finding a smoother pebble or
a prettier shell, whilest the great ocean of truth lay all undiscovered before me.
Isaac Newton (1643 - 1727)
211
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Articles in international journals
M. YarlequeMedina, D. Schreurs and B. Nauwelaers, RF class-E power amplifier design based on a load line-equivalent capacitance method, IEEE Microwave and Guided Wave Letters, Vol. 18, No. 3, pp. 206-208, March 2008
M. YarlequeMedina, D. Schreurs and B. Nauwelaers, WiMAX Class AB and
Class E Power Amplifier Design Using Equivalent Capacitance Concept, accepted for publication in International Journal of RF and Microwave ComputerAided Engineering.
Articles in international conference proceedings
M. Yarleque, P. Colantonio, D. Schreurs, F. Giannini, and B. Nauwelaers, "Xband class-E power amplifier design," TARGET Workshop on RF Power Amplifier, Orvieto, Italy, pp. 43-46, 14-15 April 2005.
P. Colantonio, F. Giannini, R. Giofre, M.A. Yarleque, D. Schreurs, and B.
Nauwelaers, "High Frequency Class E Design Methodologies," European Gallium
Arsenide and Other Semiconductors Application Symposium, Paris, France, pp.
329-332, 3-7 October 2005.
M.A. Yarleque Medina, D. Scheurs, and B. Nauwelaers, "Medium-Power RF
FET Intrinsic Parameter Extraction based on Four-port Extrinsic Model," URSI
Benelux Meeting, Eindhoven, The Netherlands, 12 May 2006.
M.A. Yarleque Medina, D. Schreurs, and B. Nauwelaers, "Four-port Deembedding Technique for FET Devices Mounted in Hybrid Test Fixture," 1st European
Microwave Integrated Circuits Conference, Manchester, UK, pp. 464-467, 10-13
September 2006.
M.A. Yarleque Medina, D. Schreurs, and B. Nauwelaers, "Harmonic Orthogonality Condition in RF Class-E Power Amplifiers," 2006 Asia-Pacific Microwave
Conference, Yokohama, Japan, pp. 437-440, 12-15 December 2006.
229
D. Kther, D. Schreurs, M. Yarleque Medina, J.C. Pedro, A. Cidronali, R.
Makri, and A. Mediavilla, "Amplifier Model Verification for Communications,"
Proc. TARGET Days 2007, Frascati, Italy, pp. 25-29, 16-17 December 2007.
P. Colantonio, F. Giannini, M. Imbimbo, M. Yarleque Medina, D. Schreurs, B.
Nauwelaers, J.A. Garcia, and A. Mediavilla, "Design and realisation of Power
Amplifiers for WiMAX applications," Proc. TARGET days 2007, Frascati, Italy,
pp. 87-92, 16-17 December 2007.
D. Schreurs, M. Myslinski, A. Cidronali, M. Yarleque Medina, P. Colantonio,
F. Giannini, R. Giofre, and B. Nauwelaers, "Large-Signal Measurements-Based
Characterization of PA for Modern Wireless Applications," Proc. 11th International Symposium on Microwave and Optical Technology, Frascati, Italy, pp
487-490, 17-21 December 2007.
Article in electronic media
TARGET, Linear Power Amplifier Design & Wireless Systems. EPSCUPC,
2006, ISBN 978-84-611-9755-2.
230
Curriculum vitae
Manuel Augusto Yarlequ Medina received the B.Sc. degree in Electronics Engineering in 1993 and the professional title of Electronics Engineer in 1996 from Pontificia
Universidad Catlica del Per (PUCP). Since 1996, he has been involved in telecommunications projects related to wireless communications and data networking in Per.
He received a diploma in Digital Communications Engineering from Instituto Nacional
de Investigacion y Capacitacion de Telecomunicaciones, Per in 1999. He was lecturer
on Telecommunications Theory and System from 1997 to 2001 at PUCP. In 2001, he
joined the ESAT-Telemic team to pursue a PhD degree in the area of high-efficiency
linear RF power amplifiers.
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KATHOLIEKE UNIVERSITEIT LEUVEN

Proefschrift voorgedragen tot

KATHOLIEKE UNIVERSITEIT LEUVEN

Proefschrift voorgedragen tot

Katholieke Universiteit Leuven - Faculteit Ingenieurswetenschappen

the development of this investigation. Additionally, she managed to proofread all my

Introduction and motivation . . . . . . . . . . . . . . . . . . . . . . . .

Scope of the research work . . . . . . . . . . . . . . . . . . . . . . . . .

2 RF power amplifier basics

Basic RF amplifier characteristics . . . . . . . . . . . . . . . . . . . . .

Drain efficiency and power added efficiency . . . . . . . . . . .

Harmonic distortion and intermodulation distortion . . . . . .

Adjacent channel power ratio . . . . . . . . . . . . . . . . . . .

Error vector magnitude . . . . . . . . . . . . . . . . . . . . . .

Class of amplifiers: from class-A to class-C . . . . . . . . . . . . . . .

Class-A power amplifier . . . . . . . . . . . . . . . . . . . . . .

Reduced-conduction-angle amplifier: class AB, B and C . . . .

Harmonic output termination: tuned load . . . . . . . . . . . .

Class-E power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . .

Capacitance and switching losses . . . . . . . . . . . . . . . . .

Class-E operation analysis . . . . . . . . . . . . . . . . . . . . .

Class-F power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . .

Actual figures of merit and efficiency - linearity challenge . . . . . . .

3 RF devices for power amplifiers

Two-port network and stability condition . . . . . . . . . . . .

Two-port power gain . . . . . . . . . . . . . . . . . . . . . . . .

Maximum frequency of oscillation and cut-off frequency . . . .

Bandgap and breakdown effect . . . . . . . . . . . . . . . . . .

GaAs technology and devices . . . . . . . . . . . . . . . . . . . . . . .

pHEMT, mHEMT and power HEMT . . . . . . . . . . . . . .

Silicon-based technology and devices . . . . . . . . . . . . . . . . . . .

GaN technology and devices . . . . . . . . . . . . . . . . . . . . . . . .

Technologies and applications . . . . . . . . . . . . . . . . . . . . . . .

4 High efficiency RF power amplifier

From lumped components to transmission line class-E power amplifier

Transmission line-based class-E power amplifier . . . . . . . . .

2 GHz SiGe class-E amplifier . . . . . . . . . . . . . . . . . . . . . . .

X-band GaAs class-E power amplifier . . . . . . . . . . . . . . . . . .

2.4 GHz GaN class-E power amplifier . . . . . . . . . . . . . . . . . . .

Class-E with non-linear capacitance . . . . . . . . . . . . . . . . . . .

Harmonic orthogonality analysis of class-E amplifiers . . . . . . . . . . 102

Class-E with linear shunt capacitance . . . . . . . . . . . . . . 105

Class-E with non-linear shunt capacitance . . . . . . . . . . . . 106

Linearity of class-E power amplifier and EER technique . . . . . . . . 110

Class-E amplifier linearity . . . . . . . . . . . . . . . . . . . . . 110

Class-E amplifier linearity in EER configuration . . . . . . . . 112

5 GaAs HEMT device modeling

Basic concepts: measurements, calibration and deembedding

Test structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Test fixture for packaged SiGe BFP620 . . . . . . . . . . . . . 120

Test fixture for bare-die GaAs FPD750

Small signal modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Equivalent circuit of extrinsic network . . . . . . . . . . . . . . 125

Four-port representation of extrinsic network . . . . . . . . . . 133

De-embedding and extraction of device intrinsic parameters . . 139

Large-signal modeling using empirical Angelov FET model

Angelovs drain current expression . . . . . . . . . . . . . . . . 144

Angelovs capacitance expressions