A

+VCCP
U34A

H_ADSTB#1

18
18
18

H_A20M#
H_FERR#
H_IGNNE#

C2
D3
A3

18
18
5
18

H_STPCLK#
H_INTR
H_NMI
H_SMI#

C6
D1
D4
B4

CONTROL

IERR#
INIT#

RESET#
RS0#
RS1#
RS2#
TRDY#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
ADSTB#1

HIT#
HITM#
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDI
TD0
TMS
TRST#
DBR#

H_ADS#
H_BNR#
H_BPRI#

L4
H2
M2

H_DEFER#
H_DRDY#
H_DBSY#

N4

H_BR0#

H_INIT#

18,41

A4
B5

9
9
9
9

H_IERR#

J2

H_LOCK#
H_RS#0
H_RS#1
H_RS#2

H_RS#[2:0]
H_TRDY#

K3
K4
C8
B8
A9
C9
A10
B10
A13
C12
A12
C11
B13
A7

H_HIT#
9
H_HITM# 9
H_BPM0_ITP#
H_BPM1_ITP#
H_BPM2_ITP#
H_BPM3_ITP#
H_BPM4_PRDY#
H_BPM5_PREQ#
H_TCK
H_TDI
H_TDO

A15
STPCLK#
ITP_CLK1 A16
LINT0
ITP_CLK0 B14
LINT1
BCLK1 B15
SMI#
BCLK0
Banias-Processor-Skt_cooperspur

CLK_ITP_CPU#
CLK_ITP_CPU
CLK_CPUHCLK#
CLK_CPUHCLK

R383 +VCCP
150

5
R390

H_TDO
5
H_TMS
5
H_TRST# 5
TP57
H_PROCHOT#

PM_THRMTRIP#

R388
10K

+VCCP

TP2
TP7
TP5
TP3
TP61
TP58
H_TCK

ITP_DBRESET#

H_THERMDA
H_THERMDC

THERMTRIP#

P lace testpoint
o n H_IERR# with
a GND 0.1" away

H_CPURST#

B11
H1
K1
L2
M3

+VCCP

R382
54.9

C17

PROCHOT#
THERMDA
THERMDC

R379
56

9
9

B17
B18
A18

A20M#
FERR#
IGNNE#

H _ T D I pullup (R8001) must

b e p laced within 300ps of
C P U TDI pin (within 2")

56

U34B

H_D#[63:0]

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

4
4
19
6
6
6
6

9
9
9

R387
10K

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

EVMC connections

C O M P 1 , C O M P3 should be routed as Zo=55ohm

t r a c es shorter than 0.5"

+VCCP

R266
Comp0
Comp1
Comp2
Comp3

9
9
9

H_DSTBN#1
H_DSTBP#1
H_DINV#1

1K_1%

R265

TP_GTLREF3
TP_GTLREF2
TP_GTLREF1

TP34
TP6
TP54

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#

H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
K24
L24
J26

D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#

DATA GRP 3

Layout note:
C O M P 0 a n d C OMP2 need to be Zo=27.4ohm traces.
B e s t e s t i m a t e i s 18mil wide trace for outer layers and
1 4 m i l i f o n internal layer. See RDDP of Banias.
T r a c e s s h o u l d b e shorter than 0.5". Refer to latest CS layout

H_DSTBN#0
H_DSTBP#0
H_DINV#0

A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
C23
C22
D25

DATA GRP 2

AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5

BR0#

LOCK#

ADDR GROUP1

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

R2
P3
T2
P1
T1

DEFER#
DRDY#
DBSY#

N2
L1
J3

AC1
G1
E26
AD26

GTLREF3
GTLREF2
GTLREF1
GTLREF0

A1
B2

0 .5" max length

NC0
NC1

2K_1%
R243
54.9_1%

R244
27.4_1%

R300
54.9_1%

R299
27.4_1%

TP4
TP59
TP1
R376

C14
C3
AF7
C16
E1

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#

DATA GRP 0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

ADS#
BNR#
BPRI#

D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#

DATA GRP 1

H_ADSTB#0
H_REQ#[4:0]

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB#0

ITP SIGNALS

9
9

P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
AA3
Y3
AA2
U3

ADDR GROUP0

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

2,3,5,9,10,11,18,19,20,50

+VCCP

THERM

H_A#[31:3]

H CLK

COMP0
COMP1
COMP2
COMP3
DPSLP#
DPWR#
PWRGOOD
SLP#

Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
W25
W24
T24

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
AE24
AE25
AD20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

P25
P26
AB2
AB1
B7
C19
E4
A6

H_DSTBN#2
9
H_DSTBP#2
9
H_DINV#2
9

CHK Banias w/ GL,

DPWR? need pull up?

H_DSTBN#3
9
H_DSTBP#3
9
H_DINV#3
9
+VCCP

Comp0
Comp1
Comp2
Comp3

PM_PSI#

330_*
H_DPSLP#
8,18
H_DPWR#
8
H_PWRGD
18
H_CPUSLP#
18

RSVD1
RSVD2 MISC
C5
TEST1
RSVD3
TEST1 F23 TEST2
RSVD4
TEST2
PSI#
Banias-Processor-Skt_cooperspur

PM_PSI#

330

R66
H_DPSLP#

R67
1K_*
44

R63

R380
1K_*

R389
1K_*

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
1
56
B

DESCRIPTION:
C

Dothan 1 of 2

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

U34D

A2
A5
A8
A11
A14
A17
A20
A23
A26
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11

D13
VSS0
VSS97 D15
VSS1
VSS98 D17
VSS2
VSS99 D19
VSS3
VSS100 D21
VSS4
VSS101 D23
VSS5
VSS102 D26
VSS6
VSS103 E3
VSS7
VSS104 E6
VSS8
VSS105 E8
VSS9
VSS106 E10
VSS10
VSS107 E12
VSS11
VSS108 E14
VSS12
VSS109 E16
VSS13
VSS110 E18
VSS14
VSS111 E20
VSS15
VSS112 E22
VSS16
VSS113 E25
VSS17
VSS114 F1
VSS18
VSS115 F4
VSS19
VSS116 F5
VSS20
VSS117 F7
VSS21
VSS118 F9
VSS22
VSS119 F11
VSS23
VSS120 F13
VSS24
VSS121 F15
VSS25
VSS122 F17
VSS26
VSS123 F19
VSS27
VSS124 F21
VSS28
VSS125 F24
VSS29
VSS126 G2
VSS30
VSS127 G6
VSS31
VSS128 G22
VSS32
VSS129 G23
VSS33
VSS130 G26
VSS34
VSS131 H3
VSS35
VSS132 H5
VSS36
VSS133 H21
VSS37
VSS134 H25
VSS38
VSS135 J1
VSS39
VSS136 J4
VSS40
VSS137 J6
VSS41
VSS138 J22
VSS42
VSS139 J24
VSS43
VSS140 K2
VSS44
VSS141 K5
VSS45
VSS142 K21
VSS46
VSS143 K23
VSS47
VSS144 K26
VSS48
VSS145 L3
VSS49
VSS146 L6
VSS50
VSS147 L22
VSS51
VSS148 L25
VSS52
VSS149 M1
VSS53
VSS150 M4
VSS54
VSS151 M5
VSS55
VSS152 M21
VSS56
VSS153 M24
VSS57
VSS154 N3
VSS58
VSS155 N6
VSS59
VSS156 N22
VSS60
VSS157 N23
VSS61
VSS158 N26
VSS62
VSS159 P2
VSS63
VSS160 P5
VSS64
VSS161 P21
VSS65
VSS162 P24
VSS66
VSS163 R1
VSS67
VSS164 R4
VSS68
VSS165 R6
VSS69
VSS166 R22
VSS70
VSS167 R25
VSS71
VSS168 T3
VSS72
VSS169 T5
VSS73
VSS170 T21
VSS74
VSS171 T23
VSS75
VSS172 T26
VSS76
VSS173 U2
VSS77
VSS174 U6
VSS78
VSS175 U22
VSS79
VSS176 U24
VSS80
VSS177 V1
VSS81
VSS178 V4
VSS82
VSS179 V5
VSS83
VSS180 V21
VSS84
VSS181 V25
VSS85
VSS182 W3
VSS86
VSS183 W6
VSS87
VSS184 W22
VSS88
VSS185 W23
VSS89
VSS186 W26
VSS90
VSS187 Y2
VSS91
VSS188 Y5
VSS92
VSS189 Y21
VSS93
VSS190 Y24
VSS94
VSS191
VSS95
VSS96
Banias-Processor-Skt_cooperspur

+VCORE

+VCORE

U34C
AA11
AA13
AA15
AA17
AA19
AA21
AA5
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
D6
D8
E17
E19
E21
E5
E7
E9
F18
F20
F22
F6
F8
G21

G5
VCC0
VCC59 H22
VCC1
VCC60 H6
VCC2
VCC61 J21
VCC3
VCC62 J5
VCC4
VCC63 K22
VCC5
VCC64 U5
VCC6
VCC65 V22
VCC7
VCC66 V6
VCC8
VCC67 W21
VCC9
VCC68 W5
VCC10
VCC69 Y22
VCC11
VCC70 Y6
VCC12
VCC71
VCC13
F26
VCC14
VCCA0 B1
VCC15
VCCA1 N1
VCC16
VCCA2 AC26
VCC17
VCCA3
VCC18
D10
VCC19
VCCP0 D12
VCC20
VCCP1 D14
VCC21
VCCP2 D16
VCC22
VCCP3 E11
VCC23
VCCP4 E13
VCC24
VCCP5 E15
VCC25
VCCP6 F10
VCC26
VCCP7 F12
VCC27
VCCP8 F14
VCC28
VCCP9 F16
VCC29
VCCP10 K6
VCC30
VCCP11 L21
VCC31
VCCP12 L5
VCC32
VCCP13 M22
VCC33
VCCP14 M6
VCC34
VCCP15 N21
VCC35
VCCP16 N5
VCC36
VCCP17 P22
VCC37
VCCP18 P6
VCC38
VCCP19 R21
VCC39
VCCP20 R5
VCC40
VCCP21 T22
VCC41
VCCP22 T6
VCC42
VCCP23 U21
VCC43
VCCP24
VCC44
P23
VCC45
VCCQ0 W4
VCC46
VCCQ1
VCC47
E2
VCC48
VID0 F2
VCC49
VID1 F3
VCC50
VID2 G3
VCC51
VID3 G4
VCC52
VID4 H4
VCC53
VID5
VCC54
VCC55
AE7
VCC56
VCCSENSE
VCC57
AF6
VCC58
VSSSENSE
Banias-Processor-Skt_cooperspur

+VCORE

3,39,44
1

+V1.8S_PROC
+V1.8S_PROC_VCCA1
+V1.8S_PROC_VCCA2
+V1.8S_PROC_VCCA3

+VCCP

+VCCP

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5

RN18
RN19
RN20

1
3
1
3
1
3

TP_VSSSENSE

VR_VID0
VR_VID1
VR_VID2
VR_VID3
VR_VID4
VR_VID5

44
44
44
44
44
44

R246
54.9_1%_*

54.9_1%_*

F O R B A N I A S BO , NO STUFF VCCA1, VCCA2, VCCA3

+V1.8S

+V1.8S_PROC_VCCA1

51

R401

Banias VID values

VID0 VID1 VID2 VID3 VID4 VID5
0
1
1
0
1
0
0
1
1
0
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
1
0
1
1
0
0
1
1
1
1

0
C401
C395

1.356V
1.100V
1.004V
0.908V
0.844V
0.748V

0805

10U_0805
0.01UF
+V1.8S
R370
+V1.8S_PROC

+V1.8S_PROC_VCCA2
R31

C391

C62

0805

C392
+V1.5S

C75

0805

10U_0805
R371

10U_0805

0.1UF

0.01UF

0_*

+V1.8S_PROC_VCCA3
R283

LAYOUT NOTE: Provide a test point with no

stub to connect differential probe between
VCCSENSE and VSSSENSE at the location
where the two 54.9ohm resistors terminate
the 55ohm tramission lines.

0
C314
C313

8,10,11,16,18,19,20,21,51

0805

10U_0805
0.01UF

REVISION

M2Ne

2 0_2R4P
4
2 0_2R4P
4
2 0_2R4P
4

TP_VCCSENSE

R245

+V1.5S

ASUS PROJECT:

1,3,5,9,10,11,18,19,20,50

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
2
56
B

DESCRIPTION:
C

Dothan 2 of 2

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+VCORE
+VCCP

+VCCP

7343

7343

7343

1,2,5,9,10,11,18,19,20,50

+
+

C94
1uF/10V
C11
470U/4V_7343_*

C293
330U/4V_7343_*

C107
1uF/10V

C95
1uF/10V

C108
1uF/10V

C96
1uF/10V

C109
1uF/10V

C53
1uF/10V

C86
1uF/10V

C87
330U/4V_7343

C49
470U/4V_7343

+VCCP

+V2.5

+V1.35S

+V2.5

C ONNECT GND AND GND_SIGNAL

C497
0.1U

+VCORE

C291
0805

C451
0.1U

C531
0.1U

C529
0.1U

C290
0805

10U_0805

10U_0805

CROSS_POWER_PLANE_BOTH_SIDE
G10
C646

C647

0805

C648

0805

C649

0805

C650

0805

0805

C357

C367

0805

0805

C341

0805

10U_0805

10U_0805

10U_0805

10U_0805

10U_0805

10U_0805

10U_0805

10U_0805

C358

C368

C359

C369

C337

C292

C338

C342

HOLE-D

G3

0805

0805

0805

0805

0805

0805

0805

10U_0805

10U_0805

10U_0805

10U_0805

10U_0805

10U_0805

C286

C56

C47

C325

C285

C283

C42

C90

0805

0805

0805

10U_0805

10U_0805

10U_0805

10U_0805

C330

C331

C82

C41

0805

10U_0805

G6

G5

PTH

PTH

G2

10U_0805

0805

0805

10U_0805

0805

10U_0805

0805

10U_0805

0805

10U_0805

C339

C343

0805

10U_0805

0805

10U_0805

G9

HOLE-A

HOLE-B

G11

HOLE-B

G12

HOLE-B

G17

HOLE-B

G14

HOLE-B

10U_0805

G16
C324

HOLE-A

0805

10U_0805

0805

G8

10U_0805

0805

HOLE-A

0805

10U_0805

0805

G4

HOLE-A

C323
0805

10U_0805

HOLE-B

G15

HOLE-B

G13

HOLE-B

C329

0805

10U_0805

10U_0805

G1

HOLE-B

G7

HOLE-B

G18

PTH

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
3
56
B

DESCRIPTION:
C

CPU-CAP & HOLE

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+3VS
Route H_THERMDA,
H_THERMDC on same
l ayer, 10 mil width, 5
mil between on a 12
mil spacing

C651
R655
10K_*

R656
10K

FAN_PWM
FAN_SPD

R657

0_402_*

R64

22 OS#_OC

PWMOUT

OS#_OC_C

TACH/AIN

0_402

THERM#

0.1U

U10

VCC

R654
10K_*

SCL

A DM1030

SDA
INT#
D+

FANFAULT#

SMBCK_3S

6,7,14,33

15

SMBDA_3S

6,7,14,33

14

PM_THRM#

19

10

H_THERMDA

H_THERMDC

NC
NC
NC
NC
ADD
GND

D-

16

3
4
11
12
13
5

ADM1030_*

C130
2

2200P
+3VS
SM Bus Address fix at:
1001 100x (98, 99),
Resolution : +/- 1
degree

+5VS

DXP

ALERT#

DXN

OS#_OC_C

H_THERMDA

H_THERMDC

10UF/6.3V_1206

OVERT

SMBDATA

10UF/6.3V_1206

C734

10UF/6.3V_1206

C735

C736
2

PM_THRM#

SMBCLK

SMBDA_3S

GND

SMBCK_3S

VCC

U8

MAX6657
3

R425

100K
(0603)
L68

+5VS

R135

+5VS_FAN

(0402)
47K_402
U42
3

47K_402

6
Q62
R434

1K_402

1
2
5 3
CN-3_FAN

10K_402

R663

0
(0603)

FAN_SPD

37,39

GND_FAN

-A

Q63
5

2N7002
39 FAN_DA1

C420

0603

0.1U

OUTA

CN26

80/2A

+B
OUTB

-B

R658

0_402

V-

V+

1K

1
NDS351NS

(0603)

+5VS

C427
1U

8
0402

(0402)

R443

LMV393

0603

(0402)

R136

+A

10K_402

R442

47K_402

R132

(0402)

R133

(0402)

(0402)

FAN

0805

C426
0.1U_402

+5VS

R659

D22

0_402_*

22 OS#_OC

3
RB717F

D35

(0402)

FAN_PWM

RB717F

0_*

R660

0_402_*

R759

R142

(0402)

19 PM_THRM#

+3VS
Q32

39 WATCHDOG

2N7002

(0402)

1
R764
10K_402

48 OTP#_P

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
4
56
B

DESCRIPTION:
C

FAN & THERMAL SENSOR

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+5V

PCMCIA DEBUG
PORT

+VCCP

U22
VCC

1,2,3,9,10,11,18,19,20,50

+VCCP

H_TDO

R384

54.9/1%

H_TMS

R381

39.2/1%

H_TRST#

R385

680

H_TCK

R386

27.4/1%

6
CLK_DEBUG
19,41 LFRAME#
19,37,39,41 LAD0
19,37,39,41 LAD1
19,37,39,41 LAD2
19,37,39,41 LAD3
41 D IS_SYSBIOS#_FWH

CBDEBUGEN#

27,43 CBDEBUGEN#

NMI

NMI#/SMI#

3
4
7
8
11
14
17
18
21
22
1
13

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
BEA#
BEB#
3384

B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
GND

24

+5V

2
5
6
9
10
15
16
19
20
23

CLKRUN#/IOIS16#
26,28
C A U D I O/SPKR_IN#/BVD2
CPERR#/A14
26,28
RFU/D2
26,28
RFU/D14
26,28
RFU/A18
26,28
CSERR#/WAIT#
26,28
CBLOCK#/A19
26,28

23,27,29,34,35,39,43,47,51

26,28

12
2

R181
0_402_*
(0402)

+5VS
+5VS

F W H test connector
f o r first version

4 , 1 1 , 1 6 , 2 0,22,23,24,25,29,31,32,33,35,37,38,39,42,43,48,51

R85
10K_*

H_NMI

+3VS
+3VS
C104
0.1uF

41 CLK_DEBUGPCI

2
4
6
8
10
12

1
3
5
7
9
11

2
1
4
3
6
5
8
7
10
9
12
11
CN-12(LPC_DEBUG_*)

+3VS
R84

NMI
DIS_SYSBIOS#

4 , 6 , 7 , 8 , 1 0 , 1 4 , 1 7,20,21,22,23,25,26,31,32,33,35,36,37,38,39,40,41,43,51

NMI

R108
0

1
Q27
2N7002_*

R107
10K_*

LAD0
LAD1
LAD2
LAD3
LFRAME#

10K_*

C105
0.1uF_*
3

CN15

NMI_ICH

18

D IS_SYSBIOS#_FWH

Q26
2N7002_*

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
5
56
B

DESCRIPTION:
C

DEBUG PORT

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+3VS

+3VS
L26

80/2A_0805

+3VS_CLK

CT2
0402

C158

CT1

0805

0402
0.01U_402

C142

C146

0402

0.01U_402

0.01U_402

C153

0402

0805

10U_0805

10U_0805

0402

0.01U_402

C388 0402

C143 0402

C154 0402

C148

0.01U_402

0.01U_402

0.01U_402

0.01U_402

X2
1

U39

R347

33

CLK_SIO14

37

R357

33

CLK_ICH14

19

0_402

C127
14.318MHZ_PAD177A

C138

15p

15p

X1_CKGEN

X2_CKGEN

3
4

C131

18

5P_*

CLK_ICHPCI

R360
R367

CLK_DEBUG

33/1%

FS3

33/1%

FS4

TP56

7
8

+3VS_CLK
C141

41

5P_*

R368

10K

CLK_FWHPCI

R372

33/1%

10

29

CLK_LANPCI

R377

33/1%

11

C145

5P_*

26

CLK_CBPCI

R378

33/1%

12

C150

5P_*

39

R395

33/1%

13

C144

5P_*

CLK_KBCPCI

14
15
C149
C152

31

5P_*

37

5P_*

CLK_MINIPCI
CLK_SIOPCI

R394

33/1%

16

R398

33/1%

17

VTT_PWRGD#
7,19,43

18

R112

SUSA#_3
L64

+3VS

L_0603

0_402

19

(0402)

+3VS_CLKA

20
21

19

R114

PCI_STP#_3

0_402

22

(0402)

23
24

C403

5P_*

18 CLK_ICHHUB

C408

5P_*

CLK_MCH66

R405

33/1% CLK_R_ICHHUB

25

R408

33/1%

26

CLK_R_MCH66

27
4,7,14,33

R111

SMBCK_3S

CT9

C394
0.01U

FS0

R74

1K_*

FS1

R69

1K_*

FS2

R113

R100

28

VDDREF

REF0

X1

FS1

X2

FS0

GND

CPU_STOP#

FS3/PCICLK_F0

CPUCLK0/FS6

FS4/PCICLK_F1

CPUCLK0#/FS5

ASEL/PCICLK_F2

VDDCPU

VDDPCI

CPUCLK1

GND

CPUCLK1#

MULTSEL0/PCICLK0

GND

MODE/PCICLK1

VDDCPU

PCICLK2

CPUCLK2

PCICLK3

CPUCLK2#

VDDPCI

IREF

GND

GND

PCICLK4

FS2

PCICLK5

VID5

VTT_PWRGD#

VID4

PD#

VID3

VDDA

VID2

GND

VID1

PCI_STOP#

VID0

VDD3V66

VDD48

GND

GND

3V66_0

48MHZ_0

3V66_1

48MHZ_1

3V66_2

SDATA

SCLK

3V66_3/48MHZ_2

56
55

FS1

R199

54

FS0

R201

(0402)

0_402

(0402)

53
52

CLK_R_ITP_CPU

51

CLK_R_ITP_CPU#

R553

CG_FS1

19

CG_FS0
0_402

19

(0402)

R358

CPU_STP#_3
33/1%

R366

C386

R83

19

33/1% R356

49.9/1%

R361

49.9/1%

50
49

CLK_R_CPUHCLK

R374

33/1%

48

CLK_R_CPUHCLK#

R392

33/1% R369

49.9/1%

R391

49.9/1%

47

10P_*
C387

R89

0_402_*
(0402)
CLK_ITP_CPU
CLK_ITP_CPU#
0_402_*
(0402)
CLK_CPUHCLK

10K_*

19

CG_FS5

19

CLK_CPUHCLK#

45

CLK_R_GMCHHCLK

R397

33/1%

44

CLK_R_GMCHHCLK#

R400

33/1% R396

49.9/1%

CLK_GMCHHCLK

R399

49.9/1%

43
R109

CLK_GMCHHCLK#

475/1%

42
FS2

41

R117

0_402

near CLK Gen.

(0402)

40

39

CG_FS2

19

38
37
36
35
34
33
32

R402

33

CLK_ICH48

19

31

R406

33

CLK_DREF

30

R110

29

R412

22

0_402

C399

SMBDA_3S 4,7,14,33
SSC_CLK_IN
7

(0402)

5P_*
C402

C406

5P_*

5P_*

FS3 Internal Pull-up

FS4,5,6, ASEL Internal
Pull- Down

56PIN TSSOP

+3VS

1K

CG_FS6
1

46

10U_0805

+3VS

10P_*

0805

FS3
FS4

0_402
(0402)

ICS950815

FS4

FS3

FS2

FS1

FS0

0
1

0
0
1

1
1
0

0
0

0
0

100
200

66
66

33
33

133

66

33

66Buf[2:0]

+3VS

PCI_F
R345
10K

R72
1K

VTT_PWRGD#
3

CPU(MHZ)

R649
1K

R344
1K

R75
1K

R70
1K

R115
1K_*

8,19,22,44

VRM_PWRGD

R71

R77

20K

Q58
2N3904

R78

44 CLK_EN#

ASUS PROJECT: M2Ne

A

REVISION

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
6
56
B

DESCRIPTION:
C

CLOCK GEN.

0_*

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+3VS

C384
0.1U_*

C374
1U_*

U11

T R A CE_LENGH->1"~4"
SSC_CLK_IN

6 SSC_CLK_IN

1
2

R61

0_402
3

(0402)
8

R60

DREFSSCLK

33_*

DREFSSCLK_D

CLKIN

PD#

VDD

SCLK

GND

SDATA

CLKOUT

48MHZ

R106

R105

6
5

R104
R101

0_402_*
(0402)
(0402)
(0402)

SUSA#_3

0_402_*
R510
0_402_*
R511
10K_*

0_402_*
(0402)

0_402_*
(0402)
+3VS

SMBCK_3S
LCLKCTLA
SMBDA_3S
LCLKCTLB

6,19,43
4,6,14,33
8
4,6,14,33
8
3

T R ACE_LENGH->1"~7"
ICS91718_*
R59
10K_*

The distance between CS91718 and Clock

Gen: 1000 mil<L< 4000 mil

ASUS PROJECT: M2Ne

A

REVISION

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
7
56
B

DESCRIPTION:
C

CLOCK GEN.

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

SMA_B1
SMA_B2
SMA_B4
SMA_B5
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3
SM_BA0
SM_BA1
SM_RAS#
SM_CAS#
SM_WE#
SM_CMDCLK0
SM_CMDCLK#0
SM_CMDCLK1
SM_CMDCLK#1
SM_CMDCLK2
SM_CMDCLK#2
SM_CMDCLK3
SM_CMDCLK#3
SM_CMDCLK4
SM_CMDCLK#4
SM_CMDCLK5
SM_CMDCLK#5
SM_DM0
SM_DM1
SM_DM2
SM_DM3
SM_DM4
SM_DM5
SM_DM6
SM_DM7
SM_DM8
SM_RCVENOUT#
SM_RCVENIN#
SMRCOMP

11,12,13,14

AJ24

SM_VREF_DDR

C463
0.1U

SM_VREF

SMVSWINGL
SMVSWINGH

SM_DQS0
SM_DQS1
SM_DQS2
SM_DQS3
SM_DQS4
SM_DQS5
SM_DQS6
SM_DQS7

AC18
AD14
AD13
AD17
AD11
AC13
AD8
AD7
AC6
AC5
AC19
AD5
AB5

SM_MAA0
SM_MAA1
SM_MAA2
SM_MAA3
SM_MAA4
SM_MAA5
SM_MAA6
SM_MAA7
SM_MAA8
SM_MAA9
SM_MAA10
SM_MAA11
SM_MAA12

SM_DQS[0:8]

AD16
AC12
AF11
AD10

SM_MAB1
SM_MAB2
SM_MAB4
SM_MAB5

SM_MAB1
SM_MAB2
SM_MAB4
SM_MAB5

12,13,15
12,13,15
12,13,15
12,13,15

AC7
AB7
AC9
AC10

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

14,15
14,15
12,15
13,15

AD23
AD26
AC22
AC25

SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3

SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3

14,15
14,15
12,15
13,15

AD22
AD20

SM_BS0
SM_BS1

SM_BS0
SM_BS1

12,13,15
12,13,15

AC21
AC24
AD25

SM_RAS#
SM_CAS#
SM_WE#

AB2
AA2
AC26
AB25
AC3
AD4
AC2
AD2
AB23
AB24
AA3
AB4

R478
R477
R429
R426
R476
R475
R474
R473
R432
R431

AE5
AE6
AE9
AH12
AD19
AD21
AD24
AH28
AH15

SM_DM0
SM_DM1
SM_DM2
SM_DM3
SM_DM4
SM_DM5
SM_DM6
SM_DM7

MCH_SMRCOMP

AJ22
AJ19

MCH_SMVSWINGL
MCH_SMVSWINGH

SM_DQS[0:8]
SM_MAA[0:12]

SM_DM[0:8]

SM_DM[0:8]

SM_DQ[0:63]

SM_DQ[0:63]

15
12,13,14,15
15

U43C
15

R3
R5
R6
R4
P6
P5
N5
P2
N2
N3
M1
M5

R454

100K

P3
P4
T6
T5
L2
M2

R450
R453

100K
100K

G2
M3

+V1.5S

K5
K1
K3
K2
J6
J5
H2
H1
H3
H4
H6
G3

+V1.5S

14
14
14
14
14
14
12,13
12,13
12,13
12,13

RP2
5
1
2
3
4

R151

100K

6
7
8
9
2.2K-10P8R

+V1.5S

E5
F5
E3
E2
G5
F4
G6
F6
L7
D5

R148
1K
R447
1K_1%

ADDDETECT
19

DPMS_CLK

F1

NEAR_NB

R146

19,21 AGP_BUSY#
R452
1K_1%

C455
0.1U

R451
40.2_1%
CLK_MCH66
TP73

MONTARA_GMCH_B
C202
5P_*
+V2.5

+V2.5

R471
60.4_1%

+V1.5S
R444
R440
R441

+V2.5

R458
604_1%

MCH_SMRCOMP

J3
J2
K6
L5
L3
H5
K7
N6
N7
M6
P7
T7

10

+V1.5S

TP10
TP9

AB1

3,10,11,12,13,14,49,50
2,10,11,16,18,19,20,21,51

SM_MAA[0:12]

SM_RAS# 12,13,15
SM_CAS# 12,13,15
SM_WE#
12,13,15
0
SM_CLK_DDR0
CLK_DCLK0
0
SM_CLK_DDR#0
CLK_DCLK0#
0
SM_CLK_DDR1
CLK_DCLK1
0
SM_CLK_DDR#1
CLK_DCLK1#
SM_CLK_DDR2
0
CLK_DCLK2
0
SM_CLK_DDR2#
CLK_DCLK2#
0
SM_CLK_DDR3
CLK_DCLK3
0
SM_CLK_DDR#3
CLK_DCLK3#
0
SM_CLK_DDR4
CLK_DCLK4
0
SM_CLK_DDR#4
CLK_DCLK4#
SM_CLK_DDR5
TP74
SM_CLK_DDR#5
TP77

AC15
AC16

+V2.5
+V1.5S

MCH_SMVSWINGL

R462
150_1%
MCH_SMVSWINGH

1K_*
1K_*
1K_*

TP65

+3VS

F7
D1
Y3
AA5
F2
F3
B2
B3
C2
C3
C4
D2
D3
D7
L4

DVOBD0
DVOBD1
DVOBD2
DVOBD3
DVOBD4
DVOBD5
DVOBD6
DVOBD7
DVOBD8
DVOBD9
DVOBD10
DVOBD11

DAC

SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12

+V2.5
+V1.5S

AG2
AH5
AH8
AE12
AH17
AE21
AH24
AH27
AD15

REFSET

DVOBCLK
DVOBCLK#
DVOBHSYNC
DVOBVSYNC
DVOBBLANK#
DVOBFLDSTL
DVOBCINTRB
DVOBCCLKINT
DVOCD0
DVOCD1
DVOCD2
DVOCD3
DVOCD4
DVOCD5
DVOCD6
DVOCD7
DVOCD8
DVOCD9
DVOCD10
DVOCD11

BLUE
BLUE#
GREEN
GREEN#
RED
RED#
HSYNC
VSYNC

DDCACLK
DDCADATA

LVDS

SM_SDQS0
SM_SDQS1
SM_SDQS2
SM_SDQS3
SM_SDQS4
SM_SDQS5
SM_SDQS6
SM_SDQS7
SM_SDQS8

PANELBKLTCTL
PANELBKLTEN
PANELVDDEN
LVREFH
LVREFL

MI2CCLK
MI2CDATA
MDVICLK
MDVIDATA
MDDCCLK
MDDCDATA
ADDID0
ADDID1
ADDID2
ADDID3
ADDID4
ADDID5
ADDID6
ADDID7
ADDDETECT
DPMS
GVREF

IYAM0
IYAM1
IYAM2
IYAM3
IYAP0
IYAP1
IYAP2
IYAP3
IYBM0
IYBM1
IYBM2
IYBM3
IYBP0
IYBP1
IYBP2
IYBP3
ICLKAM
ICLKAP
ICLKBM
ICLKBP
DDCPCLK
DDCPDATA

DVOCCLK
DVOCCLK#
DVOCHSYNC
DVOCVSYNC
DVOCBLANK#
DVOCFLDSTL

LVBG
LIBG

CLKS

SM_SDQ0
SM_SDQ1
SM_SDQ2
SM_SDQ3
SM_SDQ4
SM_SDQ5
SM_SDQ6
SM_SDQ7
SM_SDQ8
SM_SDQ9
SM_SDQ10
SM_SDQ11
SM_SDQ12
SM_SDQ13
SM_SDQ14
SM_SDQ15
SM_SDQ16
SM_SDQ17
SM_SDQ18
SM_SDQ19
SM_SDQ20
SM_SDQ21
SM_SDQ22
SM_SDQ23
SM_SDQ24
SM_SDQ25
SM_SDQ26
SM_SDQ27
SM_SDQ28
SM_SDQ29
SM_SDQ30
SM_SDQ31
SM_SDQ32
SM_SDQ33
SM_SDQ34
SM_SDQ35
SM_SDQ36
SM_SDQ37
SM_SDQ38
SM_SDQ39
SM_SDQ40
SM_SDQ41
SM_SDQ42
SM_SDQ43
SM_SDQ44
SM_SDQ45
SM_SDQ46
SM_SDQ47
SM_SDQ48
SM_SDQ49
SM_SDQ50
SM_SDQ51
SM_SDQ52
SM_SDQ53
SM_SDQ54
SM_SDQ55
SM_SDQ56
SM_SDQ57
SM_SDQ58
SM_SDQ59
SM_SDQ60
SM_SDQ61
SM_SDQ62
SM_SDQ63
SM_SDQ64
SM_SDQ65
SM_SDQ66
SM_SDQ67
SM_SDQ68
SM_SDQ69
SM_SDQ70
SM_SDQ71

DDR SYSTEM MEMORY

AF2
AE3
AF4
AH2
AD3
AE2
AG4
AH3
AD6
AG5
AG7
AE8
AF5
AH4
AF7
AH6
AF8
AG8
AH9
AG10
AH7
AD9
AF10
AE11
AH10
AH11
AG13
AF14
AG11
AD12
AF13
AH13
AH16
AG17
AF19
AE20
AD18
AE18
AH18
AG19
AH20
AG20
AF22
AH22
AF20
AH19
AH21
AG22
AE23
AH23
AE24
AH25
AG23
AF23
AF25
AG25
AH26
AE26
AG28
AF28
AG26
AF26
AE27
AD27
AG14
AE14
AE17
AG16
AH14
AE15
AF16
AF17

DREFCLK
DREFSSCLK
LCLKCTLA
LCLKCTLB

E8

16

16

16

HSYNC
VSYNC

16
16

DAC_REFSET
R147

137/1%
DDC2BC
16
DDC2BD
16

B6
G9
G14
E15
C15
C13
F14
E14
C14
B13
H12
E12
C12
G11
G12
E11
C11
G10
D14
E13
E10
F10

R420

0_*

R418

0_*

R144

0_*

R141

0_*

B4
C5

TP67
TP66

G8
F8
A5

TP72

L1_TX0L1_TX1L1_TX2-

17
17
17

L1_TX0+
L1_TX1+
L1_TX2+

17
17
17

L1_TXACL1_TXAC+

17
17

LCD_ENBACK
LCD_ENVDD

36
17

D12
F12

B12
A10
R428
B7
B17
H9
C6

1.5K_1%

CLK_DREF
6
DREFSSCLK
7
LCLKCTLA 7
LCLKCTLB 7

LCLKCTLB

+3VS

DPWR#
DPSLP#
RSTIN#
PWROK

AGPBUSY#
EXTTS0
MCHDETECTVSS

GRCOMP
66IN
RVSD0
RVSD1
RVSD2
RVSD3
RVSD4
RVSD5
RVSD6
RVSD7
RVSD8
RVSD9
RVSD10
RVSD11

C9
D9
C8
D8
A7
A8
H10
J9

TP64

MISC

U43B
SM_DQ0
SM_DQ1
SM_DQ2
SM_DQ3
SM_DQ4
SM_DQ5
SM_DQ6
SM_DQ7
SM_DQ8
SM_DQ9
SM_DQ10
SM_DQ11
SM_DQ12
SM_DQ13
SM_DQ14
SM_DQ15
SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19
SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23
SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27
SM_DQ28
SM_DQ29
SM_DQ30
SM_DQ31
SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35
SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39
SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43
SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47
SM_DQ48
SM_DQ49
SM_DQ50
SM_DQ51
SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55
SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59
SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63

NC

DVO

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11

AA22
Y23
AD28

H_DPWR#
1
H_DPSLP#
1,18
PCIRST#_ICH
18

J11

VRM_PWRGD

R149
6,19,22,44 10K_1%

D6
AJ1
R479
B1
AH1
A2
AJ2
A28
AJ28
A29
B29
AH29
AJ29
AA9
AJ4

TP69
TP79
TP8
TP78
TP62
TP70
TP60
TP63
TP68
TP71
TP75
TP76

MONTARA_GMCH_C

C484
0.1U
R433
R470
60.4_1%

C464
0.1U

R457
150_1%

C465
0.1U

1K_* LCLKCTLB

R461
604_1%
RSVD5,6,7, LCLKCTLB
RESERVE FOR STRAPPING

F or M-GM + Banias mount RA,

For M-GML + P4 no RA

NEAR_NB
NEAR_NB

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
8
56
B

NEAR_NB

DESCRIPTION:
C

SCHEMATIC FILE NAME : <Doc>

Montara-GME (1 of 4) LIBRARY DATE :

D

DESIGN ENGINEER :
E

+VCCP

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

R416
301/1%

R413

150/1%

MCH_HYSWING

R415

150/1%

MCH_HXSWING
C413
0.1U

C409
0.1U

NEAR_NB
M C H _HYSWING, MCH_HXSWING, MCH_HYRCOMP, MCH_HXRCOMP
TRACE: SPACE=10:20
2

1
1
1
1
1
1
1

+VCCP

R138

49.9/1%

R421

49.9/1%

MCH_HCCVREF

R150

49.9/1%

MCH_HAVREF

R139
100/1%

NEAR_NB

R143
100/1%

R424
100/1%

1
1
1
1
1
1
1
1
1
1
1
1

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

J28
C27
E22
D18
K27
D26
E21
E18
J25
E25
B25
G19

H_CPURST#

F15

NEAR_NB

HUB0
HUB1
HUB2
HUB3
HUB4
HUB5
HUB6
HUB7
HUB8
HUB9
HUB10
HUB_PSTRB
HUB_PSTRB#
HUB_HLZCOMP
MCH_PSWING
MCH_LVREF

MCH_HCCVREF
MCH_HAVREF
C419
0.1U

C417
1U

C168
1U

18

C179
0.1U

HUB[0:10]

+V1.35S

NEAR_NB

18 HUB_PSTRB
18 HUB_PSTRB#
+V1.35S

+V1.35S

R455
68.1/1%

R465

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB0#
H_ADSTB1#

37.4/1%
C468
0.1U

R466
287/1%

U7
U4
U3
V3
W2
W6
V6
W7
T3
V5
V4
W3
V2
T2
U2
W1

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HOST

HCLK#
HCLK
HYRCOMP
HYSWING
HXRCOMP
HXSWING
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
DINV#0
DINV#1
DINV#2
DINV#3
H_CPURST#

K21
J21
J17
Y28
Y22

C163
0.1U

H_D#[0:63]

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

AD29
AE29
H28
K28
B20
B18

MCH_HYRCOMP
MCH_HYSWING
MCH_HXRCOMP
MCH_HXSWING

MCH_HDVREF
C162
1U

P23
T25
T28
R27
U23
U24
R24
U28
V28
U27
T27
V27
U25
V26
Y24
V25
V23
W25
Y25
AA27
W24
W23
W27
Y27
AA28
W28
AB27
Y26
AB28
R28
P25
R23
R25
T23
T26
AA26

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1

6 CLK_GMCHHCLK#
6 CLK_GMCHHCLK
R410
27.4/1%
R409
27.4/1%

MCH_HDVREF

U43A

H_A#[3:31]

H_A#[3:31]

R414
301/1%

HDVREF0
HDVREF1
HDVREF2
HCCVREF
HAVREF
HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10
HUB_PSTRB
HUB_PSTRB#
HLZCOMP
PSWING
HUB_LVREF
MONTARA_GMCH_A

H_ADS#
H_TRDY#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BREQ0#
H_BNR#
H_BPRI#
H_DBSY#
H_RS#0
H_RS#1
H_RS#2

HUB I/F

K22
H27
K25
L24
J27
G28
L27
L23
L25
J24
H25
K23
G27
K26
J23
H26
F25
F26
B27
H23
E27
G25
F28
D27
G24
C28
B26
G22
C26
E26
G23
B28
B21
G21
C24
C23
D22
C25
E24
D24
G20
E23
B22
B23
F23
F21
C20
C21
G18
E19
E20
G17
D20
F19
C19
C17
F17
B19
G16
E16
C16
E17
D16
C18

H_D#[0:63]

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

L28
M25
N24
M28
N28
N27
P27
M23
N25
P28
M26
N23
P26
M27

H_RS#0
H_RS#1
H_RS#2

1
1

H_ADS#
H_TRDY#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_RS#0
H_RS#1
H_RS#2

1
1
1
1
1
1
1
1
1
1
1
1
1
1

C472
0.01U

NEAR_NB
MCH_PSWING

C467
0.1uF

MCH_LVREF
R460
100/1%

NEAR_NB

ASUS PROJECT:
A

R464
100/1%

C473
0.1uF

REVISION

2.2

+V1.35S

+VCCP

1,2,3,5,10,11,18,19,20,50

+V1.35S

3,10,11,50
5

MCH_PSWING
VOLTAGE=0.8V+-8%

NEAR_NB

M2Ne

+VCCP

MCH_LVREF
VOLTAGE=0.35V+-8%

DATE: Tuesday, January 06, 2004

SHEET
OF
9
56
B

DESCRIPTION:
C

SCHEMATIC FILE NAME : <Doc>

Montara-GME (2 of 4) LIBRARY DATE :

D

DESIGN ENGINEER :
E

VSS

VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168

T16
AA16
AE16
A17
D17
H17
N17
R17
U17
AB17
AC17
F18
J18
AA18
AG18
A19
D19
H19
AB19
AE19
F20
J20
AA20
AC20
A21
D21
H21
M21
P21
T21
V21
Y21
AA21
AB21
AG21
B24
F22
J22
L22
N22
R22
U22
W22
AE22
A23
D23
AA23
AC23
AJ23
F24
H24
K24
M24
P24
T24
V24
AA24
AG24
A25
D25
AA25
AE25
G26
J26
L26
N26
R26
U26
W26
AB26
A27
F27
AC27
AG27
AJ27
AC28
AE28
C29
E29
G29
J29
L29
N29
U29

+V1.35S

+VCCP

U43E
J15
P13
T13
N14
R14
U14
P15
T15
AA15
N16
R16
U16
P17
T17
AA17
AA19
W21
H14

+V1.35S
L65

V1
Y1
W5
U6
U8
W8
V7
V9

+V1.2S_HPLL

0.82UH
CT10 3528 +
22uF/10V

C397
0.1U
+V1.35S

D29
Y2
+V1.2S_DPLLA
+V1.2S_DPLLB

C204
0.1U

E1
J1
N1
E4
J4
M4
E6
H7
J8
L8
M8
N8
R8
K9
M9
P9

+V1.35S
L67

10UH_0805
7343

+V1.2S_DPLLA

CT14
220uF/2.5V-7343

A6
B16

C423
0.1U
+V1.5S

+V1.35S
L66

10UH_0805
7343

CT12
220uF/2.5V-7343

A9
B9
B8

+V1.2S_DPLLB

A11
B11

+
C411
0.1U

G13
B14
J13
B15
+V2.5

F9
B10
D10
A12

0805

R422

0-0805

+3VS

A3
A4

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCCHL0
VCCHL1
VCCHL2
VCCHL3
VCCHL4
VCCHL5
VCCHL6
VCCHL7

POWER

VTTLF0
VTTLF1
VTTLF2
VTTLF3
VTTLF4
VTTLF5
VTTLF6
VTTLF7
VTTLF8
VTTLF9
VTTLF10
VTTLF11
VTTLF12
VTTLF13
VTTLF14
VTTLF15
VTTLF16
VTTLF17
VTTLF18
VTTLF19
VTTLF20
VTTHF0
VTTHF1
VTTHF2
VTTHF3
VTTHF4

VCCAHPLL
VCCAGPLL

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36

VCCADPLLA
VCCADPLLB
VCCDVO_0
VCCDVO_1
VCCDVO_2
VCCDVO_3
VCCDVO_4
VCCDVO_5
VCCDVO_6
VCCDVO_7
VCCDVO_8
VCCDVO_9
VCCDVO_10
VCCDVO_11
VCCDVO_12
VCCDVO_13
VCCDVO_14
VCCDVO_15
VCCADAC0
VCCADAC1
VSSADAC
VCCALVDS
VSSALVDS
VCCDLVDS0
VCCDLVDS1
VCCDLVDS2
VCCDLVDS3
VCCTXLVDS0
VCCTXLVDS1
VCCTXLVDS2
VCCTXLVDS3

VCCQSM0
VCCQSM1

VCCGPIO_0
VCCGPIO_1

VCCASM0
VCCASM1

G15
H16
H18
J19
H20
L21
N21
R21
U21
H22
M22
P22
T22
V22
Y29
K29
F29
AB29
A26
A20
A18

A22
A24
H29
M29
V29

C396

0.1U

C412

0.1U

AC1
AG1
AB3
AF3
Y4
AJ5
AA6
AB6
AF6
Y7
AA8
AB8
Y9
AF9
AJ9
AB10
AA11
AB12
AF12
AA13
AJ13
AB14
AF15
AB16
AJ17
AB18
AF18
AB20
AF21
AJ21
AB22
AF24
AJ25
AF27
AC29
AF29
AG29

C398

0.1U

C405

0.1U

C416

0.1U

+V2.5

C482
0805

10U_0805

C483
0.1U
+V2.5

AJ6
AJ8

+V2.5_QSM
R472

AD1
AF1

+V1.35S

0805

+V1.2S_ASM

0-0805
0805

R486

0-0805

MONTARA_GMCH_E
C424
0.1U
CT19

6032

C493
0.1U

100UF/2V_7343

AJ26
T9
L6
E28
D28
C22
AJ20
AJ18
AJ12
AJ10
AA29
W29

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83

VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169

C1
G1
L1
U1
AA1
AE1
R2
AG3
AJ3
D4
G4
K4
N4
T4
W4
AA4
AC4
AE4
B5
U5
Y5
Y6
AG6
C7
E7
G7
J7
M7
R7
AA7
AE7
AJ7
H8
K8
P8
T8
V8
Y8
AC8
E9
L9
N9
R9
U9
W9
AB9
AG9
C10
J10
AA10
AE10
D11
F11
H11
AB11
AC11
AJ11
J12
AA12
AG12
A13
D13
F13
H13
N13
R13
U13
AB13
AE13
J14
P14
T14
AA14
AC14
D15
H15
N15
R15
U15
AB15
AG15
F16
J16
P16

MONTARA_GMCH_D

U43D
1

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
10
56
B

DESCRIPTION:
C

SCHEMATIC FILE NAME : <Doc>

Montara-GME (3 of 4) LIBRARY DATE :

D

DESIGN ENGINEER :
E

+V1.35S
C194

C188

0805

0805

10U_0805

+5VS

C171
0805

10U_0805

C176
0.1U

C201
0.1U

C192
0.1U

C180
0.1U

C167
0.1U

C165
0.1U

C166
0.1U

C169
0.1U

C400
0.1U

C164
0.1U

C190
0.1U

10U_0805

+5V
+VCCP
7343

R767

R768

0_*

+ CT11

220uF/2.5V-7343

+V2.5

7343

+ CT17

C200
0.1U

C220
0.1U

C454
0.1U

C469
0.1U

C477
0.1U

C487
0.1U

C474
0.1U

C471
0.1U

C178
0.1U

C195
0.1U

C462
0.1U

C450
0.1U

C418
0.1U

C193
0.1U

C187
0.1U

C422
0.1U

C415
0.1U

C414
0.1U

+V2.5
330uF/4v-7343
U20
R169
10K_1%

1
2

+V2.5_DIV

TLV2471
1OUT

VDD

+V1.5S

GND
1IN+
U-tlv2471

R170
10K_1%

3528

1IN-

R174
+1.25VREF_OP

CT16 3528 +
33uF/10V

3528 +
CT15
33uF/10V

CT13
47uF/6.3V

0
SM_VREF_DDR

8,12,13,14

ASUS PROJECT: M2Ne

A

REVISION

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
11
56
B

DESCRIPTION:
C

SCHEMATIC FILE NAME : <Doc>

Montara-GME (4 of 4) LIBRARY DATE :

D

DESIGN ENGINEER :
E

8,11,13,14

SM_VREF_DDR

8,15

SM_CS#2

R456

0_402

8,15

49
21
22
23
24

SM_DQS_R0
SM_DQS_R1

51
16

SM_BS0
SM_BS1

26
27

SM_CS#2_OB

(0402)

8,13,15
8,13,15

SM_VREF_DDR
SM_WE#
SM_CAS#
SM_RAS#

SM_BS0
SM_BS1

44
45
46

SM_CKE2

8,13 CLK_DCLK3
8,13 CLK_DCLK3#
SM_DM_R0
SM_DM_R1

R157

47
20

+V2.5
120

1
18
33
3
9
15
55
61

34
48
66
6
12
52
58
64

VREF
WE#
CAS#
RAS#
CS#
UDQS
LDQS
BA0
BA1
CKE
CLK
CLK#

U47

UDM
LDM

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC
NC
NC
NC

65
63
62
60
59
57
56
54
13
11
10
8
7
5
4
2

SM_DQ_R0
SM_DQ_R1
SM_DQ_R2
SM_DQ_R3
SM_DQ_R4
SM_DQ_R5
SM_DQ_R6
SM_DQ_R7
SM_DQ_R8
SM_DQ_R9
SM_DQ_R10
SM_DQ_R11
SM_DQ_R12
SM_DQ_R13
SM_DQ_R14
SM_DQ_R15

42
41
28
40
39
38
37
36
35
32
31
30
29

SM_MAA12
SM_MAA11
SM_MAA10
SM_MAA9
SM_MAA8
SM_MAA7
SM_MAA6
SM_MAB5
SM_MAB4
SM_MAA3
SM_MAB2
SM_MAB1
SM_MAA0

SM_WE#
SM_CAS#
SM_RAS#

SM_VREF_DDR

49

SM_WE#
SM_CAS#
SM_RAS#
SM_CS#2_OB

21
22
23
24

SM_DQS_R2
SM_DQS_R3

51
16

SM_BS0
SM_BS1

26
27

SM_CKE2

44
45
46

CLK_DCLK3
CLK_DCLK3#
SM_DM_R2
SM_DM_R3

+V2.5

47
20
1
18
33
3
9
15
55
61

34
48
66
6
12
52
58
64

VREF
WE#
CAS#
RAS#
CS#
UDQS
LDQS
BA0
BA1
CKE
CLK
CLK#

U46

UDM
LDM

VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0.1U

21
22
23
24

SM_DQS_R6
SM_DQS_R7

51
16

SM_BS0
SM_BS1

26
27

SM_CKE2

44
45
46

8,13 CLK_DCLK4
8,13 CLK_DCLK4#
SM_DM_R6
SM_DM_R7

R463

49

SM_WE#
SM_CAS#
SM_RAS#
SM_CS#2_OB

47
20

+V2.5
120

1
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64

VREF

UDQS
LDQS
BA0
BA1
CKE
CLK
CLK#

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

NC
NC
NC
NC
NC
NC
NC

65
63
62
60
59
57
56
54
13
11
10
8
7
5
4
2

SM_DQ_R16
SM_DQ_R17
SM_DQ_R18
SM_DQ_R19
SM_DQ_R20
SM_DQ_R21
SM_DQ_R22
SM_DQ_R23
SM_DQ_R24
SM_DQ_R25
SM_DQ_R26
SM_DQ_R27
SM_DQ_R28
SM_DQ_R29
SM_DQ_R30
SM_DQ_R31

42
41
28
40
39
38
37
36
35
32
31
30
29

SM_MAA12
SM_MAA11
SM_MAA10
SM_MAA9
SM_MAA8
SM_MAA7
SM_MAA6
SM_MAB5
SM_MAB4
SM_MAA3
SM_MAB2
SM_MAB1
SM_MAA0

SM_VREF_DDR

49

SM_WE#
SM_CAS#
SM_RAS#
SM_CS#2_OB

21
22
23
24

SM_DQS_R4
SM_DQS_R5

51
16

SM_BS0
SM_BS1

26
27

SM_CKE2

44
45
46

SM_DM_R4
SM_DM_R5

47
20

+V2.5
1
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64

DDR 4MX4X16

U44

UDM
LDM

A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC
NC
NC
NC

65
63
62
60
59
57
56
54
13
11
10
8
7
5
4
2

SM_DQ_R53
SM_DQ_R54
SM_DQ_R55
SM_DQ_R52
SM_DQ_R49
SM_DQ_R51
SM_DQ_R50
SM_DQ_R48
SM_DQ_R56
SM_DQ_R57
SM_DQ_R60
SM_DQ_R61
SM_DQ_R59
SM_DQ_R58
SM_DQ_R62
SM_DQ_R63

42
41
28
40
39
38
37
36
35
32
31
30
29

SM_MAA12
SM_MAA11
SM_MAA10
SM_MAA9
SM_MAA8
SM_MAA7
SM_MAA6
SM_MAB5
SM_MAB4
SM_MAA3
SM_MAB2
SM_MAB1
SM_MAA0

SM_DQ_R[63:0]

SM_DQS_R[0:7]

SM_MAB5
SM_MAB4

8,13,15
8,13,15

SM_MAB2
SM_MAB1

8,13,15
8,13,15

13,14,15

SM_MAA[12:0]

8,13,14,15

SM_DM_R[7:0]

13,14,15

SM_DQS_R[0:7]

13,14,15

14
17
19
25
43
50
53

DDR 4MX4X16

CLK_DCLK4
CLK_DCLK4#

14
17
19
25
43
50
53

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

WE#
CAS#
RAS#
CS#

BOT
SIDE

A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

SM_VREF_DDR
C478

14
17
19
25
43
50
53

DDR 4MX4X16

8,13,15
8,13,15
8,13,15

VREF

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

WE#
CAS#
RAS#
CS#
UDQS
LDQS
BA0
BA1
CKE
CLK
CLK#

U45

UDM
LDM

A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC
NC
NC
NC

65
63
62
60
59
57
56
54
13
11
10
8
7
5
4
2

SM_DQ_R33
SM_DQ_R32
SM_DQ_R34
SM_DQ_R35
SM_DQ_R36
SM_DQ_R37
SM_DQ_R38
SM_DQ_R39
SM_DQ_R42
SM_DQ_R43
SM_DQ_R47
SM_DQ_R46
SM_DQ_R45
SM_DQ_R44
SM_DQ_R40
SM_DQ_R41

42
41
28
40
39
38
37
36
35
32
31
30
29

SM_MAA12
SM_MAA11
SM_MAA10
SM_MAA9
SM_MAA8
SM_MAA7
SM_MAA6
SM_MAB5
SM_MAB4
SM_MAA3
SM_MAB2
SM_MAB1
SM_MAA0

34

33

TOP
VIEW

66

33

34

BOT
VIEW
1

66

14
17
19
25
43
50
53

DDR 4MX4X16

+V2.5

C215
7343 +
CT4
330UF/4V_7343

0805

10U_0805

ASUS PROJECT:
A

REVISION

M2Ne

2.2

C517
C524
C511
C510
C513
C516
C514
C518
C522
C520
C526
C199
C481
C479
C486
C217
C218
C216
0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402

DATE: Tuesday, January 06, 2004

12
SHEET
OF
56
B

DESCRIPTION:
C

C198
0.1U_402

C515
0.1U_402

SCHEMATIC FILE NAME : <Doc>

ON_BOARD_256MB_DDR_1 LIBRARY DATE :

D

DESIGN ENGINEER :
E

8,11,12,14

SM_VREF_DDR

8,15

SM_CS#3

R152

0_402

8,15

49
21
22
23
24

SM_DQS_R1
SM_DQS_R0

51
16

SM_BS0
SM_BS1

26
27

SM_CS#3_OB

(0402)

8,12,15
8,12,15

SM_VREF_DDR
SM_WE#
SM_CAS#
SM_RAS#

SM_BS0
SM_BS1

44
45
46

SM_CKE3

8,12 CLK_DCLK3
8,12 CLK_DCLK3#
SM_DM_R1
SM_DM_R0

47
20

+V2.5
1
18
33
3
9
15
55
61

34
48
66
6
12
52
58
64

VREF
WE#
CAS#
RAS#
CS#
UDQS
LDQS
BA0
BA1
CKE
CLK
CLK#

U18

UDM
LDM

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC
NC
NC
NC

65
63
62
60
59
57
56
54
13
11
10
8
7
5
4
2

SM_DQ_R15
SM_DQ_R14
SM_DQ_R13
SM_DQ_R12
SM_DQ_R11
SM_DQ_R10
SM_DQ_R9
SM_DQ_R8
SM_DQ_R7
SM_DQ_R6
SM_DQ_R5
SM_DQ_R4
SM_DQ_R3
SM_DQ_R2
SM_DQ_R1
SM_DQ_R0

42
41
28
40
39
38
37
36
35
32
31
30
29

SM_MAA12
SM_MAA11
SM_MAA10
SM_MAA9
SM_MAA8
SM_MAA7
SM_MAA6
SM_MAB5
SM_MAB4
SM_MAA3
SM_MAB2
SM_MAB1
SM_MAA0

SM_WE#
SM_CAS#
SM_RAS#

SM_VREF_DDR

49

SM_WE#
SM_CAS#
SM_RAS#
SM_CS#3_OB

21
22
23
24

SM_DQS_R3
SM_DQS_R2

51
16

SM_BS0
SM_BS1

26
27

SM_CKE3

44
45
46

CLK_DCLK3
CLK_DCLK3#
SM_DM_R3
SM_DM_R2

+V2.5

47
20
1
18
33
3
9
15
55
61

34
48
66
6
12
52
58
64

VREF
WE#
CAS#
RAS#
CS#
UDQS
LDQS
BA0
BA1
CKE
CLK
CLK#

U17

UDM
LDM

VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

0.1U

49

SM_WE#
SM_CAS#
SM_RAS#
SM_CS#3_OB

21
22
23
24

SM_DQS_R7
SM_DQS_R6

51
16

SM_BS0
SM_BS1

26
27

SM_CKE3

44
45
46

8,12 CLK_DCLK4
8,12 CLK_DCLK4#
SM_DM_R7
SM_DM_R6

47
20

+V2.5
1
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64

VREF

UDQS
LDQS
BA0
BA1
CKE
CLK
CLK#

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

NC
NC
NC
NC
NC
NC
NC

65
63
62
60
59
57
56
54
13
11
10
8
7
5
4
2

SM_DQ_R31
SM_DQ_R30
SM_DQ_R29
SM_DQ_R28
SM_DQ_R27
SM_DQ_R26
SM_DQ_R25
SM_DQ_R24
SM_DQ_R23
SM_DQ_R22
SM_DQ_R21
SM_DQ_R20
SM_DQ_R19
SM_DQ_R18
SM_DQ_R17
SM_DQ_R16

42
41
28
40
39
38
37
36
35
32
31
30
29

SM_MAA12
SM_MAA11
SM_MAA10
SM_MAA9
SM_MAA8
SM_MAA7
SM_MAA6
SM_MAB5
SM_MAB4
SM_MAA3
SM_MAB2
SM_MAB1
SM_MAA0

SM_VREF_DDR

49

SM_WE#
SM_CAS#
SM_RAS#
SM_CS#3_OB

21
22
23
24

SM_DQS_R5
SM_DQS_R4

51
16

SM_BS0
SM_BS1

26
27

SM_CKE3

44
45
46

SM_DM_R5
SM_DM_R4

47
20

+V2.5
1
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64

DDR 4MX4X16

U15

UDM
LDM

A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC
NC
NC
NC

65
63
62
60
59
57
56
54
13
11
10
8
7
5
4
2

SM_DQ_R63
SM_DQ_R62
SM_DQ_R58
SM_DQ_R59
SM_DQ_R61
SM_DQ_R60
SM_DQ_R57
SM_DQ_R56
SM_DQ_R48
SM_DQ_R50
SM_DQ_R51
SM_DQ_R49
SM_DQ_R52
SM_DQ_R55
SM_DQ_R54
SM_DQ_R53

42
41
28
40
39
38
37
36
35
32
31
30
29

SM_MAA12
SM_MAA11
SM_MAA10
SM_MAA9
SM_MAA8
SM_MAA7
SM_MAA6
SM_MAB5
SM_MAB4
SM_MAA3
SM_MAB2
SM_MAB1
SM_MAA0

SM_DQ_R[63:0]

SM_DQS_R[0:7]

SM_MAB5
SM_MAB4

8,12,15
8,12,15

SM_MAB2
SM_MAB1

8,12,15
8,12,15

12,14,15

SM_MAA[12:0]

8,12,14,15

SM_DM_R[7:0]

12,14,15

SM_DQS_R[0:7]

12,14,15

14
17
19
25
43
50
53

DDR 4MX4X16

CLK_DCLK4
CLK_DCLK4#

14
17
19
25
43
50
53

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

WE#
CAS#
RAS#
CS#

TOP
SIDE

A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

SM_VREF_DDR
C470

14
17
19
25
43
50
53

DDR 4MX4X16

8,12,15
8,12,15
8,12,15

VREF

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

WE#
CAS#
RAS#
CS#
UDQS
LDQS
BA0
BA1
CKE
CLK
CLK#

U16

UDM
LDM

A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC
NC
NC
NC

65
63
62
60
59
57
56
54
13
11
10
8
7
5
4
2

SM_DQ_R41
SM_DQ_R40
SM_DQ_R44
SM_DQ_R45
SM_DQ_R46
SM_DQ_R47
SM_DQ_R43
SM_DQ_R42
SM_DQ_R39
SM_DQ_R38
SM_DQ_R37
SM_DQ_R36
SM_DQ_R35
SM_DQ_R34
SM_DQ_R32
SM_DQ_R33

42
41
28
40
39
38
37
36
35
32
31
30
29

SM_MAA12
SM_MAA11
SM_MAA10
SM_MAA9
SM_MAA8
SM_MAA7
SM_MAA6
SM_MAB5
SM_MAB4
SM_MAA3
SM_MAB2
SM_MAB1
SM_MAA0

14
17
19
25
43
50
53

34

33

TOP
VIEW

66

33

34

BOT
VIEW
1

66

DDR 4MX4X16

+V2.5

C527
0805
5

10U_0805

ASUS PROJECT:
A

C489
C504
C498
C495
C506
C501
C492
C488
C475
C476
C461
C503
C525
C505
C500
C499
C460
C490
C459
C480
C458
0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

13
SHEET
OF
56
B

DESCRIPTION:
C

SCHEMATIC FILE NAME : <Doc>

ON_BOARD_256MB_DDR_2 LIBRARY DATE :

D

DESIGN ENGINEER :
E

CN27
8,15 SM_MAA1
8,15 SM_MAA2
12,13,15

SM_DQ_R[0:63]

SM_DQ_R[0:63]

12,13,15

SM_DQS_R[0:8]

SM_DQS_R[0:8]

15 SM_MAA_R[0:12]
12,13,15

8,15 SM_MAA4
8,15 SM_MAA5

SM_MAA_R[0:12]
SM_DM_R[0:8]

SM_DM_R[0:8]

15
15

SM_BS_R0
SM_BS_R1

4,6,7,33
4,6,7,33

112
111
110
109
108
107
106
105
102
101
115
100
99
97

SM_BS_R0
SM_BS_R1

117
116
98
71
73
79
83
72
74
80
84
35
37
160
158
89
91
96
95
120
118
119
121
122
194
196
198
195
193
86

SM_CLK_DDR0
SM_CLK_DDR#0
SM_CLK_DDR1
SM_CLK_DDR#1
SM_CLK_DDR2
SM_CLK_DDR#2
SM_CKE0
SM_CKE1
SM_CAS_R#
SM_RAS_R#
SM_WE_R#
SM_CS#0
SM_CS#1

8
CLK_DCLK0
8
CLK_DCLK0#
8
CLK_DCLK1
8
CLK_DCLK1#
8 CLK_DCLK2
8 CLK_DCLK2#
8,15
SM_CKE0
8,15
SM_CKE1
15
SM_CAS_R#
15
SM_RAS_R#
15
SM_WE_R#
8,15
SM_CS#0
8,15
SM_CS#1

SM_MAA_R0
SM_MAA1
SM_MAA2
SM_MAA_R3
SM_MAA4
SM_MAA5
SM_MAA_R6
SM_MAA_R7
SM_MAA_R8
SM_MAA_R9
SM_MAA_R10
SM_MAA_R11
SM_MAA_R12

SMBCK_3S
SMBDA_3S

12
26
48
62
134
148
170
184
78

SM_DQS_R0
SM_DQS_R1
SM_DQS_R2
SM_DQS_R3
SM_DQS_R4
SM_DQS_R5
SM_DQS_R6
SM_DQS_R7

11
25
47
61
133
147
169
183
77

+V2.5

C523
CT3

7343

C502

0805

330UF/4V_7343

10U_0805

C208

C205

C196

C212

C213

C214

C207

C197

C512

C496

C494

C521

0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402 0.1U_402

9
21
33
45
57
69
81
93
113
131
143
155
157
167
179
191
10
22
34
36
46
58
70
82
92
94
114
132
144
156
168
180
192

+V2.5

+3VS

199
197
1
2

8,11,12,13

SM_VREF_DDR
C203

ASUS PROJECT:
A

M2Ne

REVISION

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
14
56
B

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

SODIMM

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

DU
DU
DU
DU
201
202

VDDID
VDDSPD
VREF
VREF

0.1U

DESCRIPTION:
C

BA0
BA1
BA2(DU)
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0
CK0#
CK1
CK1#
CK2
CK2#
CKE0
CKE1
CAS#
RAS#
WE#
S0#
S1#
SA0
SA1
SA2
SCL
SDA
DU/RESET#

DDR SODIMM

SM_DM_R0
SM_DM_R1
SM_DM_R2
SM_DM_R3
SM_DM_R4
SM_DM_R5
SM_DM_R6
SM_DM_R7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
DU/A13

5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190

SM_DQ_R0
SM_DQ_R1
SM_DQ_R2
SM_DQ_R3
SM_DQ_R4
SM_DQ_R5
SM_DQ_R6
SM_DQ_R7
SM_DQ_R8
SM_DQ_R9
SM_DQ_R10
SM_DQ_R11
SM_DQ_R12
SM_DQ_R13
SM_DQ_R14
SM_DQ_R15
SM_DQ_R16
SM_DQ_R17
SM_DQ_R18
SM_DQ_R19
SM_DQ_R20
SM_DQ_R21
SM_DQ_R22
SM_DQ_R23
SM_DQ_R24
SM_DQ_R25
SM_DQ_R26
SM_DQ_R27
SM_DQ_R28
SM_DQ_R29
SM_DQ_R30
SM_DQ_R31
SM_DQ_R32
SM_DQ_R33
SM_DQ_R34
SM_DQ_R35
SM_DQ_R36
SM_DQ_R37
SM_DQ_R38
SM_DQ_R39
SM_DQ_R40
SM_DQ_R41
SM_DQ_R42
SM_DQ_R43
SM_DQ_R44
SM_DQ_R45
SM_DQ_R46
SM_DQ_R47
SM_DQ_R48
SM_DQ_R49
SM_DQ_R50
SM_DQ_R51
SM_DQ_R52
SM_DQ_R53
SM_DQ_R54
SM_DQ_R55
SM_DQ_R56
SM_DQ_R57
SM_DQ_R58
SM_DQ_R59
SM_DQ_R60
SM_DQ_R61
SM_DQ_R62
SM_DQ_R63

3
15
27
39
51
63
75
87
103
125
137
149
159
161
173
185
4
16
28
38
40
52
64
76
88
90
104
126
138
150
162
174
186

85
123
124
200
201
202

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

SM_DQ[0:63]

SM_DQ[0:63]

SM_DQ_R[0:63]

SM_DQ_R[0:63]

SM_MAA[0:12]
SM_MAA_R[0:12]

SM_MAA[0:12]

8
12,13,14
8,12,13,14

SM_MAA_R[0:12]

14

SM_DM[0:7]

SM_DM[0:7]

SM_DM_R[0:7]

SM_DM_R[0:7]

SM_CKE[0:3]

+V1.25S
12,13,14

SM_CKE[0:3]

8,12,13,14

SM_CS#[0:3]

8,12,13,14

SM_DQS[0:8]

SM_DQS[0:8]

SM_DQS_R[0:8]

SM_DQS_R[0:8]

12,13,14

+V1.25S
RN90
3
10_2R4P 1

4
2

SM_DQ_R1
SM_DQ_R0

SM_DQ2
SM_DQS0
SM_DQ4
SM_DQ5

RN89
10_2R4P
RN64
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ_R2
SM_DQS_R0
SM_DQ_R4
SM_DQ_R5

SM_DQ7
SM_DQ12
SM_DQ8
SM_DQ3

RN62
10_2R4P
RN88
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ_R7
SM_DQ_R12
SM_DQ_R8
SM_DQ_R3

SM_DQ11
SM_DQ10
SM_DQ13
SM_DM1

RN86
10_2R4P
RN61
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ_R11
SM_DQ_R10
SM_DQ_R13
SM_DM_R1

SM_DQ14
SM_DQ15
SM_DQ17
SM_DQ16

RN60
10_2R4P
RN85
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ_R14
SM_DQ_R15
SM_DQ_R17
SM_DQ_R16

SM_DQ18
SM_DQS2
SM_DQ20
SM_DQ21

RN84
10_2R4P
RN65
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ_R18
SM_DQS_R2
SM_DQ_R20
SM_DQ_R21

SM_DQ23
SM_DQ28
SM_DQ24
SM_DQ19

RN58
10_2R4P
RN83
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ_R23
SM_DQ_R28
SM_DQ_R24
SM_DQ_R19

SM_DQ27
SM_DQ26
SM_DQ29
SM_DM3

RN81
10_2R4P
RN57
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ_R27
SM_DQ_R26
SM_DQ_R29
SM_DM_R3

C183

0.1U_402

C430

C448

0.1U_402

0.1U_402

C181

C186

3
1
3
1

4
2
4
2

RN54
3
10_2R4P 1

4
2

3
1
3
1

4
2
4
2

SM_DQ_R30
SM_DQ_R31
SM_DQ_R33
SM_DQ_R32

SM_DQ36
SM_DQ37
SM_DQ34
SM_DQS4

RN52
10_2R4P
RN78
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ_R36
SM_DQ_R37
SM_DQ_R34
SM_DQS_R4

SM_DQ43
SM_DQ42
SM_DQ40
SM_DQ35

RN75
10_2R4P
RN77
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ_R43
SM_DQ_R42
SM_DQ_R40
SM_DQ_R35

SM_DQ39
SM_DQ44
SM_DQ46
SM_DQ47

RN50
10_2R4P
RN48
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ49
SM_DQ48
SM_DQ50
SM_DQS6

RN74
10_2R4P
RN73
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ_R49
SM_DQ_R48
SM_DQ_R50
SM_DQS_R6

SM_DQ52
SM_DQ53
SM_DM6
SM_DQ54

RN47
10_2R4P
RN46
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ_R52
SM_DQ_R53
SM_DM_R6
SM_DQ_R54

SM_DQ56
SM_DQ51
SM_DQ59
SM_DQ58

RN72
10_2R4P
RN70
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ_R56
SM_DQ_R51
SM_DQ_R59
SM_DQ_R58

SM_DQ55
SM_DQ60
SM_DQ62
SM_DQ63

RN45
10_2R4P
RN43
10_2R4P

3
1
3
1

4
2
4
2

SM_DQ_R55
SM_DQ_R60
SM_DQ_R62
SM_DQ_R63

SM_DM2
SM_DQ22

RN59
3
10_2R4P 1

4
2

SM_DQ_R39
SM_DQ_R44
SM_DQ_R46
SM_DQ_R47

SM_DQ_R43
SM_DQ_R47
SM_DM_R4
SM_DQ_R33

2
4
6
8

1
3
5
7

RN32

SM_DQ_R46
SM_DQ_R45
SM_DQ_R42
SM_DQS_R5

56_8P4R_402
2
4
6
8

1
3
5
7

RN31

SM_DM_R5
SM_DQ_R41
SM_DQ_R40
SM_DQ_R44

56_8P4R_402
2
4
6
8

1
3
5
7

RN30

SM_DQS_R6
SM_DM_R6
SM_DQ_R54
SM_DQ_R53

56_8P4R_402
2
4
6
8

1
3
5
7

RN28

SM_DQ_R49
SM_DQ_R51
SM_DQ_R50
SM_DQ_R48

56_8P4R_402
2
4
6
8

1
3
5
7

RN27

7
5
3
1

SM_DQ_R15
SM_DQ_R14
SM_DQ_R13
SM_DQ_R12

56_8P4R_402
8
RN42 6
4
2

7
5
3
1

SM_DQ_R21
SM_DQ_R17
SM_DQ_R16
SM_DM_R2

56_8P4R_402
8
RN41 6
4
2

7
5
3
1

SM_DQ_R19
SM_DQS_R2
SM_DQ_R23
SM_DQ_R22

56_8P4R_402
8
RN40 6
4
2

7
5
3
1

SM_DQ_R25
SM_DM_R3
SM_DQ_R18
SM_DQ_R20

56_8P4R_402
8
RN38 6
4
2

7
5
3
1

SM_DQ_R27
SM_DQS_R3
SM_DQ_R24
SM_DQ_R26

8
RN37 6
4
2

7
5
3
1

SM_DQ_R31
SM_DQ_R30
SM_DQ_R29
SM_DQ_R28

56_8P4R_402
8
RN34 6
4
2

7
5
3
1

SM_DQ_R39
SM_DQ_R37
SM_DQ_R36
SM_DQ_R34

56_8P4R_402
8
6
4
2

7
5
3
1

SM_DQ_R32
SM_DQ_R35
SM_DQ_R38
SM_DQS_R4

56_8P4R_402
2
RN39 4
6
8

1
3
5
7

SM_BS1
SM_MAA0
SM_MAA6
SM_MAA11

56_8P4R_402
2
4
6
8

1
3
5
7

SM_MAA10
SM_MAA3
SM_MAA7
SM_MAA9

0.1U_402

C185

C429

0.1U_402

RN51
10_2R4P
RN49
10_2R4P

3
1
3
1

2
4
6
8

1
3
5
7

RN26

SM_DQ_R59
SM_DQ_R57
SM_DQ_R60
SM_DQ_R56

56_8P4R_402
2
4
6
8

1
3
5
7

RN25

SM_DQ_R63
SM_DQ_R62
SM_DQ_R58
SM_DQ_R61

56_8P4R_402
2
4
6
8

1
3
5
7

RN5

56_8P4R_402
8
6
4
2

7
5
3
1

SM_DM_R2
SM_DQ_R22
SM_MAA1
SM_MAA4
SM_MAA2
SM_MAA5

0.1U_402
SM_DM4
SM_DQ38
SM_DQ45
SM_DM5

4
2
4
2

SM_DM_R4
SM_DQ_R38
SM_DQ_R45
SM_DM_R5

4
2
4
2

SM_DM_R0
SM_DQ_R6
SM_DQ_R61
SM_DM_R7

RN33

8
6
4
2

SM_MAB1
SM_MAB2
SM_MAB4
SM_MAB5

RN8

56_8P4R_402
RN7

SM_DM0
SM_DQ6
SM_DQ61
SM_DM7

SM_MAA_R9
SM_MAA_R12
SM_MAA_R11
SM_MAA_R8

8,12,13

RN63
10_2R4P
RN44
10_2R4P

SM_BS1

SM_BS1

R485

SM_WE#

SM_WE#

10_402

(0402)
RN53
3
10_2R4P 1

SM_RAS#
SM_CAS#

8,12,13 SM_RAS#
8,12,13 SM_CAS#

3
1
3
1

R512

4
2
10_402

SM_MAA12

R448

56_8P4R_402

SM_DQS_R7
SM_DM_R7
SM_DQ_R55
SM_DQ_R52

56_402
(0402)

56_8P4R_402

SM_BS_R1

SM_BS_R1

SM_RAS_R#
SM_CAS_R#

14

SM_RAS_R#
SM_CAS_R#

SM_WE_R#

SM_WE_R#

(0402)

RN29 7
5
3
1

14
14
14

SM_MAA_R6
SM_MAA_R0

SM_MAB1
SM_MAB2
SM_MAB4
SM_MAB5

8,12,13
8,12,13
8,12,13
8,12,13

56_8P4R_402
RN2

RN3
SM_DQ_R10
SM_DQS_R1
SM_DQ_R8
SM_DQ_R9

8,12,13

8
RN21 6
4
2

56_8P4R_402

C449

0.1U_402

8,12,13
SM_MAA6
SM_MAA0

RN56
10_2R4P
RN79
10_2R4P

0.1U_402

C428

SM_MAA9
RN80
SM_MAA12 10_2R4P
SM_MAA11
RN55
SM_MAA8
10_2R4P

SM_DQ30
SM_DQ31
SM_DQ33
SM_DQ32

C184

0.1U_402

0.1U_402

SM_CS#[0:3]

SM_DQ1
SM_DQ0

2
4
6
8

1
3
5
7

8
6
4
2

7
5
3
1

7
5
3
1

56_8P4R_402
RN22
8
6
4
2

SM_DQ_R4
SM_DQ_R6
SM_DM_R1
SM_DQ_R11
4

56_8P4R_402

SM_BS0
SM_BS0
SM_MAA10
SM_DQS1
SM_DQ9
SM_DQ25
SM_DQS3

RN68
3
10_2R4P 1
RN87
10_2R4P
RN82
10_2R4P

3
1
1
3

4
2

SM_BS_R0
SM_MAA_R10

4
2
2
4

SM_DQS_R1
SM_DQ_R9
SM_DQ_R25
SM_DQS_R3

SM_BS_R0
+V1.25S

RN23

14

SM_DQ_R5
SM_DQS_R0
SM_DQ_R7
SM_DQ_R3
C189

C432

C438

C437

C436

C433

C434

C439

C453

C444

C456

C440 0805

0.1U_402 0.01U_4020.1U_402 0.01U_402 0.1U_402 0.01U_402 0.1U_402 0.01U_402 0.1U_402 0.01U_402

2
4
6
8

1
3
5
7

56_8P4R_402

56_8P4R_402

0805

10U_0805

10U_0805
RN6
SM_CS#1
SM_CS#0

SM_DQS7
SM_DQ57

RN71
3
10_2R4P 1

4
2

SM_MAA3
SM_MAA7

RN69
3
10_2R4P 1

4
2

C191
C452

C182

C446

C435

C442

C441

C447

C445

C443

C457

C431 0805

0.1U_402 0.01U_4020.1U_402 0.01U_402 0.1U_402 0.01U_402 0.1U_402 0.01U_402 0.1U_402 0.01U_402

7343

SM_CS#3
SM_CS#2

RN4

1
3

SM_DQS_R7
SM_DQ_R57
SM_MAA_R3
SM_MAA_R7

SM_DQ_R1
SM_DQ_R2
SM_DQ_R0
SM_DM_R0

2
4

1
3

56_2R4P
RN24
1
3

2
4

SM_CKE1
SM_CKE0

2
4

SM_CKE2
SM_CKE3

56_2R4P
RN35
2
4

1
3

R446

10U_0805
56_2R4P

R449
SM_DQS5
SM_DQ41

RN76
3
10_2R4P 1

4
2

SM_DQS_R5
SM_DQ_R41

100U/2V_7343

RN36
SM_MAA8
SM_BS0

1
3

2
4
56_2R4P

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

15
SHEET
OF
56
B

DESCRIPTION:
C

DDR Damping & Pull-up

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

56_402

SM_WE#

56_402

SM_RAS#

56_402

SM_CAS#

(0402)

56_2R4P

(0402)
R445
(0402)

DESIGN ENGINEER :
E

R251
R253
R248

0_402_*
(0402)
(0402)

0_402_*
0_402_*

R241

75 R652
+V1.5S

S
OE
74CBT3257

D3
BAV99_SOT23

13
14
10
11
6
5
3
2

4B2
4B1
3B2
3B1
2B2
2B1
1B2
1B1

VCC

1
15

PD_SWVGA

35

D2
BAV99_SOT23

D4
BAV99_SOT23
3

35

R
G
B

4A
3A
2A
1A

GND

8
8
8

35

PD_B

0.1U_402
U29

12
9
7
4

35

PD_G

C294

0402

10K_402
16

(0402)

+5VS

75 R651

75 R650

(0402)

PD_R

CN1
R262
R252
R247

(0402)
(0402)

0_402_*

R_Q

L43

L_0603

R_CN

0_402_*

G_Q

L44

L_0603

G_CN

0_402_*

B_Q

L45

L_0603

B_CN

R229

33

R230

33

R231

33

R232

33

1
9
2
10
3
11
4
12
5
13
6
14
7
15
8

(0402)
3

+12VS

HSYNC_Q

16

S2

G2

D1

Q41

VSYNC_Q
5

1M
6

R228

17

C275

C274

C276

C278

C279

C280

CON15(VGA)

2
4
6
8

C277
RN14

100P_* 100P_* 100P_* 100P_*

75_8P4R

D2

G1

S1

3.3P_* 3.3P_* 3.3P_*

1
3
5
7

VSYNC

HSYNC

DUAL_N_SC70-6P

DDC2BD_Q

S2

G2

D1

HSYNC_Q
VSYNC_Q

C720
DDC2BC_Q

0805

35

VSYNC_Q

35
35

DDC2BD_Q

35

+3VALWAYS

D2

DDC2BC_Q

R754
100K

G1

DDC2BD_Q
S1

220K_0805

HSYNC_Q

DDC2BC_Q
4

+5VS

8
8

R225

Q114

PCIRST#_3

Q113
2N7002

2N7002

DDC2BD
DDC2BC

ASUS PROJECT:
A

18,22,23,32,37,41

2.2K

2.2K

R227

Q40
DUAL_N_SC70-6P

M2Ne

REVISION
2.2

DATE: Tuesday, January 06, 2004

16
SHEET
OF
56
B

DESCRIPTION:
C

CRT Port

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+12VS
+3VS
LCD_+3VS
L21
L_1206
2

LCD_VCC

SI3456DV

C78
0.1U

C58
1000P

C50
0.1U

3
G

C39

C38
0.1U

0805

C37
0.1U

10U_0805
LCD_+3VS

4
3

Q9
2N7002

1
2
5
6

R38
1M

C88
0.1U

R47
1M

Q7

C66
47P

1
Q13
2N7002
1
R54
100K

8 LCD_ENVDD

LCD_VCC
CN11
LCD_VCC
4

L1_TX0-

8
8

L1_TX1+
L1_TX2-

8
37

PID1

37

PID0

L1_TXAC+
R12

R13

1
3
5
7
9
11
13
15
17
19
21
23

1
3
5
7
9
11
13
15
17
19

2
4
6
8
10
12
14
16
18
20

21
23

22
24

2
4
6
8
10
12
14
16
18
20

L1_TX0+
L1_TX1-

8
8

L1_TX2+
L1_TXAC-

8
8

22
24

CONN20(LCD)

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

17
SHEET
OF
56
B

DESCRIPTION:
C

LCD CON

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

26,29,31
9

AD[0:31]

AD[0:31]

HUB[0:11]

HUB[0:10]

+3VALWAYS

R186

10K

+VCCP

U50A

26,29,31
26,29,31
26,29,31
26,29,31

29
26
31
21
21,29
21,26
21
21,31

Not use for PC/PCI,

can program as GPIO

C/BE0#_3
C/BE1#_3
C/BE2#_3
C/BE3#_3

J2
K4
M4
N4

TP85
GNT1#_3
GNT2#_3
TP90
GNT4#_3

C1
E6
A7
B7
D6

REQ0#_3
REQ1#_3
REQ2#_3
REQ3#_3
REQ4#_3

B1
A2
B3
C7
B6

6
CLK_ICHPCI
21,26,29,31 DEVSEL#_3
21,26,29,31 FRAME#_3
21 PCPCI_REQA#_3
21 PCPCI_REQB#_3
21 PCPCI_GNTA#_3

TP88

21,26,29,31 IRDY#_3
21,26,29,31 PAR_3
21,26,29,31 PERR#_3
21 PLOCK#_3
26,29,31 PME#
8
PCIRST#_ICH
21,26,29,31 SERR#_3
21,26,29,31 STOP#_3
21,26,29,31 TRDY#_3

H5
J3
H3
K1
G5
J4
H4
J5
K2
G2
L1
G4
L2
H2
L3
F5
F4
N1
E5
N2
E3
N3
E4
M5
E2
P1
E1
P2
D3
R1
D2
P4

R499

0
R498

R566

0_*

P5
M3
F1
B5
A6
E8
C5
L5
G1
L4
M2
W2
U5
K5
F3
F2

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

CPU I/F

CPU_A20GATE
CPU_A20M#
CPU_DPSLP#
CPU_FERR#
CPU_IGNNE#
CPU_INIT#
CPU_INTR
CPU_NMI
CPU_PWRGOOD
CPU_RCIN#
CPU_SLP#
CPU_SMI#
CPU_STPCLK#

Hublink
I/F

PCI I/F

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

SM_INTRUDER#
SMLINK0
SMLINK1
S.M.
SMB_CLK
SMB_DATA
SMB_ALERT#/GPIO11

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10
HUB_PD11
HUB_CLK
HUB_PSTRB#
HUB_PSTRB
HUB_RCOMP
HUB_VREF
HUB_VSWING

INT_APICCLK
INT_APICD0
INT_APICD1
Interrupt
INT_PIRQA#
INT_PIRQB#
I/F
INT_PIRQC#
INT_PIRQD#
INT_PIRQE#/GPIO2
INT_PIRQF#/GPIO3
INT_PIRQG#/GPIO4
INT_PIRQH#/GPIO5
INT_IRQ14
INT_IRQ15
INT_SERIRQ

PCI_CLK
PCI_DEVSEL#
PCI_FRAME#
PCI_GPIO0/REQA#
PCI_GPIO1/REQB#/REQ5#
PCI_GPIO16/GNTA#
PCI_GPIO17/GNTB#/GNT5#
PCI_IRDY#
PCI_PAR
PCI_PERR#
PCI_LOCK#
PCI_PME#
PCI_RST#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

EEPROM
I/F

EEP_CS
EEP_DIN
EEP_DOUT
EEP_SHCLK

LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN I/F
LAN_TXD0
LAN_TXD1
LAN_TXD2
LAN_JCLK
LAN_RSTSYNC
LAN_RST#

W6
AC3
AB1
AC4
AB4
AA5

SM_INTRUDER#

Y22
AB23
U23
AA21
W21
V22
AB22
V21
Y23
U22
U21
W23
V23

A20GATE_3 39
H_A20M# 1
R588

R589
56

SMBCK_ICH
33
SMBDA_ICH
33
LID_RSM#
22,36

H_IGNNE#
1
H_INIT#
1,41
H_INTR
1
NMI_ICH
5
H_PWRGD
1
KBDCPURST_3

HUB0
HUB1
HUB2
HUB3
HUB4
HUB5
HUB6
HUB7
HUB8
HUB9
HUB10
R607

N20
P21
R23
M23
R22

HUB_PSTRB#
HUB_PSTRB

R614
10K_*

R613

H_DPSLP#
H_FERR#

56

39
R200

H_CPUSLP#

+V1.5S
56
CLK_ICHHUB

R610

HUB_PSTRB#
HUB_PSTRB
48.7/1%

J19
H19
K20
D5
C2
B4
A3
C8
D7
C3
C4
AC13
AA19
J22

R194
R196
R202

6
9
9

C615

EEP_DOUT
TP91

0.01uF

ICH_VREF
ICH_VSWING
0
10K
1 0 K INT_PIRQA#
21,26,29
INT_PIRQB#
21,26
INT_PIRQC#
21,26,31
INT_PIRQD#
21,31
INT_PIRQE#
21
INT_PIRQF#
21
INT_PIRQG#
21
INT_PIRQH#
21
IRQ14_3
21,32
IRQ15_3
21,32
SERIRQ_3
21,26,37,39

C616
0.01uF

TP17
TP20

D10
D11
A8
C12

1,8
1
2

H_SMI#
1
H_STPCLK#
1

L19
L20
M19
M21
P19
R19
T20
R20
P23
L22
N22
K21
T21

+VCCP

21

EEP_DOUT

ICH_VREF
VOLTAGE=0.35V+-8%

21

ICH_VSWING
VOLTAGE=0.8V+-8%

A10
A9
A11
B10
C10
A12
C11
B11
Y5

+V1.5S
+V1.5S
R183

10K

R612
130/1%

R609
487/1%
+3V

ICH4-M Part A

I f ICH4 LAN not used, pull down

through 10K

ICH_VSWING

C579

ICH_VREF

0.1uF
U54A
14
16,22,23,26,29,31,32,37,39,41

PCIRST#_3

R611
150/1%

C617
0.1uF

NEAR_SB

NEAR_SB

R608
150/1%

C614
0.1uF

74LVC08
1

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
18
56
B

DESCRIPTION:
C

ICH4-M (1 of 4)

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

PDD[0:15]

32

SDD[0:15]

PDD[0:15]
SDD[0:15]

6,7,43

14

U54C

14

U54B
32

74LVC08
4

SUSA#_3_D

SUSB#_3

100K_402

VRM_PWRGD_ICH

SUSA#_3

R198

10

(0402)

BAT_LLOW#_OC

R506

6,8,22,44

0.1U_402

39,40,47

VRM_PWRGD

C253

0402
1

74LVC08

BAT_LLOW#_OC_ICH

0_*

R581 0_402_*
(0402)

21

U50B

SUSA#_3_D
SUSB#_3

22,27,51
29,51

SUSB#_3
R507
6 CPU_STP#_3 R508
6 PCI_STP#_3

SUSC#_3

0
0_*

R505

0
J21
Y20
V19

TP27

CPU_PERF#
VRM_PWRGD_ICH

R615

B8
C13
D13
A13
B13
D9
C9

21,23 AC_BIT_CLK
23,24,25,31 AC_RST#
21,23 AC_DATA_IN0
21,25,31 AC_DATA_IN1
21,23,25,31 AC_SDATA_OUT
23,25,31 AC_SYNC

T2
R4
T4
U2
U3
U4
T5

5,37,39,41
LAD0
5,37,39,41
LAD1
5,37,39,41
LAD2
5,37,39,41
LAD3
21,37
LDRQ0#
21
LDRQ1#
5,37,39,41 LFRAME#

+3VALWAYS

34
34

USBP0+_5
USBP1+_5
TP23
TP24
USBP4+_5
USBP5+_5
USBP0-_5
USBP1-_5
TP26
TP92
USBP4-_5
USBP5-_5

R546
35
35
34
34

0
RP6
9
8
7
6

35
35

C20
A21
C18
A19
C16
A17
D20
B21
D18
B19
D16
B17

USBP2+_5
USBP3+_5

USBP2-_5
USBP3-_5

10

B15
C14
A15
B14
A14
D14

4
3
2
1
5
4

R616

18_1%

A23
B23

10K-10P8R

J20
G22
F20
G20
F21
H20
F23
H22
G23
H21
F22
E23

36 BACK_OFF#
32,35 BAY_IN0
32 BAY_IN1
6
CG_FS0
6
CG_FS1
6
CG_FS2
6
CG_FS5
6
CG_FS6
TP28
TP25
TP29
41

FWH_WP#

PM_GMUXSEL/GPIO23
PM_CPUPERF#/GPIO22
PM_VGATE/VRMPWRPGD
AC_BITCLK
AC_RST#
AC_SDIN0
AC_SDIN1
AC_SDIN2
AC_SDOUT
AC_SYNC

Geyserville

37 SUS_STAT#_3
4
PM_THRM#
TP93

CPU_STP#_3
SUSCLK_3

PM_AGPBUSY#/GPIO6
GPIO_7
PM_SYSRST#
GPIO_8
Unmuxed GPIO_12
PM_BATLOW#
GPIO
PM_C3_STAT#/GPIO21
GPIO_13
PM_CLKRUN#/GPIO24
GPIO_25
PM_DPRSLPVR
GPIO_27
PM_PWRBTN#
GPIO_28
PM_PWROK
Power
PM_RI#
IDE_PDCS1#
Management
PM_RSMRST#
IDE_PDCS3#
PM_SLP_S1#/GPIO19
IDE_SDCS1#
PM_SLP_S3#
IDE_SDCS3#
PM_SLP_S4#
PM_SLP_S5#
IDE_PDA0
PM_STPCPU#/GPIO20
IDE_PDA1
PM_STPPCI#/GPIO18
IDE_PDA2
PM_SUS_CLK
IDE_SDA0
PM_SUS_STAT#
IDE_SDA1
PM_THRM#
IDE_SDA2

AC'97
I/F

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#0
LPC_DRQ#1
LPC_FRAME#

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

LPC
I/F

USB_PP0
USB_PP1
USB_PP2
USB_PP3
USB_PP4
USB_PP5
USB_PN#0
USB_PN#1
USB_PN#2
USB_PN#3
USB_PN#4
USB_PN#5

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

USB
I/F

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5

IDE_PDDACK#
IDE_SDDACK#
IDE_PDDREQ
IDE_SDDREQ
IDE_PDIOR#
IDE_SDIOR#
IDE_PDIOW#
IDE_SDIOW#
IDE_PIORDY
IDE_SIORDY

USB_RBIAS
USB_RBIAS#
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
USB_GPIO42
GPIO43

Clocks

CLK_14
CLK_48
RTCRST#
CLK_RTCX1
CLK_RTCX2
CLK_VBIAS

Misc

SPKR
THRMTRIP#

R3
V4
V5
W3
V2
W1
W4

SCROLLOCK#_3
39
EXTSMI#_3 37,39
KBDSCI_3
39
P ORTDOCK_FDD_IN#
CB_SUSP#_ICH
27
OPMUTE# 24
XIDE_EN#_3
32

Y13
AB14
AB21
AC22

PDCS1#_3
PDCS3#_3
SDCS1#_3
SDCS3#_3

AA13
AB13
W13
AA20
AC20
AC21

PDA0_3
PDA1_3
PDA2_3
SDA0_3
SDA1_3
SDA2_3

AB11
AC11
Y10
AA10
AA7
AB8
Y8
AA8
AB9
Y9
AC9
W9
AB10
W10
W11
Y11

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

W17
AB17
W16
AC16
W15
AB15
W14
AA14
Y14
AC15
AA15
Y15
AB16
Y16
AA17
Y17

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

GPIO0 - 15 Input Only

GPIO16--21 Output Only

35

32
32
32
32
32
32
32
32
32
32

R180
1K
DPMS_CLK

SUSCLK_3

BSS138

NEAR_SB

R532
Y12
AB19
AA11
AB18
AC12
Y18
W12
AA18
AB12
AC19

PDDACK#_3
32
SDDACK#_3
32
PDDRQ_35
32
SDDRQ_35
32
PDIOR#_3
32
SDIOR#_3
32
PDIOW#_3
32
SDIOW#_3
32
PIORDY_35
32
SIORDY_35
32

J23
F19
W7
AC7
AC6
Y6

CLK_ICH14
CLK_ICH48
RTC_RST#

CPU_STP#_3

ASUS PROJECT:
A

REVISION

M2Ne

2.2

R565

PM_STPCPU#

DATE: Tuesday, January 06, 2004

SHEET
OF
19
56
B

44

X5
1
4

2
3
32.768K

6
6
36

SPKRICH_3

10M
C547

C542

15P

15P

RTC_VBIAS

H23
W20

36

21,23

R542

+VCCP

R543

R544

DESCRIPTION:
C

10M

R529

0_402
(0402)

Q37

56

ICH4-M Part B

+V1.5S

BAT_LLOW#_OC_ICH
TP11

21,26,29,31,37,39
CLKRUN#_3
44 PM_DPRSLPVR
22 PWRBTN#_RSM
22 SUSPWRGD_3
27
RIA#_3
22 RSMRST#_RSM

R2
Y3
AB2
T3
AC2
V20
AA1
AB6
Y1
AA6
W18
Y4
Y2
AA2
W19
Y21
AA4
AB3
V1

8,21 AGP_BUSY#
22 AUXPWROK

IDE

C3 STATE IS NOT
REQUIRED, USE
AS GPO

ICH4-M (2 of 4)

PM_THRMTRIP#

56

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

U50D
A1
A4
A16
A18
A20
A22
AA3
AA9
AA12
AA16
AA22
AB7
AB20
AC1
AC5
AC10
AC14
AC18
AC23
B9
B12
B16
B18
B20
B22
C6
C15
C17
C19
C21
C23
D1
D4
D8
D12
D15
D17
D19
D21
D22
D23
E10
E14
E16
E17
E18
E19
E21
E22
F8
G3
G6

+3VS
U50C

3216

E12
E13
E20
F14
G18
R6
T6
U6

CT5
4.7uF/10V

+V1.5ALWAYS

C229
0.1U
2

C242
0.1U

V CCLAN1.5 /3.3 may or may not

be powered in S3-S5

+5VS
+3VS

R187

1K

1
D24

+V1.5S

R185

F6
F7

+3VS

R189

E9
F9

VCCSUS1.5_0
VCCSUS1.5_1
VCCSUS1.5_2
VCCSUS1.5_3
VCCSUS1.5_4
VCCSUS1.5_5
VCCSUS1.5_6
VCCSUS1.5_7

VCC3.3_0
VCC3.3_1
VCC3.3_2
VCC3.3_3
VCC3.3_4
VCC3.3_5
VCC3.3_6
VCC3.3_7
VCC3.3_8
VCC3.3_9
VCC3.3_10
VCC3.3_11
VCC3.3_12
VCC3.3_13
VCC3.3_14
VCC3.3_15

VCCLAN1.5_0
VCCLAN1.5_1
VCCLAN3.3_0
VCCLAN3.3_1

POWER

C HK is it necessary (for LAN?)

2
1SS355
+3VALWAYS
+5VALWAYS
C230
1U

1
D25
R195

C231
0.1U
0402

E7
V6

+VCC5REF
2
1SS355
1K

E15
C250

0.1U
L23
M14
P18
T22

+V1.5S

VCC1.5_0
VCC1.5_1
VCC1.5_2
VCC1.5_3
VCC1.5_4
VCC1.5_5
VCC1.5_6
VCC1.5_7

VCC5REFSUS1
VCCHI_0
VCCHI_1
VCCHI_2
VCCHI_3

VCCRTC

C255
+V1.5S

R203

+V1.5S_PLL

C22

0.1U_402

VCC5REF1
VCC5REF2

+VCCP

R205

P14
U18
AA23

C247
1U

VCCPLL
VCCSUS3.3_0
VCCSUS3.3_1
VCCSUS3.3_2
VCCSUS3.3_3
VCCSUS3.3_4
VCCSUS3.3_5
VCCSUS3.3_6
VCCSUS3.3_7
VCCSUS3.3_8
VCCSUS3.3_9

VCC_CPU_IO_0
VCC_CPU_IO_1
VCC_CPU_IO_2

C262
0.1U

ICH4-M Part C

A5
B2
H6
H18
J1
J18
K6
M10
P6
P12
U1
V10
V16
V18
AC8
AC17

CT20
C236
0.1U

0805

C239
0.1U

C240
0.1U

C257
0.1U

10U_0805

+V1.5S

K10
K12
K18
K22
P10
T18
U19
V14

3528

CT6
22uF/10V

C246
0.1U

AB5

C258
0.1U

+RTCVCC
C226
0.1U

E11
F10
F15
F16
F18
K14
V7
V8
V9
F17

+3VALWAYS
CT18
0805

10U_0805

C241
0.1U

C235
0.1U

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51

VSS

VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101

G19
G21
H1
J6
K3
K11
K13
K19
K23
L10
L11
L12
L13
L14
L21
M1
M11
M12
M13
M20
M22
N5
N10
N11
N12
N13
N14
N19
N21
N23
P3
P11
P13
P20
P22
R5
R18
R21
T1
T19
T23
U20
V3
V15
V17
W5
W8
W22
Y7
Y19

ICH4-M Part D

+V1.5S_PLL

+V1.5S

C260
0.01U

C261
0.1U

C237
0.1U

C245
0.1U

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
20
56
B

DESCRIPTION:
C

ICH4-M (3 of 4)

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

PDD[0:15]

19,32 PDD[0:15]

SDD[0:15]

19,32 SDD[0:15]

RN66
1
3
5
7

19,23 AC_DATA_IN0
19,25,31 AC_DATA_IN1
19,23 AC_BIT_CLK

2
4
6
8

10K-8P4R_*
+3VS
+3VS

C259
7343

RN91
2
4
6
8

18,26,37,39 SERIRQ_3
18,26
REQ2#_3
18,31 INT_PIRQD#
18,26,29 INT_PIRQA#

1
3
5
7

18 PCPCI_REQA#_3
18,26,29,31 DEVSEL#_3
18 PCPCI_REQB#_3
18,31
REQ4#_3

2
4
6
8

1
3
5
7

C225
47P

7343

C256
0.1U

C238
0.1U

C251
47P

100U/2V_7343
18 SM_INTRUDER#

R184

100k

8.2K-8P4R
2

C224
0.1U

C221
+RTCVCC

RN9
2
4
6
8

C551
0.1U

+V1.5S

8.2K-8P4R

18,26 INT_PIRQB#
18
REQ0#_3
18,26,31 INT_PIRQC#
18,26,29,31 TRDY#_3

C228
0.1U

+
100U/6.3V_7343

+3VALWAYS
+3V

RN92
1
3
5
7

19 BAT_LLOW#_OC_ICH

R496

+3VALWAYS

10K
C564
0.1U

C553
0.1U

C244
0.1U

1206

C254
10U/10V

8.2K-8P4R
RN12
2
4
6
8

18,26,29,31 SERR#_3
18,26,29,31 PERR#_3
18
PLOCK#_3
18,26,29,31 IRDY#_3

1
3
5
7

+3VS
+RTCVCC

8.2K-8P4R
19,26,29,31,37,39

R513

CLKRUN#_3

10K
C227
0.1U

RN67

18
19,37
19
18,26,29,31

2
4
6
8

REQ3#_3
LDRQ0#
LDRQ1#
FRAME#_3

1
3
5
7

8.2K-8P4R
RN93
18
18
18
18

2
4
6
8

INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#

1
3
5
7
+3VS
8.2K-8P4R

R504

8,19 AGP_BUSY#
18,26,29,31
18,29
4

R182

STOP#_3
REQ1#_3

8.2K
8.2K
8.2K

18,32

IRQ14_3

18,32

IRQ15_3

R575
R500

PAR_3

19,23 SPKRICH_3

R606

1K_*

RA

AC_SDATA_OUT

R538

10K_*

RB

R188

1K_*

RC

R534

1K_*

RD

19,23,25,31

18 PCPCI_GNTA#_3

8.2K

R501
R552

18,26,29,31

10K

18

EEP_DOUT

100

ICH3M STRAPPING OPTIONS

Function
Default
Optional Override
RA

No Reboot

No Stuff

Stuff for No Reboot

RB

Safe Mode
Boot

No Stuff

Stuff for safe mode

RC

A16 swap
override

No Stuff

Stuff for A16 swap

override

RD

Reserved

No Stuff

Stuff

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
21
56
B

DESCRIPTION:
C

ICH4-M (4 of 4)

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+3VALWAYS_P

+3VALWAYS
R80

+5VS

+3VS

C101

Change from 100k to 47k

R42

C100
0.1U_*

1U
1

R88

47K
1

R96

RSMRST#_RSM

220K

Q19

C121
1U

ADD FOR RC-RESET

SW1

TP0610T

2
2

Q24
2N7002

U5A

14

220K

19

100K

C60

2
3
4

Q23

U5B

74HC14
7

RST_BTN#

4.7U/16V_C1206
1
2

S1

D1

G1

G2

D2

S2

74HC14
5

C135
0.01U

C103
DUAL_N_SC70-6P
220K

0.1U

R97

Q20

GND VCC

3
R103

AUXPWROK

19
+3VS

RESET#

SUSPWRGD_3

SUSB_DIS_3

R17
U5C
D13

VRM_PWRGD

24,49

19

ADM809
6,8,19

48

19,27,51

SUSB#_3

U5D

100K
1

CPU_VRON

44,50

1SS355_UMD2
C64
0.1U

74HC14

74HC14

PCIRSTNS#_3

39 PCIRST#_GATE

C140
1000P

26,29,39,43

Q28

1M

7SZ32_SC70-5P

Q29

IRLML5103

1
3

R102

U7

PCIRST#_3

16,18,23,26,29,31,32,37,39,41

+3VALWAYS_P

+3V

R48
1M

+3VALWAYS
3

2N7002

R79
+3VALWAYS
R62
U5E
10

19 PWRBTN#_RSM

11

12

74HC14

100K

U5F
13

100K

74HC14

D17

D18

3
2

OS#_OC
+3V

R668
1

2
RB715F_SOT323

+3VALWAYS_P

+5VS

C139
0.1U

R116

OPEN2MM
Q21

39 ANYKEY_RSM

Q120
2N7002

1M
LID_BOT#

C737
0.1U_*

43

RB715F_SOT323

(0402)

JP60

100K

PWRON#_3A

R760

0_402
3

42

2N7002
C156
0.1U

D19
1

LID_RSM#

18,36

1SS355_UMD2_*
5

2
Q30

PWRON#

42

2N7002
TP95

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
22
56
B

DESCRIPTION:
C

RESET SKT

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+5VS

+5VA
U36
MAX8863

+5V

L54

1
2
3

L_0805

SHDN#
GND
IN

+5VA

OUT

SET

C372

1000P
R342

MAX8863

100K/1%

C351
C345

0805

C344
0.1U

10U_0805

R350

C346
0.1U

0805

33.3K/1%

C361
0.1U

C98
0.1U

10U_0805

C99
0

R50
R315

22
22

19,21 AC_BIT_CLK

R46

56

25,31 AC_BIT_CLK_MO

R49

AC_RST#

19,21 AC_DATA_IN0
19,21,25,31 AC_SDATA_OUT

SPKRCB

C137
0.01U_402

C83

C129
0.1U_402

19,25,31

0.01U
L56

+5VA

10P_*

R326

R364
R362

CD-L_A
CD-R_A

C113

0.1U

C118

0.1U

C110

0.1U

C116

0.1U

12
13
23
24
18
20
14
15
16
17
21
22

4.7K
4.7K

25

0805

10U_0805

C69
0.1U

C91
0.1U

U6

SYNC
BIT_CLK
SDATA_OUT
SDATA_IN0
RESET#
DVDD1
DVDD2
DVSS1
DVSS2
AVDD1
AVDD2
AVSS1
AVSS2

0402

4.7K

25,31 MOD_PHONE
32
32

+3VS

22

0.1U_402

R68

L_0805

C377

10
6
5
8
11
1
9
4
7
25
38
26
42

0402

C115
19,21 SPKRICH_3

AC_SYNC

MIC_AC
0.33U

LINE_OUT_L
LINE_OUT_R
MONO_OUT
AFILT1
AFILT2
VREF
CAP1
CAP2

AC9721

XTL_IN
XTL_OUT

35
36
37
29
30
27
31
32

AC_SNDOUTL
AC_SNDOUTR

C356

1U

1206

0.1U

C133

R73

R93

R91

R90

C114

C120

0.001U

0.01U

4.7K

4.7K

4.7K

4.7K

0.1U

0.1U

C375

10U/10V

0.1U

C365

C89

C370

820P

820P

C379
1U/25V_C0805

AGND_A
STAC9721

19
28
33
34
39
41
47
48
40
43
44
45
46

C134

24
24

C364

2
3

CD_GND_REF
VREFOUT
CAP3
APOP
LNLVL_OUT_L
LNLVL_OUT_R
EAPD
SDATA_IN1
NC
NC
NC
CID0
CID1

C119

PC_BEEP
PHONE_IN
LINE_IN_L
LINE_IN_R
CD_L
CD_R
AUX_L
AUX_R
VIDEO_L
VIDEO_R
MIC1
MIC2

26

Q22
2N7002
0402

PCIRST#_3

16,18,22,26,29,31,32,37,39,41

L58

A G N D_A

R58

19,24,25,31

R37

A GND_A

X1_AC97

2
R363
32

CD_GND

CD_REF
R92

X1

X2_AC97
4

4
24.576MHz_CXSY-4

C117

4.7K

CD_GND

1M_*

C81
15P

C77
15P

0.1U

4.7K

24,25

ASUS PROJECT:
A

M2Ne

REVISION

2.2

VREFOUT

DATE: Tuesday, January 06, 2004

SHEET
OF
23
56
B

VREFOUT

DESCRIPTION:
C

AC9721

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

G AIN0
0
0
1
1
X

GAIN1
0
1
0
1
X

SE/BTL#
0
0
0
0
1

AV (V/V)
-2
-6
-12
-24
-1

+5VS

+5VAMP

+5VAMP_PVDD
L53

L_0805

+5VAMP

L24

L_0805
R298

C72

C389

0805

+5VAMP

10U_0805

R82
10K

47K_*

0805

C347
0.1U

10U_0805

R81
10K_*
GAIN0
+5VAMP

GAIN1
R99
0_*

U9

R98
0
INTSPKL+
C729

0.47U

23 AC_SNDOUTL

0.47U

R756

0.47U
C136

C122

INTSPKL-

10K

R757
10K

C123
0.47U

C124
0.47U

TPA0212

1
2
3
4
5
6
7
8
9
10
11
12

GAIN0
GAIN1

C125
0.47U

GND1
GAIN0
GAIN1
LOUT+
LLINEIN
LHPIN
PVDD1
RIN+
LOUTLIN+
BYPASS
GND2

GND3
RLINEIN
SHUTDOWN
ROUT+
RHPIN
VDD
PVDD2
HP/LINE
ROUTSE/BTL#
PCBEEP
GND4

R670
0_*

R671

24
23
22
21
20
19
18
17
16
15
14
13

C348

0.47U

R672

0
AC_RST# 19,23,25,31
OPMUTE#_SIO
37
OPMUTE# 19

0_*
INTSPKR+

C349

0.47U

C728
R755
INTSPKRSE/BTL#

R302
0

TPA0212_TSSOP24_227G

0.47U

AC_SNDOUTR

10K

23
2

R758
10K

120/400mA
L20
CN9

CP5
1
3
5
7
3

2
4
6
8

1
2
CN_2

C25
470P

120/400mA
L19

23,25 VREFOUT

R295
420/450mA

330P_8P4C_*
CN16
INTSPKR+

L_470/100M_0603

L63

INTSPKR-

L_470/100M_0603

L62

INTSPKL+

L_470/100M_0603

L61

INTSPKL-

L_470/100M_0603

L60

4
5
6

R303
2.2K

4_AJK

25

R277

MIC_IN

0_0805

1_AJK

3
4

C326
1000P

5-G
6_G

CONN_INT_AUD

C312
470P

R351

0_0805

R301

0_0805

CN13
5
4
3
6
2
1

C327
470P

5
4
3
6
2
1
AUDIO
JACK

MICJACK

AUD_GND

AOUTR

INTSPKL+
+5VAMP
+ 3528

4
S2

D1

C85

47U/10V
R327
10K

C74

DUAL_N_SC70-6P

100U/6.3V_EL_*
+

D2

C73

SE/BTL#
AOUTR_C

R339
R317

0
100

AOUTL_C

R314

100

AOUTL

C84

3_AJK

C373
47P

+ 3528

2N7002

2_AJK

100U/6.3V_EL_*

2.2U

G1

C385

22,49 SUSB_DIS_3

S1

0603

Q18

CN14

Q56
+

10M

(0603)

R346

G2

+12V

C352
47P

5
4
3
6
2
1

5
4
3
6
2
1
AUDIO
JACK

AUDJACK

AUD_GND
47U/10V

INTSPKR+

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
24
56
B

DESCRIPTION:
C

AUDIO AMP

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+5VA
L55

L_0805

C381
220P
U37

R337
23,24

R338

VREFOUT

75K

2.2K

IN+
OUT

C383
1U

C380

C382
100P_*

1U

INVDD
VSS
MAX4490_SC70-5P

+5VA_PMIC

C362
24

0.1U

R325

MIC_IN

R316

22K

2.2K
2

L22

C363

0805

C366

0805

220P

MIC_AC

10U_0805

23

R355

1K
MOD_PHONE

MDC CNT

23,31

+5VS
CN28

C626
0.1U
C627
0.1U

19,21,23,31
19,23,24,31

AC_SDATA_OUT
AC_RST#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
GND PAD1
GND PAD2
GND PAD3
GND PAD4
GND PAD5
GND PAD6

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

+3V
C628
R624

10K

R623

10K_*

0.1U

SLAVE
MASTER

R625
R626

+3V
+3VS

0
0

AC_SYNC
19,23,31
AC_DATA_IN1
19,21,31
4

AC_BIT_CLK_MO

23,31

31
32
33
34
35
36

CON-30P_MDC

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
25
56
B

DESCRIPTION:
C

MIC PRE. AMP.

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+3VS

C573 C572
0.01U 0.01U
C577
0805
C593 C592 C567
0.1U 0.1U 0.1U

C566
0.1U

L73

+3V
2

+3V
10U_0805

80/2A
+3V

C554

0805

0805
0_0805 0805

C210
0.01U

0.01U

H8
M8
H12
M12
F10
P12

18,29,31 AD[31:0]
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

P6
R6
T6
V6
W6
P7
R7
T7
R8
T8
V8
W8
R9
T9
V9
W9
V12
W12
P13
R13
T13
V13
W13
R14
V14
W14
T15
V15
W15
V16
W16
V17
R12
C/BE3#_3
V7
C/BE2#_3
R10
T12
C/BE1#_3
C/BE0#_3
T14
CB_IDSEL_J W 7

PAR_3
C/BE3#_3
C/BE2#_3
C/BE1#_3
C/BE0#_3

W5
V5
T10
V10
W10
R11
T11
V11
W11

18,21 REQ2#_3
18
GNT2#_3
18,21,29,31 FRAME#_3
18,21,29,31 IRDY#_3
18,21,29,31 TRDY#_3
18,21,29,31 DEVSEL#_3
18,21,29,31 STOP#_3
18,21,29,31 PERR#_3
18,21,29,31 SERR#_3
CB_GBRST#
CB_PCIRST#
6

T2
R5
T5

CLK_CBPCI

CLKRUN#_3

CB_PME#

W4
R1

R550 0

AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V

VCC_CORE18V
VCC_CORE18V
VCC_CORE18V
VCC_CORE18V
VCC_3V1
VCC_3V2
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
IDSEL

TPBIAS0
TPBN0
TPBP0
TPAN0
TPAP0
TPBIAS1
TPBN1
TPBP1
TPAN1
TPAP1
CPS
VREF
REXT
FIL0
XO
XI

D12
A13
B13
A12
B12

TPBIAS0
TPB0-_1
TPB0+_1
TPA0-_1
TPA0+_1

D10
A11
B11
A10
B10

AGND1
AGND2
AGND3
AGND4
AGND5
AGND6
AGND7
AGND8
AGND9
AGND10
AGND11
AGND12
AGND13
AGND14
AGND15
AGND16
HWSUSP#
RI_OUT

REQ#
GNT#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#

SPKROUT#
TEST
IRQ3
IRQ4
IRQ5
IRQ7
IRQ9-SIRQ
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15

GBRESET#
PCIRST#
PCICLK

TPB0-_1
TPB0+_1
TPA0-_1
TPA0+_1

CLKRUN#
PME#

INTA#
INTB#
INTC#
GND18
GND17
GND16
GND15
GND14
GND13
GND12
GND11

GND4
GND5
GND6
GND7
GND8
GND9
GND10

TP21
TP19
0

+3V

R 1 6 7 56/1%

R 1 6 8 5.1K/1%

R 1 6 6 56/1%

C211 270P

CPS

D14

C601
R573

A14

0.01U
10K/1%

C578

B16
A16

0.01U

XO_1394
XI_1394

B17
A17
E16
D16
E15
E12
D13
E13
E14
D11
E10
E9
D9
B9
A9
E11

C599
10P

R4

C619
10P

CB_SUSP#

P1

R526

P2

SPKRCB
R525
R592

V19
T1
U2
U1
V1
V2
W2
V3
W3
T4
V4

A5
D5
B6
E6
B7
M5
L1
L4
A6
D6
A7
D7
E7
M6
L2
L5

X7
XTAL-24.576MH z

RIC#_3

B2
C2
A3
E2
A4
B5
K5
H2
J5
M4
F6
K2
L6
H5
B3
M2
F7
J2

27
27
SPKRCB

100K
0

23

TP16
SERIRQ_3
TP18
TP12

18,21,37,39

1394_SCL
1394_SDA

N4
N5
N6
M1

TP15

W17
W18
V18

R582
R576
R583

0
0_*
0

M11
L11
K11
J11
H11
M10
L10
K10

INT_PIRQB#
INT_PIRQC#
INT_PIRQA#

18,21
18,21,31
18,21,29

(1394)

TP14

F12
F13
F14
F8
F9
E8
D8
F11
R2

R5C590-CSP277-V10_1

R562

VCC_3V5
VCC_3V6

BCADR25
BCADR24
BCADR23
BCADR22
BCADR21
BCADR20
BCADR19
BCADR18
BCADR17
BCADR16
BCADR15
BCADR14
BCADR13
BCADR12
BCADR11
BCADR10
BCADR9
BCADR8
BCADR7
BCADR6
BCADR5
BCADR4
BCADR3
BCADR2
BCADR1
BCADR0

ACADR25
ACADR24
ACADR23
ACADR22
ACADR21
ACADR20
ACADR19
ACADR18
ACADR17
ACADR16
ACADR15
ACADR14
ACADR13
ACADR12
ACADR11
ACADR10
ACADR9
ACADR8
ACADR7
ACADR6
ACADR5
ACADR4
ACADR3
ACADR2
ACADR1
ACADR0

BCDATA15
BCDATA14
BCDATA13
BCDATA12
BCDATA11
BCDATA10
BCDATA9
BCDATA8
BCDATA7
BCDATA6
BCDATA5
BCDATA4
BCDATA3
BCDATA2
BCDATA1
BCDATA0
BIORD#
BIOWR#
BOE#
BWE#
BCE2#
BCE1#
BREG#
BRESET
BWAIT#
BWP
BRDY
BBVD2
BBVD1
BVS2
BVS1
BCD2#
BCD1#
BINPACK#

ACDATA15
ACDATA14
ACDATA13
ACDATA12
ACDATA11
ACDATA10
ACDATA9
ACDATA8
ACDATA7
ACDATA6
ACDATA5
ACDATA4
ACDATA3
ACDATA2
ACDATA1
ACDATA0
AIORD#
AIOWR#
AOE#
AWE#
ACE2#
ACE1#
AREG#
ARESET
AWAIT#
AWP
ARDY
ABVD2
ABVD1
AVS2
AVS1
ACD2#
ACD1#
AINPACK#

BVCC5EN#
BVCC3EN#
BVPPEN0
BVPPEN1

AVPPEN1
AVPPEN0
AVCC3EN#
AVCC5EN#

H14
J18
J15
K18
K15
L18
L15
M19
M16
K16
K19
L14
M18
J16
N16
P18
N19
M15
J19
H15
H18
G14
G16
G19
F16
F19
P16
P14
R18
R15
T18
B18
C18
D18
R19
R16
T19
T16
U18
C19
D19
E19
N18
M14
N14
L16
P19
P15
F15
H19
G15
B19
L19
F18
E18
H16
N15
A18
U19
G18
P4
P5
N1
N2

R531
10K
R530
22,39,43 PCIRSTNS#_3

AD19/A25 28
AD17/A24 28
CFRAME#/A23 28
CTRDY#/A22 28
CDEVSEL#/A21 28
CSTOP#/A20 28
CBLOCK#/A19 5,28
RFU/A18 5,28
AD16/A17 28
R580

AD8/D15
RFU/D14
AD6/D13
AD4/D12
AD2/D11
AD31/D10
AD30/D9
AD28/D8
AD7/D7
AD5/D6
AD3/D5
AD1/D4
AD0/D3
RFU/D2
AD29/D1
AD27/D0

28
5,28
28
28
28
28
28
28
28
28
28
28
28
5,28
28
28

AD13/IORD# 28
AD15/IOWR# 28
AD11/OE# 28
CGNT#/WE# 28
AD10/CE2# 28
CBE0#/CE1# 28
CBE3#/REG# 28
CRST#/RESET 28
CSERR#/WAIT# 5,28
CLKRUN#/IOIS16# 5,28
CINT#/IREQ# 28
CAUDIO/SPKR_IN#/BVD2
5,28
CSTSCHG/STSCHG#/BVD1 28,43
CVS2
28
CVS1
28
CCD2#
28
CCD1#
28,43
CREQ#/INPACK#
28
AVPP1
AVPP0
AVCC3#
AVCC5#

27
27
27
27

RSV1
+3V

CB_PCIRST#

R528

CCLK/A16 28

CIRDY#/A15 28
CPERR#/A14 5,28
CPAR/A13 28
CBE2#/A12 28
AD12/A11 28
AD9/A10
28
AD14/A9
28
CBE1#/A8 28
AD18/A7
28
AD20/A6
28
AD21/A5
28
AD22/A4
28
AD23/A3
28
AD24/A2
28
AD25/A1
28
AD26/A0
28

C 5 7 1 0.1U
J8
K8
L8

PCIRST#_3

GND1
GND2
GND3

GND21
GND20
GND19

L12
K12
J12

0
CB_PME#

18,29,31 PME#

0_*
CB_GBRST#

10U_0805

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

R5C590-CSP277-V10_1

0.01U

J14
K14

CB_IDSEL_J

R539
18,22,23,32,37,41

C624

100

AD19

+3V

27
27
27
27

TP22

D15

B14

G1
G4
G6
F2
F5
E1
E4
D1
D4
F4
F1
E5
D2
G5
A2
B4
B1
C1
G2
H6
H4
H1
J4
J1
K4
K1

C209
0.33UF

C563
5P_*
H9
J9
K9
L9
M9
H10
J10

R 1 6 5 56/1%

R595

R545
100K_*

A15
B15
B8
A8

VCC_3V3
VCC_3V4

CARDBUS PORTION

C581

0.01U

VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V

4
2

C539

0.01U
J6
K6

PCI/1394_OHCI PORTION

P8
P9
P10
P11

+3V

C 6 0 3 0805

U53A
1

R 1 6 4 56/1%

19,21,29,31,37,39

C602
U53B

18,21,29,31
18,29,31
18,29,31
18,29,31
18,29,31

120/400mA

L72
120/400mA

10U_0805

C532
C540 C535
1 0 U _ 0 8 0 5 0.01U 0.01U

L71

0805
+V1.8

L76

R568
4.7K

U51
1
2
3
4

SA0
VCC
SA1 MODE/W#
SA2
SCL
GND
SDA
24C02(2.7V)

8
7
6
5

M2Ne

REVISION

DATE: Tuesday, January 06, 2004

2.2

SHEET
B

26

OF

DESCRIPTION:

CARDBUS RICON R5C590

56
C

SCHEMATIC FILE NAME : <Doc>

DESIGN ENGINEER :

LIBRARY DATE :
D

1394_SCL
1394_SDA
5

C730
2.2U_*
C538
1U

ASUS PROJECT:

R569
4.7K

U52
+VCCCB
+12V
9

VCC0
VCC1
VCC2

12V

+3V

13
12
11

0.1uF

C587
0.1uF

+VPPCB

+5V

VPP
C546
0.1uF

5V
5V
VCCD0#
VCCD1#
VPPD0
VPPD1

SHDN#

3.3V
3.3V
GND

C545
0.1uF

R541
10K

R527
10K

Q71

C586
0.1uF

+3V
3
4

10

OC#

1
2
15
14

R536

10K

R577

R578

AVCC3#
AVPP1
AVPP0

2N7002

26

26

RIC#_3

RIA#_3

19

Q69

16

TPS2211A
7

AVCC5#

26
26
26

5
6

+3VALWAYS

C583

R537

+3V

2N7002

10K

D37
2

5,43 CBDEBUGEN#

1SS355_UMD2
3

R153
R154
R155
R156
+3V

CN18

0_*
0_*
0_*
0_*

T41

R535
10K
4

26 CB_SUSP#

D38
SUSB#_3

CB_SUSP#
R533

CHA_GND0

19,22,51

TPA+
TPA-

CB_SUSP#_ICH

19

TPB+
6
7
8

RB717F_SOT323

CHA_GND1
7
8

TPB-

8
7
6
5

3
2

B1
B2
B3
B4

A1
A2
A3
A4

1
2
3
4

TPA0+_1
TPA0-_1
TPB0+_1
TPB0-_1

26
26
26
26

1
1394CHOKE

1394CON

ASUS PROJECT:
A

M2Ne

REVISION
2.2

DATE: Tuesday, January 06, 2004

SHEET
27
OF
56
B

DESCRIPTION:

SCHEMATIC FILE NAME : <Doc>

CARDBUS PowerSW & 1394 Slot LIBRARY DATE :

C

DESIGN ENGINEER :
E

CN23

26
26
26
26
26
26
26
26
26
26
26
26
5,26
26
26

AD0/D3
AD1/D4
AD3/D5
AD5/D6
AD7/D7
CBE0#/CE1#
AD9/A10
AD11/OE#
AD12/A11
AD14/A9
CBE1#/A8
CPAR/A13
CPERR#/A14
CGNT#/WE#
CINT#/IREQ#
+VCCCB
+VPPCB

26

CCLK/A16
26 CIRDY#/A15
26 CBE2#/A12
26 AD18/A7
26 AD20/A6
26 AD21/A5
26 AD22/A4
26 AD23/A3
26 AD24/A2
26 AD25/A1
26 AD26/A0
26 AD27/D0
26 AD29/D1
5,26 RFU/D2
5,26 CLKRUN#/IOIS16#

C562
5P_*

26,43

CCD1#

26
26
26
5,26
26
26
26
26
26
26
5,26
5,26
26
26

C222
220P

+VCCCB

+VCCCB
+VPPCB

R579
10K_*
26 CRST#/RESET

AD2/D11
AD4/D12
AD6/D13
RFU/D14
AD8/D15
AD10/CE2#
CVS1
AD13/IORD#
AD15/IOWR#
AD16/A17
RFU/A18
CBLOCK#/A19
CSTOP#/A20
CDEVSEL#/A21

26
26
26
26
26

CTRDY#/A22
CFRAME#/A23
AD17/A24
AD19/A25
CVS2

5,26 CSERR#/WAIT#
26 CREQ#/INPACK#
26 CBE3#/REG#
5,26 C A U D I O/SPKR_IN#/BVD2
26,43 C S T S CHG/STSCHG#/BVD1
26 AD28/D8
26 AD30/D9
26 AD31/D10
26 CCD2#

C263
220P

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

GND_01
AD0/D3
AD1/D4
AD3/D5
AD5/D6
AD7/D7
CBE0#/CE1#
AD9/A10
AD11/OE#
AD12/A11
AD14/A9
CBE1#/A8
PAR/A13
PERR#/A14
GNT#/WE#
INT#/IREQ#/READY
VCC1
VPP1
CCLK/A16
IRDY#/A15
CBE2#/A12
AD18/A7
AD20/A6
AD21/A5
AD22/A4
AD23/A3
AD24/A2
AD25/A1
AD26/A0
AD27/D0
AD29/D1
RFU/D2
CCLKRUN#/IOIS16#/WP
GND_02
GND_03
CCD1#/CD1#
AD2/D11
AD4/D12
AD6/D13
RFU/D14
AD8/D15
AD10/CE2#
CVS1/VS1#
AD13/IORD#
AD15/IOWR#
AD16/A17
RFU/A18
CBLOCK#/A19
STOP#/A20
DEVSEL#/A21
VCC2
VPP2
TRDY#/A22
FRAME#/A23
AD17/A24
AD19/A25
CVS2/VS2#
RST#/RESET
SERR#/WAIT#
REQ#/INPACK#
CBE3#/REG#
CAUDIO/SPKR#
CSTSCHG/STSCHG#
AD28/D8
AD30/D9
AD31/D10
CCD2#/CD2#
GND_04
GND_05
GND_06
GND
GND

CLOSE TO PCMCIA_CONNECTER

+VCCCB
C234
C232
0.1uF

C584
0.1uF

0805

10U_0805

+VPPCB
C243
C249
0.1uF

0805

10U_0805

CB_CONN

ASUS PROJECT:
A

M2Ne

REVISION
2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
28
56
B

DESCRIPTION:
C

CARDBUS CONN.

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

Q95

+3VALWAYS_P
80/2A_*

L23
1

120/400mA
2

+3VA_LAN
2

1206

Q97
2N7002

10K

C652
1

L52
120/400mA
1
2

+2.5V_LAN

+3V_LAN
+2.5VA_LAN

R27
2

+3V_LAN
AD[0:31]

+3V_LAN
For wake on
LAN use

EECS
EEDO
EEDI
EESK

TXD+
TXDRXIN+
RXIN-

RTL8101(L)

1
R25

VCTRL
RTT3
RTSET

55
52
53
54

58
AVDD2_5_1

59
70
75

48
94
VDD2_5_1
VDD2_5_2

5.6K 0603_*

R259

U32
EECS
EESK
EEDI
EEDO

EECS
EEDO
EEDI
EESK

1
2
3
4

93C46
CS
VCC
CLK
NC
DI
ORG
DO
GND

10K

C304
0.1U

8
7
6
5

93C46
72
71
68
67

TDP
TDN
RDP
RDN

56
63
65

RTSET

TDP
TDN
RDP
RDN

VCTRL

30
30
30
30
TP41

1
R29

2
5.6K
+5VS

61
60

X1_LAN
X2_LAN

X1
X2

R269
1K
57
74
64

R28

ISO#

PME#

ISO#

18,26,31

PME#
ISOLATE#
LWAKE

TP40

R284
15K

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

AVDD1
AVDD2
AVDD3

6
22
37
49
90
95
3

47
46
45
43
42
41
40
39
36
35
34
33
32
30
29
28
15
14
13
12
11
10
9
8
96
93
92
91
89
87
86
85

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

19,51

+5V

5.6K
1

C328
0.1U
2

SUSC#_3

0.1U

AD[0:31]

47,48

3
2

+3V_LAN

18,26,31

AC_APR_UC

R662

CT8
10U/10V_*

C61
0.1U
2

0.1U

100K

SI2301

C59
C126
0.1U

C70
0.1U

1
C112
0.1U
2

C102
0.1U
2

CB1
10U/10V
2

1206

2N7002

Q96

0805

L25

R661

+3V_LAN

+3V

18,22,23,32,37,41

PCIRSTNS#_3

R30
R41

38
27
17
84

CLK_LANPCI

97

18,21,26,31 DEVSEL#_3
18,21,26,31 FRAME#_3
18
GNT1#_3
REQ1#_3
AD20 18,21
18,21,26 INT_PIRQA#
18,21,26,31 IRDY#_3
18,21,26,31 TRDY#_3
18,21,26,31 PAR_3
18,21,26,31 PERR#_3
18,21,26,31 SERR#_3
18,21,26,31 STOP#_3
0_*

R65

100

21
18
82
83
98
80
19
20
24
25
26
23
81

U38

C/BE0#
C/BE1#
C/BE2#
C/BE3#

LED0
LED1
LED2

CLK
DEVSEL#
FRAME#
GNT#
REQ#
IDSEL
INTA#
IRDY#
TRDY#
PAR
PERR#
SERR#
STOP#
RST#

NC
ROMCS/OE#
CLKRUN#

78
77
76

TP44
TP42
TP43

69
51
50

TP39
R285

AC_RST#
AC_SYNC#
AC_DOUT#
AC_DIN#
AC_BCK#
INTB#
GPIO0
GPIO1

CLKRUN#_3

1
3
4
5
7
79

19,21,26,31,37,39

0
X1_LAN

X3

X2_LAN

4
25MHz_CXSY-4

C322
27P

100
99

C321
27P

2
16
31
44
88
62
66
73

22,39,43

PCIRST#_3

C/BE0#_3
C/BE1#_3
C/BE2#_3
C/BE3#_3

DGND0
DGND1
DGND2
DGND3
DGND4
AGND0
DGND1
DGND2

18,26,31
18,26,31
18,26,31
18,26,31

ASUS PROJECT:
A

M2Ne

REVISION
2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
29
56
B

DESCRIPTION:
C

LAN REALTEK 8101

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+3V_LAN

C315
0.1uF
C316

R272
0.1U_*
R271
50

R273
50

0_*
U1
YCL
PH163112

29
29

TDP
TDN

TDP
TDN

RDP
RDN

RDP
RDN

2
1
3
4
5

29
29

6
8
7

TDCT
TD+
TD-

TXCT
TX+
TX-

NC1
NC2

NC3
NC4

RD+
RDRDCT

RX+
RXRXCT

15
16
14

LAN_TX+
LAN_TX-

12
13
11
9
10

LAN_RX+
LAN_RX-

PH163112
R275
50

R274
50

C317
0.1U

R261
75/1%

R260
75/1%

C318
0.1U
LAN_CGND

A seperate float plane is

needed at least 2mm
between Gnd

R8
R7

0805
0805

0_0805
0_0805

CN3
35

LAN_TX-

LAN_TX-

LAN_TX+

L13 PLW3216C_*
2
1

CN_TX-

CN_TX+

35

LAN_TX+

35

LAN_RX-

LAN_RX-

L12
2

35

LAN_RX+

LAN_RX+

04020402 04020402
C308
10P_*
C309 C306 C307
10P_* 10P_*
LAN_CGND
10P_*
R250
75

R5
R6

PLW3216C_*
1
4

0805
0805

CN_TX+
CN_TXCN_RX+

8
7
6
5
4
3
2
1

CN_RXCN_RXCN_RX+

12
11
10
9

0_0805
0_0805

16_NC
15_NC
14_G
13_G

16
15
14
13

12
11
10
9

LAN_CON14
R249
75

L14
C296
1500P

8
7
6
5
4
3
2
1

CN12
L_0603

L15

L_0603

1
RING

TIP

RING_J
L16

L_0603

TIP_J

4
L17

L_0603

1
2
3
4

5
6

5_G
6_G
CONN_INT_MOD

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
30
56
B

DESCRIPTION:
C

LAN I/O

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

18,26,29

AD[0:31]

AD[0:31]

+3VS

CN19

18,21 INT_PIRQD#

CLK_MINIPCI

18,21

REQ4#_3
AD31
AD29
AD27
AD25

18,26,29

C/BE3#_3

AD23
AD21
AD19
AD17

18,26,29 C/BE2#_3
18,21,26,29 IRDY#_3
19,21,26,29,37,39
CLKRUN#_3
18,21,26,29 SERR#_3
3

18,21,26,29
18,26,29

PERR#_3
C/BE1#_3

AD14
AD12
AD10
AD8
AD7
AD5
AD3

+5VS

AD1
19,23,25

19,21,25

AC_SYNC

AC_DATA_IN1
+3V

R481

23,25 AC_BIT_CLK_MO
R159

MOD_PHONE

23,25 MOD_PHONE

0
10K_*

R482

1K

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125

TIP
LAN RESERVED
LAN RESERVED
LAN RESERVED
LAN RESERVED
LAN RESERVED
LAN RESERVED
LAN RESERVED
INTB#
3.3V
RESERVED
GROUND
CLK
GROUND
REQ#
3.3V
AD[31]
AD[29]
GROUND
AD[27]
AD[25]
RESERVED
C/BE[3]#
AD[23]
GROUND
AD[21]
AD[19]
GROUND
AD[17]
C/BE[2]#
IRDY#
3.3V
CLKRUN#
SERR#
GROUND
PERR#
C/BE[1]#
AD[14]
GROUND
AD[12]
AD[10]
GROUND
AD[08]
AD[07]
3.3V
AD[05]
RESERVED
AD[03]
5V
AD[01]
GROUND
AC_SYNC
AC_SDATA_IN
AC_BIT_CLK
AC_CODEC_ID1#
MOD_AUDIO_MON
AUDIO_GND
S_AUDIO_OUT
S_AUDIO_OGND
AUDIO_GND
RESERVED
VCC5A

RING
LAN RESERVED
LAN RESERVED
LAN RESERVED
LAN RESERVED
LAN RESERVED
LAN RESERVED
LAN RESERVED
5V
INTA#
RESERVED
3.3VAUX
RST#
3.3V
GNT#
GROUND
PME#
RESERVED
AD[30]
3.3V
AD[28]
AD[26]
AD[24]
IDSEL
GROUND
AD[22]
AD[20]
PAR
AD[18]
AD[16]
GROUND
FRAME#
TRDY#
STOP#
3.3V
DEVSEL#
GROUND
AD[15]
AD[13]
AD[11]
GROUND
AD[09]
C/BE[0]#
3.3V
AD[06]
AD[04]
AD[02]
AD[00]
RESERVED
RESERVED
GROUND
M66EN
AC_SDATA_OUT
AC_CODEC_ID0#
AC_RESET#
RESERVED
GROUND
S_AUDIO_IN
S_AUDIO_I GND
AUDIO_GND
MCPIACT#
3.3VAUX

PAD1

PAD2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

+5VS
INT_PIRQC#

18,21,26

+3V
PCIRST#_3

R158

18,22,23,32,37,41

GNT4#_3

18

PME#

18,26,29

PAR_3

18,21,26,29

AD30

R163

AD28
AD26
AD24
AD21

100

AD22
AD20
AD18
AD16

FRAME#_3 18,21,26,29
TRDY#_3
18,21,26,29
STOP#_3 18,21,26,29
DEVSEL#_3

18,21,26,29

AD15
AD13
AD11
AD9
C/BE0#_3

18,26,29

AD6
AD4
AD2
AD0

R160

0
R161

AC_SDATA_OUT
AC_RST#

R162

19,21,23,25

10K
1K

19,23,24,25

MOD_PHONE
4

+3V

126

CN124(MINI_PCI)

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
31
56
B

DESCRIPTION:
C

MiniPCI

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

D5

19

PDD[0:15]

IDE_PDACTIVE#

IDE_SDACTIVE#

42 IDE_ACTIVE#

PDD[0:15]

DAP202K
+3VS

+5VS
R294
C44
4.7K

19

PIORDY_35

+5VS

10K

0.1U
R312
16,18,22,23,26,29,31,37,39,41

5.6K

PCIRST#_3

U40

VCC

IDERST#_5

7SZ32_SC70-5P

+12VS
+5VS
2

IDERST#_5

D1
D2
D3
D4

+3VS

IDERST#_5S
R373

0_*

1
2
5
6

R570
100K

19
19

+5VS
Q72
5

SI3456
3

+5VDOCK
R590

100K

C561
0.1uF

0.1uF

NC7SZ08
R365

C598
0.1uF

10K

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46

PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

CSEL1
PDIAG
PDA2_3
PDCS3#_3

PDA2_3
19
PDCS3#_3 19

R296
470_*

XIDE_EN_12
R278

1SS355

100K

PDIOW#_3
PDIOR#_3

19 PDDACK#_3
18,21 IRQ14_3
19
PDA1_3
19
PDA0_3
19
PDCS1#_3

CN25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45_G 46_G
CN_44

Q75
2N7002

4 IDERST#_5S

C560

1
0.1uF

PDDRQ_35
PDIOW#_3
PDIOR#_3
PIORDY_35
PDDACK#_3
IRQ14_3
PDA1_3
PDA0_3
PDCS1#_3
IDE_PDACTIVE#

C565
1

U56

2
R591

D42
2

XIDE_EN#_3

PCIRST#_3

R548
10K

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45

PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

GND
3

19

C303
10U_0805

PDDRQ_35

PDDRQ_35

19

R279
0805

PIORDY_35

C585

XIDE_EN_12

Q115

2N7002_*

0_*

0.1uF
3

+3V

C568
0.1U

+3VS

C570
0.1U
+5VDOCK

C552
R179

R193

10K
39

10K

R761
0805

R197
10K

19

BAY_IN0
BAY_IN1

19,35 BAY_IN0
19,35 BAY_IN1

C580
10U_0805

C223

C248

C252

0.1uF

0.1uF

0.1uF
R762

0_402

SDD1
SDD0
SDIOW#_3
SIORDY_35_MOS

SDIOW#_3

18,21

IRQ15_3

19
19
19

SDA1_3
SDA0_3
SDCS1#_3
CSEL1

R551

SDA1_3
SDA0_3
SDCS1#_3
IDE_SDACTIVE#_MOS
0

(0402)
4

FLP_INDEX#

35,37 FLP_INDEX#

XIDE_EN_12

B AY DEVICE DETECT
DEVICE

BAY_IN1

BAY_IN0

HDD

FDD
CD_ROM

Q116
3
2
+3VS

35,37 FLP_TRK0#
35,37 FLP_WP#
35,37 FLP_RDATA#
35,37 FLP_HDSEL#

DUAL_N_SC70-6P_*

D2

S2

G1

G2

S1

D1

4
5
6

23
23

R574
19
19
5

19

SDD[0:15]
SIORDY_35
SDDRQ_35

R555

(0402)

0805

CN24

4.7K

10U_0805

DOCK_IN#

DOCK_IN#

0_402

CD_GND
CD-L_A

FLP_TRK0#
FLP_WP#
FLP_RDATA#
FLP_HDSEL#
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
IDERST#_5S
CD_GND
CD-L_A

SDD[0:15]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61

4.7K

R596

SIORDY_35

R763

0_402
(0402)

SDDREQ_35

10K

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

61_G

62_G

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

SDDREQ_35
SDIOR#_3
SDDACK#_3

SDIOR#_3 19
SDDACK#_3
19

SDA2_3
SDCS3#_3
FLP_DR0#

SDA2_3 19
SDCS3#_3 19
FLP_DR0# 35,37

FLP_DSKCHG#
BAY_IN0
FLP_DRATE0
FLP_MTR0#
3MODE#
FLP_DIR#
BAY_IN1
FLP_STEP#
DOCK_IN#
FLP_WDATA#
FLP_WGATE#
SDD15
SDD14
SDD13
SDD12
SDD11
SDD10
SDD9
SDD8
CD_GND
CD-R_A

FLP_DSKCHG#

35,37

FLP_DRATE0
37
FLP_MTR0# 35,37
3MODE# 35
FLP_DIR#
35,37
FLP_STEP#
FLP_WDATA#

35,37

FLP_WGATE#

35,37

CD-R_A

23

62

CONN60_BAY

R597
10K

IDE_SDACTIVE#
5

R564
5.6K

PROJECT:
A

M2Ne

REVISION
2.2

35,37

DATE:
SHEET
B

Tuesday, January 06, 2004

32
OF
56

DESCRIPTION:
C

HDD & BAY CON

SCHEMATIC FILE NAME :

DESIGN ENGINEER :

LIBRARY DATE :
D

+3VALWAYS

+3VALWAYS
+5VS

+3VS
+3VS

R469
R468
R467

R459

NOTE:
ICH4 ==>+3VALWAYS
THERMAL SENSOR ==>+3VS

10K
2.2K
10K

2.2K
Q64

18

SMBCK_ICH

4,6,7,14

SMBDA_3S

D1

S1

G2

G1

S2

D2

SMBCK_3S

4,6,7,14

2
3

SMBDA_ICH

18

DUAL_N_SC70-6P

+3VALWAYS_P

+3VALWAYS_P

22,29,36,42,43,49

+3VALWAYS

+3VALWAYS

16,18,19,20,21,22,27,39,49

+5VALWAYS

+5VALWAYS

20,49

+V1.5ALWAYS

14

U54D
74LVC08

12

11

+3V

1 8 , 2 1,22,25,26,27,29,31,32,37,39,40,43,49,51

+5V

+5V

5,23,27,29,34,35,39,43,47,51

+12V

+12V

24,27,51

+3VS

+3VS

4 , 5 , 6 , 7 , 8 , 1 0 , 1 4 ,17,20,21,22,23,25,26,31,32,35,36,37,38,39,40,41,43,51

+5VS

+5VS

4 , 5 , 1 1 , 1 6 ,20,22,23,24,25,29,31,32,35,37,38,39,42,43,48,51

+12VS

16,17,32,35,51

+VCORE

+VCORE

2,3,39,44

+VCCP

+VCCP

1,2,3,5,9,10,11,18,19,20,50

+V2.5

+V2.5

3,8,10,11,12,13,14,49,50

+V1.8S

+V1.8S

2,51

+V1.5S

+V1.5S

2,8,10,11,16,18,19,20,21,51

+V1.2S

+V1.2S

3,9,10,11,50

+1.25VREF

+1.25VREFR

+RTCVCC

+RTCVCC

20,21,36

+5VA

+5VA

23,25

+V1.8

+V1.8

26,49

+VCCCB

27,28

+VPPCB

+VPPCB

27,28

+3V_LAN

+3V_LAN

29,30

+VCCCB

13

20,49

+3V

+12VS

+V1.5ALWAYS

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
33
56
B

DESCRIPTION:
C

SM_BUS

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+5V_USB

C12
0.1U

CN6
L47
19
19

USBP0-_5

USBP0+_5

1
2
3
4
5
6

C297
PLW3216C_*
2

R255

R254

0.1uF_*

C302
0.1uF_*

CON4(USB1)

+5V
F1
L46

L_0805

+5V_USB

FUSE_1.5A
+ C645
+ C18

100U/6.3V_EL

100U/6.3V_EL

+5V_USB

C13
0.1U

CN7
L48
4

19

USBP1-_5

19

USBP1+_5

3
2

1
2
3
4
5
6

C298
PLW3216C_*
R257
0
0.1uF_*
R256

C299
0.1uF_*

CON4(USB1)

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
34
56
B

DESCRIPTION:
C

3*USB2.0 Conn.

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

R233

+3VS

(0402)
1

+5VS
1

+5VS
DOCK_VIN_P

0_402_*

R3
100K

C4
1
3
5
7

C5

R2
10U/16V_C3528

RN13

0.1U

C3

2.7K_8P4R
2.7K
CONN68_PR2

0.1U

M TR0#_35 IS RESERVED,
NOT USE IN PORTDOCK

32,37 FLP_TRK0#
32,37 FLP_WDATA#
32,37 FLP_DIR#
19
USBP5-_5

USBP5-_5
FLP_MTR0#

39
KBDCLK_5
30 LAN_TX+
30 LAN_RX+
16 PD_SWVGA
37,38 LPT_PD0_3
37,38 LPT_PD2_3
37,38 LPT_PD5_3
37,38 LPT_BUSY/WAIT#_3
16
VSYNC_Q
16
PD_G

R234
(0402)

0_402

R238

32 3MODE#
32,37 FLP_HDSEL#
37 FLP_DSL
19
USBP4-_5

R242
USBP4-_5
+5VS

19

0_*

USBP4+_5
MT_DR0#_35

USBP4+_5

37,38 LPT_PE_3
37,38 LPT_PD6_3
37,38 LPT_SLIN#/ASB#_3
37,38 LPT_ERR#_3
+12VS
+5V
3

16
32,37 FLP_MTR0#

HSYNC_Q
PD_R

R239

FLP_MTR0#
FLP_MTR0#_EN

R1
R4

0_*
0

33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35

33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
67
65
63
61
59
57
55
53
51
49
47
45
43
41
39
37
35

FLP_WGATE#
32,37
FLP_STEP#
32,37
USBP5+_5 19
P ORTDOCK_FDD_IN#
KBDDATA_5
39

USBP5+_5

19
2

LAN_TX30
LAN_RX30
LPT_STB#/WR#_3
37,38
LPT_PD1_3 37,38
LPT_PD3_3 37,38
LPT_PD7_3 37,38
DDC2BD_Q

16

FLP_RDATA#
32,37
FLP_WP# 32,37
+5VS
+5VS
ACK#_3
PD4_3
INIT#_3
AFD#/DSB#_3
SLCT_3
+5V
R240

FLP_DSKCHG#
32,37
FLP_INDEX#
32,37
LPT_ACK#_3 37,38
LPT_PD4_3 37,38
LPT_INIT#_3
37,38
LPT_AFD#/DSB#_3
37,38
LPT_SLCT_3 37,38
3

DDC2BC_Q
16
PD_B
16

69
70
71
72

16

34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36

69
70
71
72

2
4
6
8

CN4
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
68
66
64
62
60
58
56
54
52
50
48
46
44
42
40
38
36

F O R PortDockI, MTR0#35 short to

D R 0#_35 at Top_Brd of PortDock

N o t e: pin 40, 35 reserve for AGND_V (VGA GND),

f or S1A project, using GND only

B A Y DEVICE DETECT

+5VS
67

65

37

68

38

66
33

36
3

32

C300

BAY_IN1

BAY_IN0

HDD

FDD
CD_ROM

1
2

0.1U
5

34

31

35

DEVICE

U28
+3VS

Top View

19,32 BAY_IN0

VCC
4

BAY_FDD_IN#

2
GND
3

ASUS PROJECT:
A

32

4
NC7SZ14P5
3

32,37 FLP_DR0#

2
Q42

REVISION

M2Ne

BAY_IN1

R236
10K
1

5
5

The funtion difference between

Port-DockI / Port Dock II:
1. PDI w/ COM, 2xPS2, wo/ Lan
2. PDII w/ 2xUSB, Lan, 1xPS2

1
2

R237
10K

7SZ32_SC70-5P

U30

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
56
35
B

DESCRIPTION:
C

PORT BARII

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

FLP_MTR0#_EN
5

2N7002

DESIGN ENGINEER :
E

+3VS

+2.5VREF

AC_BAT_SYS

D26
2

19 BACK_OFF#

L11
R226
470/450mA
10K_402

L42
400/2A

1SS355
1

CN5

TP33

TP32

TP31

TP30

CT7
10uF/35V_*

0805

(0402)

3528

C287
0.1U

DOCK_VIN_P

VCC_INV

1
2
3
4
5
6
7

CN8

3
NP_NC
5
6

1
L9

A/D_DOCK_IN

4532

A/D_DOCK_IN

35,47

8 LCD_ENBACK

18,22 LID_RSM#

L40
1

PWM_L
0402

3
4
5
6

470/450mA
2

C284
0.1U

C7
0.1U_402

C8
0402

0402

0402

CN-4_DC

C289
1U/50V_1206

C281
0.1U

48

PWM

L10
1

420/450mA
2

0.1U_402

C6

0402

C727
TP38

TP37

TP36

INVERTOR

C10
0.1U_402

0.1U_402

0805

TP35

C9
0.1U_402

8
9

L41

0_0805

RB717F

0805

D27

10U_0805

+RTCVCC

+3VALWAYS_P

C170

D20
1

TOP_VIEW

2
RB751

1U

TP96
TP97
4

R129

D21
1

R145

180K

RTC_RST#

19

RB751V

CN17
2

1K

C177

0.1U

CON2(RTC)

C160

0.047U

RTC_VBIAS

19

ASUS PROJECT:
A

M2Ne

REVISION
2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
36
56
B

DESCRIPTION:
C

LCD,DCIN&RTC_Con.

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+3VS

14
39
63
88
VDD
VDD
VDD
VDD

CLK_SIOPCI

8
9
12
11
7
6
10
19

R306

PCIRST#_3

19,41 LFRAME#
19,21
LDRQ0#
19 SUS_STAT#_3
19,21,26,29,31,39
CLKRUN#_3
18,21,26,39
SERIRQ_3
R290
0

19,39 EXTSMI#_3

6
32,35
32,35
32,35
32,35
32,35
32,35
32,35
32,35
32,35
32,35
32,35
32,35
35
32

20

CLK_SIO14

21
22
23
24
25
26
27
28
29
30
31
32
33
34

FLP_DSKCHG#
FLP_HDSEL#
FLP_RDATA#
FLP_WP#
FLP_TRK0#
FLP_WGATE#
FLP_WDATA#
FLP_STEP#
FLP_DIR#
FLP_DR0#
FLP_MTR0#
FLP_INDEX#
FLP_DSL
FLP_DRATE0
PCB_VID0
PCB_VID1
PCB_VID2

40 KEYDETECT1
40 KEYDETECT2
40,48 CHG_FULL#
17
PID0
17
PID1

XCNF2

R333
R675

10K
0
PID0
PID1
PID2

R335

10K_402
(0402)
(0402)

PC87393

CLKIN
DSKCHG#
HDSEL#
RDATA#
WP#
TRK0#
WGATE#
WDATA#
SETP#
DIR#
DR0#
MTR0#
INDEX#
DENSEL
DRATE0/IRSL2

PNF/XRDY
SLCT/WGATE#
PE/WDATA#
BUSY_WAIT#/MTR1#
ACK#/DR1#
SLIN#_ASTRB#/STEP#
INIT#/DIR#
ERR#/HDSEL#
AFD#_DSTRB#/DENSEL
STB#_WRITE#
DCD1#
DSR1#
SIN1
RTS1#/TEST
SOUT1/XCNF0
CTS1#
DTR1#_BOUT1/BADDR
RI1#

XA0/GPIO20
XA1/GPIO21
XA2/GPIO22
XA3/GPIO23
XA4/GPIO24/XSTB0#
XA5/XSTB1#/XCNF2
XA6/GPIO26/PRIQA/XSTB2#
XA7/GPIO27/PIRQB
XA8/GPIO30/PIRQC
XA9/GPIO31/MTR1#/PIRQD
XA10/GPIO32/XIORD#/MDRX
XA11/GPIO33/XIOWR#/MDTX
XA12/GPIO10/JOYABTN1/RI2#
XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2
XA14/GPIO12/JOYAY/CTS2#
XA15/GPIO13/JOYBY/SOUT2
XA16/GPIO14/JOYBX/RTS2#
XA17/GPIO15/JOYAX/SIN2
XA18/GPIO16/JOYBBTN0/DSR2#
XA19/DCD2#/JOYABTN0/GPIO17

10K_402

IRTX
IRRX1
IRRX2_IRSL0
IRSL1
IRSL3/PWUREQ#
XD0/GPIO00/JOYABTN1
XD1/GPIO01/JOYBBTN1
XD2/GPIO02/JOYAY
XD3/GPIO03/JOYBY
XD4/GPIO04/JOYBX
XD5/GPIO05/JOYAX
XD6/GPIO06/JOYBBTN0
XD7/GPIO07/JOYABTN0
XWR#/XCNF1
XRD#/GPIO34/WDO#
XIOWR#/XCS1#/MTR1#/DRATE0
XIORD#/GPIO37/IRSL2/DR1#
XCS0#/DR1#/XDRY/GPIO25

52
50
48
46
45
44
43
42

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

35
36
37
40
41
47
49
51
53
54

LPT_PNF_3
R263

10K

BUSY/WAIT#
ACK#
SLIN#/ASB#

10K_402

(0402)

PC87393_0

1
3
5
7

2
4
6
8

LPT_AFD#/DSB#_3
LPT_PD0_3 35,38
LPT_PD1_3 35,38
LPT_PD2_3 35,38

R268

33_8P4R

38

35,38
35,38
LPT_STB#/WR#_3

33

35,38

+5VS

+3VS

+3VS
XCNF0
D29
R304
10K

70
69
68
67
66

IRTXD_3
IRRXD_3
IR_SEL

3
2
1
100
99
98
97
96
4
5
73
71
72

35,38

+3VS
LPT_SLCT_3 35,38
LPT_PE_3 35,38

LPT_INIT#_3
LPT_ERR#_3

AFD#/DSB#

55
56
57
58
59
60
61
62

RN17
AFD#/DSB#
PD0
PD1
PD2

38
38
38

D30
1SS355_*

1SS355
RP4
5

TP46
TP48

LPT_SLIN#/ASB#_3
LPT_PD3_3
LPT_PD4_3
LPT_PD5_3

1
2
3
4

LPT_PD1_3
LPT_PD0_3
LPT_STB#/WR#_3
LPT_PD2_3

6
7
8
9

10
OPMUTE#_SIO

TP51
TP52
TP49
TP53
TP55

24

1K_10P8R

MEMW#_3
MEMR#_3
TP50

RP3

TP45

VSS
VSS
VSS
VSS

+3VS

R348
R331

+3V

40,43
802_ON#
39,40,47 ACIN_OC
39,40,47 BAT_IN#_OC
4,39 FAN_SPD

R332

95
94
93
92
91
90
87
86
85
84
83
82
81
80
79
78
77
76
75
74

LCLK
LRESET#
LFRAME#
LDRQ#
LPCPD#
CLKRUN#/GPIO36
SERIRQ
SMI#/GPIO35

PD0/INDEX#
PD1/TRK0#
PD2/WP#
PD3/RDATA#
PD4/DSKCHG#
PD5/MSEN0
PD6/DRATE0
PD7/MSEN1

LPT_PD6_3
LPT_PD7_3
LPT_ACK#_3
LPT_BUSY/WAIT#_3

1
2
3
4

LPT_PE_3
LPT_INIT#_3
LPT_ERR#_3
LPT_AFD#/DSB#_3

6
7
8
9

10

13
38
64
89

16,18,22,23,26,29,31,32,39,41

LAD0
LAD1
LAD2
LAD3

15
16
17
18

LPT_SLIN#/ASB#_3
35,38
LPT_PD3_3 35,38
LPT_PD4_3 35,38
LPT_PD5_3 35,38
LPT_PD6_3 35,38
LPT_PD7_3 35,38
LPT_ACK#_3 35,38
LPT_BUSY/WAIT#_3
35,38

LAD0
LAD1
LAD2
LAD3

5,19,39,41
5,19,39,41
5,19,39,41
5,19,39,41

33_8P4R
2
4
6
8
2
4
6
8
33_8P4R

U33

RN16
1
3
5
7
1
3
5
7
RN15

SLIN#/ASB#
PD3
PD4
PD5
PD6
PD7
ACK#
BUSY/WAIT#

4.7K_10P8R
LPT_SLCT_3

R264

4.7K

+3VS
+3VS
MEMDEF3
MEMDEF2
MEMDEF1
MEMDEF0

R742
R743
R744
R745

10K
22K_*
22K_*
10K

+3VS
PCB_VID0
PCB_VID1
PCB_VID2

R352
R353
R354

10K
10K
10K_*

+3VS
C334

R746
10K_*

R747
10K

R748
10K

R749
10K_*

R330
10K

R329
10K_*

R328
10K_*

MEMR#_3

R308

1K

XCNF0

R20

1K_*

R307

10K_*

R359

10K

(XCNF1) MEMW#_3

XCNF2

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
56
37
B

DESCRIPTION:
C

SUPER I/O

0805

10U_0805

C336
0.1U

C30
0.1U

C335
0.1U

C376
0.1U

SCHEMATIC FILE NAME : VCORE.SCH

LIBRARY DATE :
D

DESIGN ENGINEER :
E

PARALLEL PORT
LPT_STB#/WR#_3
LPT_PD0_3
LPT_PD1_3
LPT_PD2_3

L35
L3
L32
L5

1
1
1
1

2
2
2
2

0
0
0
0

35,37
35,37
35,37
35,37

LPT_AFD#/DSB#_3
LPT_ERR#_3
LPT_INIT#_3
LPT_PD3_3

L7
L31
L4
L34

1
1
1
1

2
2
2
2

0
0
0
0

1
L33

35,37 LPT_SLIN#/ASB#_3

35,37
35,37
35,37
35,37

L6
L1
L29
L30

LPT_PD4_3
LPT_PD5_3
LPT_PD6_3
LPT_PD7_3

1
L2

35,37 LPT_ACK#_3

L8
L37
L38
L39

1
1
1
1

1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13

2
2
2
2

0
0
0
0

2
0
2
2
2
2

0
0
0
0

1
3
5
7

1
3
5
7

1
3
5
7

2
4
6
8

2
4
6
8

2
4
6
8

7
5
3
1
L36

8
6
4
2

26

35,37 LPT_BUSY/WAIT#_3
37 LPT_PNF_3
35,37 LPT_PE_3
35,37 LPT_SLCT_3

PRNCONN

1
1
1
1

27

CN2
35,37
35,37
35,37
35,37

CP4
150P_8P4C

CP2
150P_8P4C

0_0805

GND_PRT

0805

C2
C1
150P 150P

+5VS

CP3
CP1
150P_8P4C
150P_8P4C

+3VS
0805

0805

L70

L69

IRDA--HP3600

80/2A

80/2A_*

IRVDD

R480
C485

1206

IR_LEDA

2.7_1206

0805

TRACE = 40 MIL

37

IRTXD_3

37

IRRXD_3

37

IR_SEL

TXD

C491
470P

HSDL-3600

LEDA

U19

10

10U_0805

RXD
FIR_SEL

NC

4
5

VCC
1

11
7
2

SHLD
GND
AGND

MD0
MD1

TRACE = 40 MIL
IRVDD
5

C206
0.47uF

ASUS PROJECT:
A

M2Ne

REVISION

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
38
56
B

DESCRIPTION:
C

LPT & IR

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
Julian Kuo
E

+3V
+3VALWAYS

+3V
RP5
R488

BAT_IN#_OC
ACIN_OC

8.2K

ANYKEY_RSM

+3VS
5

RN11
2
4
6
8

KSI1
KSI0
KSI3
KSI2

1
3
5
7

1
2
3
4

47K_8P4R

KSI4
KSI5
KSI6
KSI7

19,37 EXTSMI#_3

6
7
8
9

Q66

R497
10K_*

10

+3V

2N7002
10K_10P8R
1

EXTSMI_3
C528

C519

0.1U

R503

0.1U

U48

10K

18,22,23,32,37,41

PCIRST#_3

47

BAT_LEARN

18,21,26,37 SERIRQ_3
6 0 CLK_KBCPCI
R516
19,41 LFRAME#
5,19,37,41 LAD3
5,19,37,41 LAD2
5,19,37,41 LAD1
5,19,37,41 LAD0

63
64
65
66
67
68
69
70

R51943 MSK_INSTKEY#
0

35
36
37
38

R518

100K

22 ANYKEY_RSM
4
WATCHDOG
43 SWDJ_EN#

19,21,26,29,31,37
19,40,47
48

KBDCPURST_3Q
A20GATE_3Q
KBDSCI_3Q
R491

CLKRUN#_3

0_*
R490
R487

+3V

BAT_LLOW#_OC

10K
0

HDQ
+3V

R489

TP82
32
DOCK_IN#
37,40,47 BAT_IN#_OC
4
FAN_DA1
43
SWDJ_LED

10K

4,37 FAN_SPD
40,42 BAT_SAVING

R502

+VCORE

35

KBDCLK_5

43
35

INTCLK_TP
KBDDATA_5

43
R492
100K

R495
100K

INTDATA_TP
R494

+5VS

0_402
(0402)

37,40,47 ACIN_OC
40,42
AP1#_3
40,42
AP0#_3
40,42 INTERNET#_3
40,42 EMAIL#_3

+3V

TP84

KBDCLK_5
MOUSECLK_5

TP81

KBDDATA_5
MOUSEDATA_5

KBDSCI_3

(0402)
R493 10K_402

74
75
76
77
78
79
80
1
4
5
6
7
8
9

VCC

R515
10K

VREF

R514

72
0_402_*

P27
P26
P25
P24

P23
P22
P21
P20

P17/KSO15
P16/KOS14
P15/KSO13
P14/KSO12
P13/KSO11
P12/KSO10
P11/KSO9
P10/KSO8
P07/KSO7
P06/KSO6
P05/KSO5
P04/KSO4
P03/KSO3
P02/KSO2
P01/KSO1
P00/KSO0

P42/INT0
P43/INT1
P44/RXD
P45/TXD
P46/SCLK1
P47/SRDY1#/CLKRUN#
P50/INT5
P51/INT20
P52/INT30/1-WIRE1
P53/INT40/1-WIRE2
P54/CNTR0
P55/CNTR1
P56/DA1/PWM01
P57/DA2/PWM11
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0

71

P37/KSI8
P36/KSI7
P35/KSI6
P34/KSI5
P33/KSI4
P32/KSI3
P31/PWM10/KSI2
P30/PWM00/KSI0
XIN
XOUT

P75/INT41
P74/INT31
P73/INT21
P72
P71
P70

P40/XCOUT
P41/XCIN
RESET#

P77/SCL
P76/SDA

CNVSS
VSS
AVSS

31
32
33
34

10K

R669

SCROLLOCK#_3
KBNUM_3
42
KBCAP_3
42
PCIRST#_GATE

(0402)

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62

25

40
40
40
40
40
40
40
40
40
40
40
40
40,43
40
40
40

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

40,43
40,43
40,43
40,43
40,43
40,43
40
40

EXTSMI_3
EMAIL_LED#
PCIRSTNS#_3

43
22,26,29,43

24
30
73
R509

1M_*

X4
2N7002

Q65
+5VS
1

C1

RN10

+5V
18

22

KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSO6
KSO5
KSO4
KSO3
KSO2
KSO1
KSO0

X1_KBC
X2_KBC

28
29
27
26

19

KSI7
KSI6
KSI5
KSI4
KSI3
KSI2
KSI1
KSI0

M3885XHP

(0402)

KBDSCI_3Q

17
16
15
14
13
12
11
10

(Keyboard Detect1)
2
TP83
3
TP80
(Keyboard Detect2)

10K_402

19

23
22
21
20
19
18

P87/SERIRQ
P86/LCLK
P85/LRESET#
P84/LFRAME#
P83/LAD3
P82/LAD2
P81/LAD1
P80/LAD0

A20GATE_3

3
Q68

1
3
5
7

MOUSEDATA_5
KBDDATA_5
MOUSECLK_5
KBDCLK_5

C507

20P_*

20P_*

10K_8P4R

2N7002

2
4
6
8

A20GATE_3Q

C2 RESOR-8MHZ

C508

+5VS

18 KBDCPURST_3

2N7002

ASUS PROJECT:
A

KBDCPURST_3Q

Q67

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
39
56
B

DESCRIPTION:
C

KeyBoard Controller

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+3VS

Key Board Connector

CN20
R483
10K

25
26
27
28

37 KEYDETECT1

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

R484
10K

37 KEYDETECT2

NC
NC
NC
NC

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

5
6
8
9
10
11
14
15

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

1
2
3
4
7
12
13
16
17
18
19
20
21
22
23
24

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

39
39
39,43
39,43
39,43
39,43
39,43
39,43

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

39
39
39
39,43
39
39
39
39
39
39
39
39
39
39
39
39

CN-28_KB(M2)

P54,P55 are wake-up event inputs when KBC in sta ndby mode
+3VS

10

+3V

RP1
10K_10P8R
R349
10K

6
7
8
9

1
2
3
4
5

R334
47K

Input event only at P54,P55,P60-P 67

39,42
39,42
39,42
39,42
37,39,47
39,42
37,39,47
19,39,47
37,43

+3V

AP0#_3
AP1#_3
BAT_SAVING
INTERNET#_3
ACIN_OC
EMAIL#_3
BAT_IN#_OC
BAT_LLOW#_OC
802_ON#

37,48 CHG_FULL#

PROJECT:
A

M2Ne

REVISION
2.2

DATE:
SHEET
B

Tuesday, January 06, 2004

40

OF

56

DESCRIPTION:

KBC PULL UP & KB CONNECTOR

C

SCHEMATIC FILE NAME :

LIBRARY DATE :
D

DESIGN ENGINEER :
E

NEAR TO CPU
AND GMCH
+3VS

R340
330

R318
1.3K

Q57

1,18

2N3904
R375

330
1

H_INIT#

+3VS
Q60
2N3904

C111
10U_0805

R341
10K_*
U3

16,18,22,23,26,29,31,32,37,39

R26

PCIRST#_3

R44

RN1

INIT#
RST#

31
R45

0_*
FWH_FGPI4
FWH_FGPI3
FWH_FGPI2
FWH_FGPI1
FWH_FGPI0

7
5
3
1

6 CLK_FWHPCI
5 CLK_DEBUGPCI

100

24
2

5 D IS_SYSBIOS#_FWH

CLK

30
3
4
5
6

FGPI4
FGPI3
FGPI2
FGPI1
FGPI0

9
10
11
12

ID3
ID2
ID1
ID0

10K_8P4R

10K

VPP
VCC
VCC
VCCA
TBL#
WP#
FWH4
FWH3
FWH2
FWH1
FWH0
IC

16
26
28

8
6
4
2

0805

GND
GND
GNDA

RSVD
RSVD
RSVD
RSVD
RSVD

1
25
32
27
8
7
23
17
15
14
13

R10

C68

C106

C71

0.1U

0.1U

0.1U

LFRAME#
LAD3
LAD2
LAD1
LAD0

5,19,37,39
5,19,37,39
5,19,37,39
5,19,37,39
5,19,37,39

10K

D6
RB751

FWH_WP#

19

29
22
21
20
19
18

R43
10K
4

FWH32_PLCC32

ASUS PROJECT:
A

M2Ne

REVISION
2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
41
56
B

DESCRIPTION:
C

FWH

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

0.1UF

C653

+5VS

+3VALWAYS_P

0.1UF

C654

R653
100K

CN10

10P C660

10P C659

10P C658

10P C657

C31
0.1UF

10P C656

C32

10P C655

C33

CN-14_INSTKEY

0.1UF

15
16

0.1UF

15G
16G

C34

PWRON#
22
KBNUM_3 39
KBCAP_3 39
IDE_ACTIVE#
32
LID_BOT# 22
BAT_SAVING
39,40
EMAIL#_3 39,40
INTERNET#_3
39,40
AP0#_3
39,40
AP1#_3
39,40

EMAIL#_3
INTERNET#_3
AP0#_3
AP1#_3

0.1UF

1
2
3
4
5
6
7
8
9
10
11
12
13
14

1
2
3
4
5
6
7
8
9
10
11
12
13
14

PROJECT:
A

M2Ne

REVISION
2.2

DATE:
SHEET
B

Tuesday, January 06, 2004

42

OF

DESCRIPTION:

56
C

Instant Key & Lid Switch

SCHEMATIC FILE NAME :

LIBRARY DATE :
D

DESIGN ENGINEER :
E

+3VALWAYS_P
1

R617
10K

14

Q83
2N7002

39 MSK_INSTKEY#

C265
0.1uF

1
2
3
4

DJ_PWR#

R206
10K_*

0603

+3V
5

(0603)
1

26,28 CCD1#

6,7,19

(0402)

26,28 C S T S CHG/STSCHG#/BVD1

SUSA#_3

R204

U24
7SZ00

VCC

QA#

CB#
DB
CLKB
SB#

QB
QB#

SWDJ_EN#

39

6
9

CBDEBUGEN#

5,27

GND

C264
1U_*

13
12
11
10

R207
0_402
(0402)

PCIRSTNS#_3

U25
QA

74LV74

GND
3

22,26,29,39

CA#
DA
CLKA
SA#

VCC

+5VS

1M_402
+3VALWAYS_P

+3VS

+3VALWAYS_P
2
39,40

KSO3_DJ

KSO3

R288
10K
Q33

R276
10K

R289
10K

+3VALWAYS_P

2N7002
3

Q35

+5V
DJ_PWR#

(0402)

DUAL_N_SC70-6P

D2

S2

G1

G2

Q45

R175
3

100K_402

2
2

5
DJ_PWR#

SWDJ_LED

S1

D1

PWR_LED#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

CN22
1

DTC114TKA

DJ_LED_VCC

R176
PWRON_LED#

Q34

5
6

5_G
6_G

1K_402

SWDJ_LED

Q36

(0402)

39

SWDJ_LED
(0402)

R178
300_402

DUAL_N_SC70-6P

D2

S2

G1

G2

(0402)

R177
DJ_LED_VCC
10K_402

CON4_DJ
2
1

S1

D1

D2

S2

G1

G2

S1

D1

4
5
6

PWRON#_3A

22

CN21

+3V
48

DUAL_N_SC70-6P

5
6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

+5VS
INTCLK_TP
39
INTDATA_TP
39

+3VS
+5VLCM
KSO3_DJ
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
PWRON_LED#
WIRELESS_LED#

KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

39,40
39,40
39,40
39,40
39,40
39,40
+3V

CHG_LED#
EMAIL_LED#

48
39

CON20_TP_DJ

37,40 802_ON#

2
D23

PROJECT:
A

M2Ne

REVISION
2.2

DATE:
SHEET
B

Tuesday, January 06, 2004

43

OF

DESCRIPTION:

56
C

Audio_CD Key

1
D-1SS355

SCHEMATIC FILE NAME :

LIBRARY DATE :
D

DESIGN ENGINEER :
E

AC_BAT_SYS

V ID 0 1 2 3 4 5

1
R700

1M

1
2

C665

C666

1U/25V/Y5V_0805

C664

1
2

220U/2V_7343

220U/2V_7343

D50

C670

C669

1
2

EC31QS04
4
1

D1
D2
D3
D4
3
2
1

S3
S2
S1

D1
D2
D3
D4

1
102PC675

C674

1
2

10U/25V/X5R_1210
C673
2
1

C672
2

10U/25V/X5R_1210

T188
tp30

T189
tp30

GND

T190
tp30

C683

T193
tp30

T194
tp30

T195
tp30
1

2
1

PCPU_GND

T192
tp30

4
1

T191
tp30

104P

1
+

0.8UH/24A

2
G

+VCORE

(25A)

C681

5
6
7
8
D1
D2
D3
D4

L85

S3
S2
S1

Q101
IRF7822
4

3
2
1

IRF7811W_*
4

S3
S2
S1

2
CS+
511Ohm
CM+
2
511Ohm

D1
D2
D3
D4

5
6
7
8

3m_R2512

R696

GND
4

EC31QS04

C684
1

T180
tp30

D52

VR_PWRGD

T183
tp30

R702
1

2
MCH_OK
T197

T182
tp30

tp30

50

SI7840DP

4
3
2
1

GND

Q100

0
1
R701

T179
tp30

2
104P

2
T196
1

T178
tp30

1
C671

360Ohm
2

1
R703

2
1K/1%

C685

MCH_OK
1
R704

2
1
100K/1% R705
1.2K/1%

1
R706

2
4.7K

1
R707

2
1K/1%

472P

R708

100K

GND

R 0 603

tp30

0 603

VRM_PWRGD

T181
tp30

1U/25V/Y5V_0805

2
2.7

0 6 03

1
R692

2
1K

6,8,19

S3
S2
S1

1
102P
C721

GND2
CSP
CSN
CMN
CMP
DPSLP#
SUS
V+
BSTS
LXS
DHS
DLS
PGND

CM+

470P

T176
tp30

GND

AC_BAT_SYS

Q108
1
R697
1
R698

T177
tp30

RB717F

3
2
1

1
R699

PM_PSI#

+5VO

102P

36
35
34
33
32
31
30
29
28
27
26
25

VDD
DLM
DHM
LXM
BSTM
DD0#
D0
D1
D2
D3
D4
D5

GND

CS+

C722

C679
2

GND

T174
tp30

1
R0603

C678 100P
2
1

100K/1%

3m_R2512

T175
tp30

T173
tp30

R695

PCPU_GND

4.7U/16V/Y5V_1206

+5VO

IRF7822
4

1
2
R693 100K/1%
1
2
R694 10_R0805

CLK_EN#

Q99

3
2
1

IRF7811W_*

CLK_EN#

5
6
7
8

5
6
7
8

C668 104P
1

Q107

T172
tp30

R686

+VCORE
T171
tp30

L84
0.8UH/24A

1
R685

C676

VRON

TIME
TON
B0
B1
B2
S0
S1
S2
SHDN#
REF
ILIM
VCC

PCPU_GND

2
SHORT5MM

4
3
2
1

2
0

T170
tp30

C714
2
49
48
47
46
45
44
43
42
R 0 603
41
1
2
40
39 R689
2.7
38
37

DPRSLPVR

1
2
3
4
5
6
7
8
9
10
11
12

2
SHORT5MM
JP41

104P_*
1

1
R683

T187

2
56K/1%

JP38
1

D51

VR_VID5
VR_VID4
VR_VID3
VR_VID2
VR_VID1
VR_VID0

T186

1
R691
STPCPU#

C667
220UF/25V

GND

U64
MAX1987

GND
CCV
POS
NEG
CC1
FB
OAINOAIN+
PSI#
SYSOK
IMVPOK
CLKEN#

T185

VRON

STPCPU#
DPRSLPVR

SI7840DP

1 0U/25V/X5R_1210_*

1
Q98

8
7
6
5 D

tp30
1
tp30
1
tp30
1
tp30
1

T184

C663

1
R681

13
14
15
16
17
18
19
20
21
MCH_OK
22
VR_PWRGD 23
24
CLK_EN#

22,50 CPU_VRON

2
1K
2
1K
2
1K

C680 47P
2
1

1
R687
1
R688
1
R690

PM_STPCPU#

4.7U/16V/Y5V_1206

19

19 PM_DPRSLPVR

474P/25V/0805_Y5V
C677
2
1

10U/25V/X5R_1210

VR_VID0
VR_VID1
VR_VID2
VR_VID3
VR_VID4
VR_VID5

GND

1
R677

104P_*
1

2
OPEN2MM
2
OPEN2MM
2
OPEN2MM
2
OPEN2MM
2
OPEN2MM
2
OPEN2MM

C713
2

OPEN2MM JP44

OPEN2MM JP49 1

2 OPEN2MM JP43
1

OPEN2MM JP48 1

2
1

OPEN2MM JP47 1

1
JP36
1
JP37
1
JP39
1
JP40
1
JP45
1
JP46

2
47K
2
47K
2
47K
2
47K
2
47K
2
47K

1
R676
1
R678
1
R679
1
R680
1
R682
1
R684

8
7
6
5 D

2 OPEN2MM JP42

+3VO

VR_VID0
VR_VID1
VR_VID2
VR_VID3
VR_VID4
VR_VID5

2
2
2
2
2
2

0 . 956V 1 1 1 1 0 1

102P

AC_BAT_SYS

1 . 468V 1 1 1 1 0 0

tp30

T166
tp30
T169
tp30

T168
tp30

T167

T165
tp30

T164
tp30

220U/2V_7343

+3VO

PROJECT:
A

M2Ne

REVISION
2.2

DATE:
SHEET
B

Tuesday, January 06, 2004

44

OF

DESCRIPTION:

56
C

Vcore

SCHEMATIC FILE NAME :

LIBRARY DATE :
D

DESIGN ENGINEER :
E

3D

tp30
T142

R224
100K

R639

1
1

10UF/25V

4
3
2
1

C609

+5VLCM

tp30
T160
2

1
R219

5
6
7
8
1
1U

BAT

50m

5750
7343

2
2
C629

D48
EC31QS04

+ C269
15UF/25V
tp30
T129

tp30
T143

tp30
T150

JP35
1

1
0.1U
2
100K
2
C631

1
TMP/22UH/3.6A

R213

47P

R217
1
1

R643
49.9K

GND

R218
47K

R211

tp30
T69

L28

MB3878

100K

150K

0.01U
2

R222
8.2K 2

Q86
SI4425DY

2 0.1U

BAT_SET

47P

2
47KOhm

C273
0.01U

C271
4.7u

CONS_POWER#

CS_SET

R223
1

C270 1

C272
1

10

24
23
22
21
20
19
18
17
16
15
14
13

C268

5VREF

+INC2
GND
CS
VCC(O)
OUT
VH
VCC
RT
-INE3
FB3
CTL
+INC1

ICHG_SET

AC_BAT_SYS

R210

-INC2
OUTC2
+INE2
-INE2
FB2
VREF
FB1
-INE1
+INE1
OUTC1
OUTD
-INC1

1
2
3
4
5
6
7
8
9
10
11
12

8.2K

R638
1
150K

R641
24.3KOhm

A/D_VIN

2
U62

C639 4 7 P
2
1

tp30
T58

C267

C643
0.01U

GND

R640

tp30
T151

8.2K
2

Q38
2 S 2N7002_*
1

R216
60.4K

SUSB#_PWR

56.2K_*
2

48,50,51

R215
1
tp30
T101

GND

tp30
T60

BAT_S

150K

R634

CHG_EN

A/D_VIN

-A
OUTA

R208
13K
1

LMV393

tp30
T54

A/D_VIN_O
+2.5VREF

C266
0.1U

+A

+B

48

-B
OUTB

ICHG_OUT

R214

GND

GND

tp30
T147

V-

V+

47K

U60
8

SHORT5MM

R209

100K

GND

tp30
T215

EOC#

VCC

48

EOC#_O

CONS_POWER#

GND

tp30
T56

U26

3
C726
0.1U

NC7SZ32
GND
4

PROJECT:
A

M2Ne

REVISION
2.2

DATE:
SHEET
B

Tuesday, January 06, 2004

56
45
OF

DESCRIPTION:

CHARGE
C

SCHEMATIC FILE NAME :

DESIGN ENGINEER :

LIBRARY DATE :
D

+5VAO
R313
2

Q55
3

1
5.1KOhm

D3

2N7002

2S

11

SUSC#_PWR

S 2 G

TP0610T
G

49,50,51

11

Q54

3 D
3

GND

AC_BAT_SYS
47,49 SHUT_DOWN#

C92

C23

10UF/25V

1U

R319
681Ohm

C24
0.1U

R0805

R23
2

10_R0805

AC_BAT_SYS

PSYS_GND
Q2

JP1
4
S 1 /D2_1

C354 4 7 P
2
1

R321
1

1MOhm
2

SHORT5MM

3.65KOhm
2

GND

T96
tp30

T22
tp30

10UH

T95
tp30

T6
tp30

T99
tp30

D7
FS1J4TP

C63
1U

GND

C36
1U

tp30
T217
D8
1

+12VM

C35

GND

CE2
120U

1
2

2.7Ohm
2

10UF/25V

AC_BAT_SYS

GND

0.1U
2

C55
1

2
R322
10KOhm

2
RB717F

D10
3

R24
1

T91
tp30

L50

1
+5VAO

R320
1

+3VO
7

0.1U
2

C54
1

100P
1

2.7Ohm
2
82KOhm
2

3
G2
S 1/D2_2

T7
tp30
R21
1
R22
1

28
27
26
25
24
23
22
21
20
19
18
17
16
15

4.7uF/25V

R309

0.1U
1
C718
2

C350
1

C76

10KOhm

4.7u
2

4.7u

+12VM

RUN/ON3
DH3
LX3
BST3
DL3
SHDN#
V+
VL
PGND
DL5
BST5
LX5
DH5
SEQ

CSH3
CSL3
FB3
12OUT
VDD
SYNC
TIME/ON5
GND
REF2.5V
SKIP#
RESET#
FB5
CSL5
CSH5
MAX1902

C340
4.7u
C43
2
1

1
2
3
4
5
6
7
8
9
10
11
12
13
14

1
U4
T27
tp30

+12VO

C378
2
2

SHORT5MM
JP2

S2

D1_2
S 1/D2_3

2
D 1_1
G1

1
SI4814DY

T34
tp30

PSYS_GND

C51
4.7u
2

SI4814DY
3

L51

T89
tp30

T19
tp30

T94
tp30
1

2
1

tp30

1U
1

GND

PROJECT:
A

M2Ne

REVISION
2.2

DATE:
SHEET
B

Tuesday, January 06, 2004

46

OF

DESCRIPTION:

56
C

SYSTEM

SCHEMATIC FILE NAME :

DESIGN ENGINEER :

LIBRARY DATE :
D

T2
tp30

GND

C93

T12
tp30

C57
1U

T9
R310
10.2KOhm

D11
FS1J4TP
1

R324
560Ohm

100U
+ CE3

2MOhm

R323
1

47P
1

C371
2

R305
10.7KOhm

C355
100P

T86
tp30

10UH
1

S2
S 1/D2_1

S 1 /D2_2

G2

2
S 1 / D 2_3 D 1 _2

Q4

+5VO
8

T8
tp30

G1

D 1_1

FS05J10TP

T149
tp30
BAT_LLOW

T107
tp30

AC_BAT_SYS

48

470K

R586

R587
2
D44

SHUT_DOWN#

46,49

BAT_IN#_OC

37,39,40

T13
tp30

Q80
UMZ1N

+5VLCM

1SS355

10K
R621

+2.5VREF

365K
1

1
R601

R600
2

BAT_S

100K

A/D_VIN

R603
2

T146
tp30
R602

100K
2

1
C611
0.1U

C638
1000P

Q93B
UM6K1N

C610
0.1U
2

143K

C625
0.1U

C635
0.1U

100K
2

GND

+2.5VREF

Q93A
UM6K1N

R646

100K
R637

0.1U

C597

4.7u

C604

R585

2S

2
1
100K

Q84
2N7002

OUTPUT3
OUTPUT4
GND
INPUT4+
INPUT4INPUT3+
INPUT3-

49.9KOhm

4.7u

47K

1
R642
1

OUTPUT2
OUTPUT1
V+
INPUT1INPUT1+
INPUT2INPUT2+
LM339MX

14
13
12
11
10
9
8

470K
R622

2
442K
2

C636
2

3
3

+2.5VREF

R635
1

11

1
2
3
4
5
6
7

+5VLCM
+2.5VREF

Q94A
UM6K1N
BAT_S

AC_APR_UC

U58

1
1

100K

3
4

GND

100K

2
1

29,48 AC_APR_UC

T226
tp30

R644

T161
tp30
Q94B
UM6K1N
5

R636

4.7M

R648

47K
C637
1U

tp30
T224

1
1

2
+5VLCM

T225
tp30

RB715F
R645

D43
220K

3
C

R629

GND

E
4

S 2

11

+5VCHG

T152
tp30

IRLML2402

1
E

Q91
D3

BAT_LLOW#_OC

C
6

19,39,40

+5VLCM

T65
tp30
1

GND

TS#

48

T84
tp30
AC_PHY

A/D_VIN_O

A/D_VIN

R9
2

2
50m

FD6JK3TP

2
1

R292 100K_*

2
1
R286 10K_*

+5VCHG

1
3

GND

OUT

F02JK2E

R605
4.7K

LM3480
T140
tp30 +2.5VREF
1
1

C613
1U

GND
GND

PROJECT:
A

M2Ne

REVISION
2.2

DATE:
SHEET
B

Tuesday, January 06, 2004

46
47
OF

DESCRIPTION:

BATLOW#/SD#
C

SCHEMATIC FILE NAME :

DESIGN ENGINEER :

LIBRARY DATE :
D

U57

1
C618
1U
2

C632
1U

C630
1U

LM4040BIM3X

+2.5VREF

IN

+5VLCM

2N7002_*
1

2S

PMBS3904_*

E
2

U59

1
4

100K

C320 0.1U_*

29,48 AC_APR_UC

Q89B
UM6K1N
5

R270 10K_*

R18

A/D_VIN
Q48

1 B

2N7002

2S

10K

T145
tp30

G
3
C

+5VO
D47

11
Q47

11

Q89A
UM6K1N
2

Q51

+5V

+5VCHG
3

R633

2
3

R628
3D

D31
UDZS_18B_*

6 1

2N7002

2 S

2
30K

3
C65

R293
1

11
G

GND

BAT

R664 100K_*

C623 0.47U_*

2
20K
1

R281

R618

18K

1
2
0.1U

10K

A/D_SD

1
E

3D
Q50

T17
tp30

Q53
DTC144EK

Q52
UMZ1N_*

47K
R-2
47K

A/D_SD

3
C

R-1

G
SI4425DY

C
6

3
C
E

39 BAT_LEARN

AC_BAT_SYS

1
2
3
4

Q87
D

R287 10K_*

R267
2

8
7
6
5

C661 4.7u_*

22K

1
2
1

R282
2

R291

R15
1

C333 0.47U

100K

10K

100K

1
3

BAT

AC_BAT_SYS

11
S 2

T15
tp30

Q49
2N7002

T14
tp30

SI4425DY

D3

T11
tp30

D9

8
7
6
5

Q44
1
2
3
4

T85
tp30

ACIN_OC

T4
tp30

T74
tp30

T79
tp30

E
4

A/D_DOCK_IN

37,39,40

T72
tp30
1

T73
tp30

AC_BAT_SYS
3

T76
tp30

+5VLCM
1

R632
4

100K

NC
SUB
GND

VOUT

1U

tp30
T156

tp30
T144

GND

GND

PST9142

tp30
T154

tp30
T66

tp30
T70

2
R627
47K

C612
tp30
T106

VCC

1
2
3

U63
5

Q 8 5 A UM6K1N
1
6

tp30
T135

Q85B
3

UM6K1N
4

PWM

36

HDQ

39

T128
tp30
1

1
1M

T100
R631
1

X6
1

R667
C621
1U

+5VS

RST_BTN#

tp30
T155

22

GND

Q92

3D

GND

2
4.7K

4.7K_*

RESOR-4MHz_MAT

PWR_LED#

tp30
R604

tp30
T138

GND

CHG_LED#

43

tp30
T75

GATING#
HDQ_BAT

43

AC_APR_UC
29,47
TS#
47

tp30
T61

SUSB#_PWR

tp30
T163

2
1SS355

18
17
16
15
14
13
12
11
10

RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
Vdd
RB7
RB6
RB5
RB4

RA2
RA3
T0CKL
MCLR#/Vpp
Vss
RB0
RB1
RB2
RB3
PIC16C54C

D49

37,40 CHG_FULL#

45,50,51

1
2
3
4
5
6
7
8
9

EOC#
CHG_EN

U61
45
45

D3

D3

Q88

Q82

2N7002

1
11

2 S

2N7002

GND

S2

100K
2

2N7002

G
R630
100K
1

R647

S 2

11

GND

T68
tp30

tp30
T90

BAT_S

L79

T67
tp30
1

T158
tp30
1

T228
tp30

+5VS

1K OHM/100MHZ
L82

L83

tp30
T59
Q39
PMBS3904
B 1

3
C

R220
1

BAT_LLOW

47

GND

100K OHM

0.01U

R221
1

GND

C128
2
1

100K

E
2

BAT_EDV1
HDQ_BAT
TS#

1K OHM/100MHZ
C644
0.1U

C641
0.1U

C640
0.1U

1K OHM/100MHZ

1
1
25133A-06G1-10

tp30
T38

U12
2

1
2
3

100K

C642
100P

NC
VCC
SUB
GND VOUT
PST9013

5
4

L81
1

2
1K OHM/100MHZ

L80
1

THERMAL PROTECTION
PLACE UNDER CPU

R86

tp30
T36

6
5
4
3
2

80 DEGREE C

33.2KOhm
tp30
T162

CN29

R95
BAT

4532
680 OHM 100MHZ

T227
tp30

OTP#_P

GND
GND

PROJECT:
A

M2Ne

REVISION
2.2

DATE:
SHEET
B

Tuesday, January 06, 2004

46
48
OF

DESCRIPTION:

PIC16C54
C

SCHEMATIC FILE NAME :

DESIGN ENGINEER :

LIBRARY DATE :
D

+5VALWAYS

2 +5VALWAYS
0

+V1.25S

+V2.5

R750

+5VAO

1
2
100KOhm

R7101 0 0 K
2

TP94

1
T222
tp30

C687
104P

22,24 SUSB_DIS_3

0Ohm
2

2 S

VCNTL_3

REFEN

VCNTL_2

VOUT

VCNTL_1

8
7
6

+ CE4

100KOhm

10UF/6.3V

2N7002

RT9173

C686
100U/2V

10UF/6.3V
C719

VCNTL_4

GND

R711
Q102

11

GND

4
1

R712
1

3D

VIN

CE6
47U/6.3V/EL

R751

+3VALWAYS_P
1

D54
F01J2E

47uH
1

+3VAO

L86

T223
tp30

6
OUT 5
SHDN# 4
LX
MAX1836
2

FB
GND
IN
U66

CE5
2

10U/35V/EL
1

1
2
3

U69

+3VALWAYS_P
2

PWR_JUMP

AC_BAT_SYS

PWR_JUMP
2

R709

JP50

F01J2E

JP51

46,47 SHUT_DOWN#

+3V

+V2.5
D53
2

GND

+V2.5

+V1.5ALWAYS

+15VOSUS

R665
46,50,51

SUSC#_PWR

+V1.8

100K

(0.6A)

2
1 2
JP15 PWR_JUMP

EN
IN
OUT
FLG

GND4
GND3
GND2
GND1

8
7
6
5

10UF/6.3V

R192
10K

MIC37101

GND

100K

C407

+3VO
2

4.7u

10UF/6.3V

C233

Vref=1.215V
1

1
2
3
4

C410

R191
2.4K

PWR_JUMP

U13
2

0.1U

+15VOSUS

C662

ADJ

OUT

IN
GND
EN
SI9183DT

1
2
3

U23

T39
tp30 +1.8VO

JP14

R190
0

tp30
T49

tp30
T127

+3VALWAYS

GND

R417

GND

1.8V_PWRGD
5

PROJECT:
A

M2Ne

REVISION
2.2

DATE:
SHEET
B

Tuesday, January 06, 2004

46
49
OF

DESCRIPTION:

1.25V & 1.8V

C

SCHEMATIC FILE NAME :

DESIGN ENGINEER :

LIBRARY DATE :
D

T198
tp30

C697

C704

1
1

1
R753

G
3
C Q109
1 B

4
3
2
1
1

E
2

tp30
1
10UF/25V

tp30
2

+1.2VO

3.3UH

(2+1A)

T213

tp30
1

1
JP58
2
1 2
PWR_JUMP

+V1.35S

tp30

+ CE10
120U

T214
tp30

2200P

SI4814DY

GND

JP59
+1.2VGND

T212

L89
1

C711

2
2
0Ohm

OUT
NC
VDD
GND
NC
RN5VD09CATV

GND

T211

Q106

CE9

AC_BAT_SYS

C706
0.1U

T210

GND

1
2
3

(1A)

+1.05VO

2
4.75KOhm

U68

100U/2V

1
R732

tp30

Q112
2 S 2N7002

PMBS3904

2
0.1U_*

20KOhm
2

3D
1

RSS090N03

2
0Ohm

R731
1

100KOhm

1 2
PWR_JUMP

Q105

0.1U

29.4KOhm

+VCCP

JP57
1

T208

T209

1
1

10UF/25V

20mOHM

5
6
7
8

4.7uF/25V

R730

C716

tp30

R739

1
2

1
2

R728

1
R737

C712

C688

S2
S 1/D2_1

680Ohm

44

2
0.1U_*

R735

7.5KOhm

0.1U
2

C708

1
GND

MCH_OK

GND

VREF5
1
C715

1SS355

R738

1
2

2
49.9KOhm

C710 0.01U

GND

VREF5

GND

C705
2

+ CE8
100U/2V

T207
tp30

GND

13
14
15
16
17
18
19
20
21
22
23
24
2.7KOhm
2
R734

6
1

(1.5A)

3.3UH

SHORT5MM

C709
0.1U

4
SI4814DY

1
2
3

R736

SUSB#_PWR

+1.5VO

+5VO

LL2
OUT2_u
LH2
VIN
VREF3.3
VREF5
REG5V_IN
LDO_IN
LDO_CUR
LDO_GATE
LDO_OUT
INV_LDO

D57

2 +1.5VO

JP55

+1.2VGND

0.01U

tp30
L88
1

48
47
46
45
44
43
42
41
40
39
38
37
INV1
FLT
LH1
OUT1_u
LL1
OUT1_d
OUTGND1
TRIP1
VIN_SENSE12
TRIP2
OUTGND2
OUT2_d
TPS5130

0Ohm

C707

+1.5VGND

36
35
34
33
32
31
30
29
28
27
26
25

R733

T206

R740
CPU_VRON

1
1

C703

FB1
SS_STBY1
INV2
FB2
SS_STBY2
PWM_SEL
CT
GND
REF
STBY_VREF5
STBY_VREF3.3
STBY_LDO

AC_BAT_SYS

1SS355

SS_STBY3
FB3
INV3
PGOUT
PG_DELAY
TRIP3
VIN_SENSE3
LH3
OUT3_u
LL3
OUT3_d
OUTGND3

0.1U

100KOhm

GND

R729

GND

45,48,51

G2

D56

2
1
2
2
0Ohm

1
2
3
4
5
6
7
8
9
10
11
12

tp30
Q104

C701
0.1U

+2.5VGND

2
0Ohm

1
C699
0.1U

0.1U

U67

ON_2.5

GND

R724

C696 0.01U

1
R723
VREF5

2
5.36KOhm
2

2.7Ohm
1

+1.5VGND
R725
2.7KOhm

1.8KOhm

C702
47P

Q110B
UM6K1N
5

S 1/D2_2

2
1
1
0.01U

ON_1.5

Q110A
UM6K1N
2

D 1_2

GND

AC_BAT_SYS

R722
1
C695

C698
3300P

1
2

+V2.5

JP54
2
1 2
PWR_JUMP

2
2

C693
2

T205

R726

100KOhm

+ CE7
120U

T204
tp30

0.1U

R727
0Ohm/?

T203
tp30

C700
22,44 CPU_VRON

tp30

tp30

AC_BAT_SYS

R721

GND

5.2UH
T202

T201

GND

(5A)

+2.5VO

D55

10KOhm

R752

SI4814DY

1SS355

330Ohm

2
1

Q103

2
SHORT5MM
T199 T200
tp30
tp30

C692
10UF/6.3V

12.7KOhm
2

R719

10KOhm

0Ohm

R718
1

R713

R714

R715
19.6KOhm

JP53
+2.5VGND
+2.5VO

R717
330Ohm/?

VREF5

D 1 _1

2
6800P

R720

S 1 /D2_3

1
6800P/?

C717

C691
1

C694

0.1U

L87

C690
2

0.01U
1

0.01U

7.68KOhm

6
1

3 2

C689

SUSC#_PWR

+2.5VO

RB715F

1
46,49,51

Q111B
UM6K1N
5

1
+1.5VO
Q111A
UM6K1N
2

G1

ON_2.5

R716
100KOhm

ON_1.5

1
3

D58

10UF/25V

VREF5

AC_BAT_SYS

2
SHORT5MM

GND

PROJECT:
A

M2Ne

REVISION
2.2

DATE:
SHEET
B

Tuesday, January 06, 2004

46
50
OF

DESCRIPTION:

SCHEMATIC FILE NAME :

2.5V & 1.5V & 1.2V & 1.05V

C

DESIGN ENGINEER :

LIBRARY DATE :
D

Q31
SI2304DS

T157
tp30

R666

2 S

3D

+1.8VO

+V1.8S

1 1

6
5
S 4

tp30
T132

tp30
T133

tp30
T229

1
2
3
R765
1

Q70
SI3456DV

100K

1
2
1 2
PWR_JUMP

+1.5VO

JP34
+V1.5S

C530
0.1U

6
5
S 4

tp30
T16

GND

tp30
T21

tp30
T231

1
tp30
T92

GND

tp30
T88

tp30
T232

1
G

6
5
S 4

+5V

0.1U

tp30
T77

tp30
T233

1
2
3

G
Q43
SI3456DV

C301
1
2

2
1 2
PWR_JUMP

JP21

Q17B
UM6K1N
5

1 2
PWR_JUMP

+5VS

SUSB#_PWR

2
GND

tp30
T81

C732
0.1U

C733
1
2

Q17A
UM6K1N
2

GND

1
D
1
2
3

2
R87
100K

Q119
SI3456DV

C311
0.1UF/?

+3VS

JP22

+5VO

2
1 2
PWR_JUMP

C52
0.1U

6
5
S 4

tp30
T93

1
2
3

Q8
SI3456DV

JP3
1

1
tp30
T80

+3V

C731
0.1U

GND

+3VO

JP25
2
1 2
PWR_JUMP

1
2
3

Q118
SI3456DV

tp30
T230

tp30
T104

tp30
T109

tp30
T103

Q117B
UM6K1N
5

tp30
T108

Q117A
UM6K1N
2

6
5
S 4

GND

GND

R19
1

100K
2

1K

Q12

GND

tp30
T105

+12VS

B
B

R36
100K

1 0K

4 7K

2
1K
GND

R53
1

SUSB#_3

19,22,27

4 7K

tp30
T98

SUSB#_PWR

tp30
T71

3
4 7K

45,48,50

R35
100K

UMC4N
Q10

tp30
T102

+12V

1 0K

4 7K

SUSC#_PWR

4 7K

+12VO
46,49,50

4 7K

tp30
T97

tp30
T35

SUSC#_3

C305
0.1U

100K

R52
19,29

0.1U
R766
2

tp30
T111

tp30
T110

GND

UMC4N

PROJECT:
A

M2Ne

REVISION
2.2

DATE:
SHEET
B

Tuesday, January 06, 2004

46
51
OF

DESCRIPTION:

LOAD SWITCH
C

SCHEMATIC FILE NAME :

DESIGN ENGINEER :

LIBRARY DATE :
D

VR_VID0-VR_VID5
PM_STPCPU#.,PM_DPRSLPVR.,PCI#.,MCH_OK.,CLK_EN#
CPU_VRON
+VCORE
1

AC_BAT_SYS

(25A)
1

MAX1987

PM_VGATE

SUSC#.

+5VO (5A)
MAX1902
+3VO
(5A)
(Regulator)
+5VAO
+12VO (0.15A)
+1.5VO (1.35A)

SUSC#

+2.5VO

(5A)

+V2.5

SUSB#
SUSB#
SUSC#
SUSC#
SUSB#
SUSC#

+5VS
+3VS
+5V
+3V
+12VS
+12V

SUSB#

+V1.5S

TPS5130

+V2.5

+V1.2S

+1.05VO(1A)

+VCCP

RT9173
+V1.25S(1A)
(Regulator)

A/D_VIN

SWITCH

CPU_VRON
SUSB#

+1.2VO (1.8A)

BAT_LLOW#_OC

Power
Signal
Circuit

BAT_S
TS

BAT_IN#_OC
ACIN_OC
AC_APR_UC
SHUT_DOWN#

SUSC#
3

+2.5VO MIC37101-1.8 +1.8VO (0.6A)

LDO

MB3878
(Charge)

+V1.8
SUSB#

CHG EN
CHG LED

+V1.8S
EOC#
SUSB#
AC_APR_UC

BAT

PIC16C54B/C

PWR LED
PWM
GATING

TS#

HQD_BAT

SI4425
4

A/D_VIN

FD6JK3TP
MAX1836
(Regulator)

+3VALWAYS

SI9183
(LDO)

+3VAO

LM3480-5
(Regulator)

+5VO (20mA) SWITCH

+5VCHG (20mA) (F02JK2E)

+3VALWAYS_P

+5VLCM
LM4040BIM
+2.5VREF
(Regulator) (500uA)

+V1.5ALWAYS

+5VAO

PROJECT:
A

M2Ne

+5VALWAYS

REVISION
2.2

DATE:
SHEET
B

Tuesday, January 06, 2004

52
56
OF

DESCRIPTION:
C

POWER FLOWCHART

SCHEMATIC FILE NAME :

LIBRARY DATE :
D

DESIGN ENGINEER :
E

PCI Device
Chipset (Host to PCI)
AGP
LAN --8101
CardBus
1394
Mini_PCI

IDSEL#
(AD30 internal)
(AD17 internal)
AD20
AD19
AD19
AD21

Interrupts

REQ/GNT#

PC/PCI

n/a
1
2
2
4

A
B,C
A
D

M38857_GPIO

USE_AS

P23

GPO

MSK_INSTKEY#

SIGNAL_NAME

M38857_GPIO
P27

USE_AS
GPO

SCROLL#_3

SIGNAL_NAME

P22

GPO

BAT_LEARN

P26

GPO

KBNUM_3

P20

GPO

KBCRSM

P25

GPO

KBCAP_3

P42

GPO

WATCHDOG

P24

GPO

PCIRST#_GATE

P43

GPI

SWDJ_EN

P41

GPO

EMAIL_LED#

I C H 4M_GPIO

Use As

GPIO07

GPO

Signal Name
SCROLLOCK#_3

GPIO08

GPI

EXT_SMI#_3A

GPIO12

GPI

KBCSCI#_3A

GPIO13

GPI

PORTDOCK_FDDIN#

GPIO25

GPO

CB_SD#

GPIO27

GPO

OP_SD#

GPIO28

GPO

XIDE_EN_3

GPIO32

GPO

BACK_OFF#

GPIO33

GPI

BAY_IN0

P44

GPO

KBDCPURST_3Q

P45

GPO

KBC_GA20

P46

GPO

KBSCI_3Q

P47

GPI

PM_CLKRUN#

P50

GPI

BAT_LLOW#_OC

NS87393_GPIO

USE_AS

GPIO10

GPI

ACIN_OC

P51

GPIO34

GPI

G PIO35

GPO

SIGNAL_NAME

BAY_IN1
P52

GPIO

1_WIRE_3Q

GPIO11

GPI

BAT_IN#_OC

P54

GPI

DOCK_IN#

GPIO12

GPI

FAN_SPD

P55

GPI

BAT_IN#_OC

GPIO13

P56

GPO

FAN_DA1

GPIO20

GPI

PCB_VID0

P57

GPO

SWDJ_LED

GPIO21

GPI

PCB_VID1

P67

GPI

FAN_SPD

GPIO22

GPI

PCB_VID2

P66

GPI

BAT_SAVING

GPIO23

GPI

KEYDETECT1

P65

GPI

+VCORE

GPIO24

GPI

KEYDETECT2

P64

GPI

ACIN_OC

GPIO27

GPI

CHG_FULL#

P63

GPI

AP1#_3

GPIO30

GPI

PID0

P62

GPI

AP0#_3

GPIO31

GPI

PID1

P61

GPI

INTERNET#_3

GPIO32

GPI

PID2

P60

GPI

EMAIL#_3

GPIO33

GPO

802_ON#

CG_FS0

G PIO36

GPO

CG_FS1

G PIO37

GPO

CG_FS2

G PIO38

GPO

CG_FS5

G PIO39

GPO

CG_FS6

GPIO40
GPIO41
GPIO42
G P IO43

GPO

FWH_WP#

ASUS PROJECT:
A

M2Ne

REVISION
2.2

DATE: Tuesday, January 06, 2004

53
SHEET
OF
56
B

DESCRIPTION:
C

SYSTEM INFO.

SCHEMATIC FILE NAME : BATLOW.SCH

LIBRARY DATE :
D

DESIGN ENGINEER :
E

V2.0 TO V2.1 MODIFY ITEM

1)OTP#_P_PULL_HIGH_10K_TO_+3VS
1

2)ADD_+VS_POWER_MOSFET

V2.1 TO V2.2 MODIFY ITEM

1)+V1.25S_REF

TURN ON IN S3

2)ADD_SIGNAL_ANYKEY_RSM_0.1U_CAPACITOR
3)ADD_Q120_2N7002_SWITCH_TO_LID_RSM#
2

4)CANCEL R673,R674

M2N V2.2 TO M2Ne V2.2 MODIFY ITEM

1)Chipset U43 changes to Intel855GME
2)Onboard DRAM changes to DDR333
(U15,U16,U17,U18,U44,U45,U46,U47)
3)Cancel R328 and R749
3

4)Add R352 10KOhm and R742 10KOhm

5)Change R739 to 29.4KOhm
(JP58 voltage changes to +1.35V)

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
54
56
B

DESCRIPTION:
C

Content & Rev. History

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

Content

PAGE

Content

PAGE

Revision History

M2Ne PAGE REF.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

V1.0_TO_V1.1_MODIFY_ITEM

BANIAS CPU-1
BANIAS CPU-2
CPU RES/CAP
FAN_THERMA_SENSOR
DEBUG PORT
ICS950805
ICS91718
MONTARA-GM_A
MONTARA-GM_B
MONTARA-GM_C
MONTARA-GM_D
ON_BOARD_256MB_DDR-1
ON_BOARD_256MB_DDR-2
SODIMM
DDR_DAMPING_PULL-UP
CRT_PORT
LCD_CONN
ICH4M_1
ICH4M_2
ICH3M_3
ICH3M_4
RESET
AC97
AUDIO AMP (TI-TPA0212)
MIC_PRE.AMP/MDC
CARDBUS_RICOH_R5C590
CARDBUS_POWERSW_1394_SLOT
CARDBUS_CONN
LAN_RTL8101
LANIO
MINIPCI
HDD/BAY_CONN
SM_BUS
USB20_CONN
PORT_BAR2
INVERTER_RTC_CONN
SUPER_IO_NS87393
IR/LPT
KEYBOARD_CONTROLLER
KBC_CAP/RES

41
42
43
44
45
46
47
48
49
50
51

FWH
INSTANT_KEY
AUDIO_DJ_KEY
VCORE
CHARGE
SYSTEM
BATLOW
PIC16C54
1.25V & 1.8V
2.5V_1.2V_1.5V_1.05V
LOAD_SWITCH

1)MODIFY +VCORE CAP

2)CHANGE_THERMAL_IC_CIRCUIT
3)CLK_GEN_+3V_TO_+3VS
2

4)ADD_68PIN_PORT_75OHM
5)UPDATE_VRM_PWRGD_RC_CIRCUIT
6)ADD_INT_E~H_PULL_HIGH
7)MODIFY_USB_POWER
8)DEL_1/10_ON_9/10_OFF_CRCUIT

V1.1 TO V1.2 MODIFY ITEM

1)ADD MEMORY SIZE SET GPIO
2)SELECT_OPMUTE_METHOD
3)ADD_R_G_B_SIGNAL_CAP
4)CHANGE_+VCORE_+VCCP_2.5V_1.5V_1.2V_SOURCE
4

V1.2 TO V2.0 MODIFY ITEM

1)CRT_SYNC_CONTROL_BY_PCIRST#
2)AMP_GAIN_CHANGE_6X
3)ADVANCE_BAY_POWER_CONTROL

ASUS PROJECT:
A

REVISION

M2Ne

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
55
56
B

DESCRIPTION:
C

Content & Rev. History

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E

M2Ne_Dothan/MONTARA-855GME_BLOCK_DIAGRAM
1

14_INCH_LCD
PORT BARII
35

Dothan

LCD &INV.
Conn_RTC.

478 uFCPGA

....

1,2

36

DEBUG
PORT

CPU
CAP/RES

RESET

DCIN_Jack
RTC/INV

INSTANT
KEY

LCD_CN

6,7

17

+2.5V
+1.25V

Hublink
USB2.0

USB 2

CAP/RES
.... DDR

15

PCI_BUS

ICH4-M

34

IDE_BUS

421 BGA

3.3V, 33MHz
3

AC LINK

CARDBUS

CDROM

RICOH
R5C590

16,17,18,19

SWAP BAY

HDD_CN

32

32

23

45

LAN

MINI PCI
TYPEII 31

REALTEK 8101

26

29

AC97
STAC9700T

44

FDD

SYSTEM

14

66MHZ

34

CHARGE

256/
512 Mb
DDR
X 8
12,13

8,9,10,11

USB 1

04

DDR333
SODIMM X 1

732 uFCBGA
16

FAN & Thermal

Sensor
(Max. 6657)
DDR SDRAM 333MHz

Montara855GME
CRT

VCORE

33

AGTL
1.3V,100MHZ

CLOCK GEN.
ICS950815

36

SM_BUS

42

HOST BUS
2

22

LPC, 33MHz

46

Mic
pre.
AMP

MDC
25

25

LAN IO 30

CARDBUS
1 SLOT

AUDIO AMP
24

BATLOW/SD#

SUPER I/O
PC87393 37

47

MICCTRL
PIC16C54

KEYBOARD
CONTROLLER
M3885XHP 39

FWH
41

48

EAR
OUT

MIC.
IN

24

24

VCCA, VCCB
VPPA, VPPB

RJ11
1394
SLOT

MCH & VCCP &

1.8V
49

27,28

27

IR

2.V & 1.25V &

1.5V

LPT
38

INTERNAL
KEYBOARD&TP

38

AUDIO_DJ

40

43

50

SW BOARD

LOAD Switch 51

PWR
BUT.

FUN.
KEY

BATTERY
4 X 2

ASUS PROJECT:
A

M2Ne

REVISION

2.2

DATE: Tuesday, January 06, 2004

SHEET
OF
56
56
B

DESCRIPTION:
C

BLOCK DIAGRAM

SCHEMATIC FILE NAME : <Doc>

LIBRARY DATE :
D

DESIGN ENGINEER :
E