EXPERIMENT #3

A. Logic Diagram
OBJECTIVES

To implement the Logic Diagram through the use of NAND gates.

To verify that the output of the original equation in the logic diagram
and the simplified version is the same.
To simplify the logic diagram as much as possible and lessen the use of
IC.

Logic Diagram Original

(SIMULATION)
000

011
XSC1
X1 X2 X3 X4

U1
555_TIMER_RATED
R1
100

U3
14
1

OUT

DIS

R2

THR

V1
5V

TRI

10k
0%
Key=A

CON

2
3
10

INA
INB
R01
R02
GND

R1
100

14
1

OUT

DIS
THR

CON

2
3
10

INA
INB
R01
R02
GND

VCC
QA
QB
QC
QD

5
12
9
8
11

74LS93D

U7B

GND

U6A

C2
.01F

V1
5V

TRI

10k
0%
Key=A

U7B

GND

C1
100F

2.5 V2.5 V2.5 V2.5

+ V_

U3

VCC
RST

R2

74LS93D

Ext T rig
+
B

5
12
9
8
11

VCC
QA
QB
QC
QD

X1 X2 X3 X4

U1
555_TIMER_RATED

VCC
RST

XSC1
Ext T rig
+

_
2.5 V2.5 V2.5 V2.5
+ V

7410N

7400N

U2A

U8A

U9B

7410N

7410N

7400N

U4A

U5B

7400N

C1
100F

U6A

C2
.01F

7410N

7400N

U8A

U9B

U2A

7410N

7410N

7400N

U4A

U5B

7400N

LED1

7400N

7400N

100

111
XSC1
XSC1

X1 X2 X3 X4

U1
555_TIMER_RATED

Ext T rig
+
_

R1
100

U3

VCC
RST

14
1

OUT

DIS

R2

THR

V1
5V

TRI

10k
0%
Key=A

CON

INA
INB

2
R01
3
R02
10 GND

VCC
QA
QB
QC
QD

R1
100

5
12
9
8
11

OUT

DIS
THR

V1
5V

TRI

10k
0%
Key=A

U7B

_
2.5 V2.5 V2.5 V2.5
+ V

U3

VCC
RST

R2

74LS93D

Ext Trig
+
B

CON

14
1

INA
INB

2
3
10

R01
R02
GND

VCC
QA
QB
QC
QD

5
12
9
8
11

74LS93D

U7B

GND

GND

C1
100F

X1 X2 X3 X4

U1
555_TIMER_RATED

_
2.5 V2.5 V2.5 V2.5
+ V

U6A

C2
.01F

C1
100F

7410N

U6A

C2
.01F

7410N

7400N

7400N

U8A

U9B

U2A

7410N

7410N

7400N

U4A

U5B

7400N

U8A

U9B

U2A

7410N

7410N

7400N

U4A

U5B

7400N

LED1

LED1

7400N

7400N

110

010

XSC1
XSC1

U3

VCC
RST

14
1

OUT

DIS

R2

THR

V1
5V

TRI

10k
0%
Key=A

CON

INA
INB

2
R01
3
R02
10 GND

R1
100

B
+

C2
.01F

RST

OUT

DIS
THR

V1
5V

TRI

10k
0%
Key=A

CON

_
2.5 V2.5 V2.5 V2.5
+ V

U3

VCC

R2

VCC 5
QA 12
QB 9
QC 8
QD 11

14
1

INA
INB

2
3
10

R01
R02
GND

VCC
QA
QB
QC
QD

5
12
9
8
11

74LS93D

U7B

GND

74LS93D

U7B

GND

C1
100F

2.5 V2.5 V2.5 V2.5

+ V_

Ext Trig
+
_

Ext Trig
+
A

R1
100

X1 X2 X3 X4

U1
555_TIMER_RATED

X1 X2 X3 X4

U1
555_TIMER_RATED

U6A
7400N

C1
100F
7410N
U8A

C2
.01F

U6A
7400N

7410N
U8A

U9B

7410N

7410N

U9B
U2A

U2A

7410N

7400N

U4A

7400N

U4A

U5B

7400N

U5B

7400N

7400N

7400N

7410N

LED1

LED1

LED1

101

001
XSC1
X1 X2 X3 X4

U1
555_TIMER_RATED
R1
100

U3

VCC
RST

OUT

DIS

R2

THR

V1
5V

TRI

10k
0%
Key=A

CON

XSC1
Ext Trig
+

14
1

INA
INB

2
3
10

R01
R02
GND

Ext Trig
+
_
B

VCC
QA
QB
QC
QD

5
12
9
8
11

R1
100

74LS93D

RST

C2
.01F

THR

U8A

U2A

U4A

U5B

7400N

CON

INA
INB

2
3
10

R01
R02
GND

5
12
9
8
11

VCC
QA
QB
QC
QD

74LS93D

U7B

GND

U9B

7410N

7400N

V1
5V

TRI

10k
0%
Key=A

7410N

7400N

14
1

OUT

DIS

R2

U7B
U6A

_
2.5 V2.5 V2.5 V2.5
+ V

U3

VCC

GND

C1
100F

X1 X2 X3 X4

U1
555_TIMER_RATED

_
2.5 V2.5 V2.5 V2.5
+ V

7410N

C1
100F

LED1

U6A

C2
.01F

7410N

7400N

U8A

U9B

U2A

7410N

7410N

7400N

U4A

U5B

7400N

7400N

7400N

Logic Diagram (Simplified)

SIMULATION

001

010
XSC1
X1 X2 X3 X4

U1
555_TIMER_RATED
R1
100

14
1

OUT

DIS

R2

THR

V1
5V

TRI

10k
0%
Key=A

CON

INA
INB

VCC
QA
QB
QC
QD

2
R01
3
R02
10 GND

R1
100

5
12
9
8
11

RST

14
1

OUT

DIS
THR

CON

2
3
10

INA
INB

VCC
QA
QB
QC
QD

R01
R02
GND

5
12
9
8
11

74LS93D

GND

U5B

C1
100F

7400N

U4C

V1
5V

TRI

10k
0%
Key=A

_
2.5 V2.5 V2.5 V2.5
+ V

U3

VCC

R2

74LS93D

C2
.01F

Ext T rig
+
B

GND

C1
100F

X1 X2 X3 X4

U1
555_TIMER_RATED

VCC
RST

XSC1
Ext Trig
+

2.5 V2.5 V2.5 V2.5

+ V_

U3

U5B

C2
.01F

7400N

U4C

U6C
7400N
7400N

U2A

U6C

7400N

LED1

7400N

U2A

7400N

LED1

7400N

100

111
XSC1
X1 X2 X3 X4

U1
555_TIMER_RATED

Ext Trig
+

R1
100

U3

VCC
RST

14
1

OUT

DIS

R2

THR

V1
5V

TRI

10k
0%
Key=A

CON

XSC1

_
B

2.5 V2.5 V2.5 V2.5

+ V_

2
3
10

INA
INB
R01
R02
GND

VCC
QA
QB
QC
QD

R1
100

74LS93D

RST

14
1

OUT

THR

V1
5V

TRI
CON

2
3
10

INA
INB
R01
R02
GND

VCC
QA
QB
QC
QD

5
12
9
8
11

74LS93D

GND

7400N

U4C

_
2.5 V2.5 V2.5 V2.5
+ V

U3

DIS

R2
10k
0%
Key=A

U5B

C2
.01F

Ext Trig
+
B

VCC

GND

C1
100F

X1 X2 X3 X4

U1
555_TIMER_RATED

5
12
9
8
11

C1
100F

U6C
7400N
7400N

U2A

U5B

C2
.01F

7400N

U4C

LED1

U6C
7400N

7400N

7400N

U2A

LED1

7400N

011
110
XSC1
X1 X2 X3 X4

U1
555_TIMER_RATED

Ext T rig
+
_

RST

14
1

OUT

DIS

R2

THR

V1
5V

TRI

10k
0%
Key=A

CON

2.5 V2.5 V2.5 V2.5

_
+ V

U3

VCC

2
3
10

INA
INB
R01
R02
GND

VCC
QA
QB
QC
QD

XSC1

R1
100

5
12
9
8
11

R1
100

74LS93D

OUT

DIS
THR

V1
5V

TRI

10k
0%
Key=A

U5B

C2
.01F

CON

2.5 V2.5 V2.5 V2.5

_
+ V

U3

VCC
RST

R2

14
1

INA
INB

2
3
10

R01
R02
GND

VCC 5
QA 12
QB 9
QC 8
QD 11

74LS93D

GND

U4C
7400N
U2A
7400N

7400N
C1
100F

U6C

U5B

C2
.01F
U4C

7400N

LED1

7400N
U6C

7400N
U2A
7400N

101

Ext Trig
+
B

GND

C1
100F

X1 X2 X3 X4

U1
555_TIMER_RATED

7400N

LED1

LED1

001

XSC1
X1 X2 X3 X4

U1
555_TIMER_RATED

Ext T rig
+
_
B

R1
100

U3

VCC
RST

14
1

OUT

DIS

R2

THR

V1
5V

TRI

10k
0%
Key=A

2.5 V2.5 V2.5 V2.5

_
+ V

CON

2
3
10

INA
INB
R01
R02
GND

VCC
QA
QB
QC
QD

5
12
9
8
11

74LS93D

GND

C1
100F

U5B

C2
.01F

7400N

U4C

U6C

7400N

7400N

U2A

LED1

7400N

XSC1
X1 X2 X3 X4

U1
555_TIMER_RATED
R1
100

14
1

OUT

DIS

R2

THR

V1
5V

TRI

10k
0%
Key=A

CON

_
2.5 V2.5 V2.5 V2.5
+ V

U3

VCC
RST

Ext T rig
+
B

2
3
10

INA
INB
R01
R02
GND

VCC
QA
QB
QC
QD

5
12
9
8
11

74LS93D

GND

C1
100F

U5B

C2
.01F
U4C

7400N
U6C

7400N

7400N

U2A

LED1

7400N

TRUTH TABLE BY KARNAUGH MAP (BOTH ORIGINAL AND SIMPLIFIED)

00
YZ
X
0

01

11

10

CONCLUSION

B. Boolean Function
OBJECTIVES

To implement the boolean functions by using only the NAND gates.

To check if the simulation and the equation has the same truth value.
To minimize the use of ic in doing the boolean function.

Boolean Function (orignal)

SCHEMATIC
R2
80

A1
VCC
RST

V1
5V

U2

OUT

U1

DIS

R3

THR

14
1

TRI

10k
60%
Key=A

CON
GND

2
3
10

INA
INB
R01
R02
GND

VCC
QA
QB
QC
QD

C1
0.01F
C2

5
12
9
8
11

1A VCC
1B 4A
1Y 4B
2A 4Y
2B 3A
2Y 3B
GND 3Y

74LS00N
U3
1A VCC
1B 1C
2A 1Y
2B 3C
2C 3B
2Y 3A
GND 3Y

74LS10N

10F

SIMULATION

GRAPH

Boolean Function (Simplified)

(SCHEMATIC)
R2
80

A1
VCC
RST

V1
5V
U2

OUT

U1

DIS

R3

THR

14
1

TRI

10k
60%
Key=A

CON
GND

2
3
10

INA
INB
R01
R02
GND

C1
0.01F
C2
10F

(SIMULATION)

(GRAPH)

VCC
QA
QB
QC
QD

5
12
9
8
11

1A
1B
1Y
2A
2B
2Y
GND

VCC
4A
4B
4Y
3A
3B
3Y

74LS00N

00

01

11

10

CD
AB
00

01

11

10

F1= C + ABD -> [C(ABD)]

00

01

11

10

CD
AB
00

01

11

10

F2= BD + BCD + ABD -> [(BD)(BCD)(ABD)]

B. COMPLEMENT
OBJECTIVES

To implement the complement of the given Boolean function using the

NAND gates.
To verify its truth table using simulation.
To apply the concept discussed.

TRUTH TABLE BY KARNAUGH MAP (COMPLEMENT)

00

01

11

10

CD
AB
00

00

01

00

11

00

10

00

F=D + BC

-> [D(BC)]

F= CD + BD -> [(CD)(BD)]

SCHEMATIC

(SIMULATION)

(GRAPH)

(TRUTH TABLE)

Truth Table
(COMPLEMENT)
B F C B
- D
C 1 D

0 0 1 0
0 1 0 0
1 1 0 0
1 1 0 0
0 0 1 1
0 1 0 0
0 0 0 1
0 1 0 0
0 0 1 0
0 1 0 0
1 1 0 0
1 1 0 0
0 0 1 1
0 1 0 0
0 0 0 1
0 1 0 0

F
2

1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0

CONCLUSION

Logic Diagram can be done even if there is only a NAND gate.

The original and simplified version will always have an equal output.
The use of NAND gates can be minimized.