reg [3:0] count; // clock divider counter

reg
clk_div; // clock divider output
always @ (posedge clock_in)
begin
if (count==4'b1001) // divide by 10
count <= 4'b0000; // reset to 0
else count <= count+1; // increment counter
clk_div <= (count == 4'b0000); // counter decoded, single cycle pulse is
generated
end