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New

homework to be posted this weekend

Last one to be graded

Project

Phase 3 Launched Next We

Some insights today

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Last

lecture

Adders
Todays

lecture

Multipliers
Introduction to Memory
Reading

(Ch 11)

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Critical Path 1 & 2

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Balanced tsum and tcarry

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Optimization

constraints different than in

binary adder
Once again:
Need to identify critical path
And find ways to use parallelism to reduce it
Other

possible techniques

Logarithmic versus linear (Wallace Tree Mult)

Data encoding (Booth)
Pipelining

First glimpse at system level optimization

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Area Dominated by Wiring

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Widthbarrel ~ 2 pm M
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Out3

Out2

Out1

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Out0

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Intel 45nm Core 2

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Read-Write Memory

Random
Access

Non-Random
Access

SRAM

FIFO

DRAM

LIFO

Non-Volatile
Read-Write
Memory
EPROM
2

E PROM

Read-Only Memory

Mask-Programmed
Programmable (PROM)

FLASH

Shift Register
CAM

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STATIC (SRAM)
Data stored as long as supply is applied
Larger (6 transistors/cell)
Fast
Differential (usually)

DYNAMIC (DRAM)
Periodic refresh required
Smaller (1-3 transistors/cell)
Slower
Single Ended
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Conceptual: linear array

Each box holds some data
But this does not lead to a nice layout shape
Too long and skinny

Create a 2-D array

Decode Row and Column
address to get data

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M bits
S0
S1
S2

N
words

SN-2
SN -1

M bits
S0

Word 0
Word 1
Word 2

Storage
cell

A0
A1
A K-1

Word N-2
Word N-1

D
e
c
o
d
e
r

Word 0
Word 1
Word 2

Storage
cell

Word N-2
Word N-1

K = log2N
Input-Output
( M bits)

Input-Output
( M bits)

Intuitive architecture for N x M memory

Too many select signals:
N words == N select signals

Decoder reduces the number of select signals

K = log2N

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Collection of 2M complex logic gates

Organized in regular and dense fashion
(N)AND Decoder

NOR Decoder

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Look

at decoder for 256x256 memory

block (8KBytes)

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Goal:

Build fastest possible decoder with

static CMOS logic

What

we know

Basically need 256 AND

gates, each one of them
drives one word line

N=8

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Each

word line has 256 cells connected to it

Total output load is 256*Ccell + Cwire
Assume that decoder input capacitance is
Caddress=4*Ccell
Each

address drives 28/2 AND gates

A0 drives of the gates, A0_b the other of the

gates
Neglecting

Cwire, the fan-out on each one of the

16 address wires is:
B

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FB

of at least 213 means that we will want to

use more than log4(213) = 6.5 stages to
implement the AND8

Need

many stages anyways

So what is the best way to implement the AND

gate?
Will see next that its the one with the most stages
and least complicated gates

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LE=10/3
1
LE = 10/3
P= 8 + 1

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LE=2
5/3
LE = 10/3
P=4 + 2

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LE=4/3
5/3
4/3
1
LE = 80/27
P= 2 + 2 + 2 + 1

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Using

2-input NAND gates

8-input gate takes 6 stages

Total

LE is (4/3)3 2.4
So PE is 2.4*213 optimal N of ~7.1
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8-input AND gates

Each built out of

tree of NAND gates
and inverters
Issue:

Every address line has

to drive 128 gates (and
wire) right away
Cant build gates small enough - Forces us
to add buffers just to drive address inputs
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Use

a single gate for each of the shared

terms
E.g., from A0, A0, A1, and A1, generate four
signals: A0A1, A0A1, A0A1, A0A1

In

other words, we are decoding smaller

groups of address bits first
And using the predecoded outputs to do
the rest of the decoding

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