library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter4 is
port(
ck: in std_logic;
clr: in std_logic;
cnt: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end counter4;
architecture Behavioral of counter4 is
component counterc
generic(
n: natural :=2
);
port(

clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q:
out std_logic_vector(n-1 downto 0)

);
end component;

begin
cnt1:counterc generic map(4) port map(ck,clr,cnt,q);