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Nanoparticle Based Charge Trapping Memory Device Applying Mos Technology A Cognitive Approach Using Polyvinyl Alcohol Capped Zinc Oxide Nanocrystal
Nanoparticle Based Charge Trapping Memory Device Applying Mos Technology A Cognitive Approach Using Polyvinyl Alcohol Capped Zinc Oxide Nanocrystal
ISSN: 2319-1163
Abstract
Development of data storage device using semiconductor based technology has always been gaining significant interests from the
researchers engaged in this field. The scope of research in this field was further enhanced by the introduction of nano particle based
techniques. Metal-Oxide-Semiconductor (MOS) structure provides the primary guidance in developing such devices. Design of a low
cost nano particle based Charge trapping memory device will be described which is expected to have superior characteristics than
the conventional ones. The basic idea behind the proposed device is to find out a way to replace the continuous polysilicon floating
gate of the flash cells with discrete nano crystal layer by using a Polyvinyl alcohol (PVA) capped ZnO nano particles. The basic
structure of the memory cell is analogous to the charge trapping MOS transistor except the charge trapping layer being replaced by
discrete nano particles. This will allow reducing the thickness of the tunneling oxide without effecting the endurance, reliability and
performance of the device.
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ISSN: 2319-1163
3. NANOPARTICLES
Use of nanoparticles for design of memory devices
Use of nanoparticles for memory device has greatly been
encouraged in recent days because of the fact that when we
use gate dielectrics embedded with nanocrystals the charge
leaking to the tunneling oxide layer is reduced significantly
and thus enhances the retention period of the device.
Demonstrative evidences are available in literature to explain
the novelty of such devices and currently significant research
activities in this field are underway.[7] Quasi nonvolatile
Metal Oxide Semiconductor (MOS) memory devices are
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Volume: 02 Issue: 01 | Jan-2013, Available @ http://www.ijret.org
40
ISSN: 2319-1163
4. DISCUSSIONS
A. Retention Period
B. Scalability
It is anticipated that the use of discrete nanoparticles for
charge trapping might allow reduction in the thickness of the
tunneling oxide layer and the device with 5nm oxide thickness
has been fabricated.[10] Since the charges are trapped in the
discrete nanoparticles even a pinhole in the tunneling oxide
wont cause all the trapped to leak off and the defect will be
highly localized. This reduction in the oxide layer allows the
shrinkage of the device thus more number of memory cells
can be fabricated on the given chip. This helps to increase the
storage capacity manifold.
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41
[3]
[4]
[5]
[6]
CONCLUSIONS
From the overall discussions it is anticipated that the proposed
memory device is expected to be an efficient device compared
to other devices reported so far. Further, this might
significantly improve the retention period as well as
programming speed of the proposed device. This is expected
because use of thinner tunnel oxide is proposed for the device
and additionally use of nanoparticles is expected to
dramatically improve both the factors namely the Retention
Period and Programming Speed. Another important aspect
of the proposed device is that it is expected to operate at lower
voltage which might ensure enhanced reliability and life of the
device.
[8]
[9]
[10]
ACKNOWLEDGMENTS
The authors would like to thank Dr. Saurabh Chaudhury,
Associate Professor, Department of Electrical Engineering,
National Institute of Technology Silchar for discussions on
various topics and Dr. V. Ramachandran, Director, National
Institute of Technology Nagaland for his all encouragement
and support during the overall completion of the project.
REFERENCES
[1]
[2]
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ISSN: 2319-1163
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