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A 12 Bit 8 47 FJ Conversion Step 1 Ms S Sar Adc Using Capacitor Swapping Technique
A 12 Bit 8 47 FJ Conversion Step 1 Ms S Sar Adc Using Capacitor Swapping Technique
A 12 Bit 8 47 FJ Conversion Step 1 Ms S Sar Adc Using Capacitor Swapping Technique
6-3
I.
INTRODUCTION
CP11,1
CP11,2
CP11,3
CP11,1=CP10
CP11,2=CP9
CP11,3=CP9C
V2P
VREF
3R
GND
VREF/4
VREF
GND
CKs
CP11
CP10
CP9
CP9C
CP8
CP7
CP6
CP6C
CP5
CP4
CP3
CP3C
CP2
CP1
CP0
V1P
V1N
Bootstrapping
switch
CP0C
Configurable
Comparator
V2P
dc
V2N
SAR
valid Control Unit
ckc
CN11
CN10
CN9
CN9C
CN8
CN7
CN6
CN6C
CN5
CN4
CN3
CN3C
CN2
CN1
CN0
VREF
CN0C
Variable Delay
Time Control
VREF/4
GND
157
CKs
LN_mode
CKi
12
Dout
CAPACITOR-SWAPPING TECHNIQUE
S3 S2
S3 S1
S3 S0
S2 S3
S1 S3
S0 S3
0 1
0 1
0 1
0 1
0 1
0 1
swap
SW3
VREF
C3
SW3A V
REF
SW3B V
REF
C3B
C3A
SW3C V
REF
C3C
SW2
SW1
VREF
C2
VREF
C1
SW0
C0
V2P
(a)
k-th
sample
3b capacitor-swapping DAC.
C3A
C3B
C3C
VREF
VREF VREF
C2
C1
C0
V2P
(k+1)-th
sample
C2
C1
C0
VREF
VREF VREF
C3A
C3B
C3C
V2P
(b)
(a)
Capacitor-swapping off.
(b)
Capacitor-swapping on.
158
VDD
ckc
M13 M7
M8
M14
von
outp
M0
outn
vop
I0
V2P
M1
VDD
V2N
M2
vop
M10 M16
vn
vp
von
Cp
Cn
LN_mode
M15 M9
vop
von
VDD
M5
M3
ckc
M4
M6
CKi
LN_mode vop
VTDC
ckc
outp
outn
von
M12
M11
Latch
dC
valid
CIRCUIT IMPLEMENTATION
MEASUREMENT RESULT
159
TABLE I.
Specification (Unit)
This work
[2]
[3]
0.9
1.0
1.2
0.9
0.0165
0.025
3.02
0.32
0.1
22.5
10
SNDR (dB)
67.3
65.3
71.1
61.34
SFDR (dB)
87
71
90.3
70.83
Power (mW)
Sampling rate (MS/s)
DNL/INL (LSB)
0.4/0.56
0.66/0.68
NA
0.4/0.65
3.1
NA
3.6
1.3
FOM (fJ/conv.-step)
8.47
165
51.3
32.4
12
12
12
11
0.092
0.63
0.09
0.06
Technology (nm)
110
180
130
90
Resolution (bit)
[1]
CONCLUSION
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
160