SET URRCTRLSWITCH:LOGICRNCID=401, PROCESSSWITCH=INVOKE_TRACE_SWITCH-0&SYS_INFO_UPDATE_FOR_IU_RST-0&DRNC_DIRECT_DSCR0&PTUSER_IDENTIFY_ENH_SWITCH-0&RNC_SHARE_SWITCH-1&RNCAP_IMSI_HO_SWITCH-0&TERMINAL_VERSION_DEBASE_SWITCH0&SYS_HO_OUT_CIPHER_SWITCH-0&SYS_HO_CIPHER_CONFIG-1&BARRED_CELL_FOR_CSDOMAIN_RST-0&CR2284R1_SWITCH0&CDT_MSG_FULL_TRACE-0&CR2284R1_COMPATIBLE_SWITCH-1&COMBINE_OPERATION_DRD_SWITCH-1&UL_INTER_PROTECT_SWITCH0&FAST_DORMANCY_SWITCH-0&SYS_HO_IN_CIPHER_SWITCH-0&PTT_EARLY_TRANS_SWITCH_OFF-0&UPLINK_MDC_ENHENCEMENT_SWITCH0&NODEB_PRIVATE_INTERFACE_SWITCH-0&PTT_SPEC_LI_SWITCH_OFF-0&RNC_DF_2_URA_PCH_SWITCH-0&FD_TAC_MATCH_SWITCH0&NONPTT_L1_FAST_SYNC_SWITCH-0&URAPCH_LAYERED_PAGING_RT_SWITCH-0&URAPCH_LAYERED_PAGING_NRT_SWITCH0&IDLE_LAYERED_PAGING_NRT_SWITCH-0&IDLE_LAYERED_PAGING_RT_SWITCH-0&INTELLIGENT_WIFI_DETECT_AND_SELECTION0&INTERRAT_LOAD_REPORT_FOR_LTE_SWITCH-0&PTUSER_IDENTIFY_SWITCH-0, RSVDPARA1=RSVDBIT1_BIT1-0&NAS_QOS_MOD_SWITCH0&RSVDBIT1_BIT3-0&RSVDBIT1_BIT4-0&RSVDBIT1_BIT5-0&RSVDBIT1_BIT6-0&RSVDBIT1_BIT7-0&RSVDBIT1_BIT8-0&RSVDBIT1_BIT90&RSVDBIT1_BIT10-0&RSVDBIT1_BIT11-0&RSVDBIT1_BIT12-0&RSVDBIT1_BIT13-0&RSVDBIT1_BIT14-0&RSVDBIT1_BIT151&RSVDBIT1_BIT16-0&SYSHO_CSIN_PERMIT_SWITCH-1&RSVDBIT1_BIT18-1&RSVDBIT1_BIT19-1&RSVDBIT1_BIT20-1&RSVDBIT1_BIT211&RSVDBIT1_BIT22-1&RSVDBIT1_BIT23-1&RSVDBIT1_BIT24-1&RSVDBIT1_BIT25-1&RSVDBIT1_BIT26-1&RSVDBIT1_BIT271&RSVDBIT1_BIT28-1&RSVDBIT1_BIT29-1&RSVDBIT1_BIT30-1&RSVDBIT1_BIT31-1&RSVDBIT1_BIT32-1, RSVDPARA2=RSVDBIT1_BIT10&RSVDBIT1_BIT2-1&RSVDBIT1_BIT3-0&RSVDBIT1_BIT4-0&RSVDBIT1_BIT5-0&RSVDBIT1_BIT6-0&RSVDBIT1_BIT7-0&RSVDBIT1_BIT80&RSVDBIT1_BIT9-0&RSVDBIT1_BIT10-0&RSVDBIT1_BIT11-0&RSVDBIT1_BIT12-0&RSVDBIT1_BIT13-0&RSVDBIT1_BIT14-0&RSVDBIT1_BIT150&RSVDBIT1_BIT16-0&RSVDBIT1_BIT17-0&RSVDBIT1_BIT18-0&RSVDBIT1_BIT19-0&RSVDBIT1_BIT20-0&RSVDBIT1_BIT210&RSVDBIT1_BIT22-0&RSVDBIT1_BIT23-0&RSVDBIT1_BIT24-0&RSVDBIT1_BIT25-0&RSVDBIT1_BIT26-0&RSVDBIT1_BIT270&RSVDBIT1_BIT28-0&RSVDBIT1_BIT29-0&RSVDBIT1_BIT30-0&RSVDBIT1_BIT31-0&RSVDBIT1_BIT32-0, RSVDPARA3=RSVDBIT1_BIT11&RSVDBIT1_BIT2-1&RSVDBIT1_BIT3-1&RSVDBIT1_BIT4-1&RSVDBIT1_BIT5-1&RSVDBIT1_BIT6-1&RSVDBIT1_BIT7-1&RSVDBIT1_BIT81&RSVDBIT1_BIT9-1&RSVDBIT1_BIT10-1&RSVDBIT1_BIT11-1&RSVDBIT1_BIT12-1&RSVDBIT1_BIT13-1&RSVDBIT1_BIT14-1&RSVDBIT1_BIT151&RSVDBIT1_BIT16-1&RSVDBIT1_BIT17-1&RSVDBIT1_BIT18-1&RSVDBIT1_BIT19-1&RSVDBIT1_BIT20-1&RSVDBIT1_BIT211&RSVDBIT1_BIT22-1&RSVDBIT1_BIT23-1&RSVDBIT1_BIT24-1&RSVDBIT1_BIT25-1&RSVDBIT1_BIT26-1&RSVDBIT1_BIT271&RSVDBIT1_BIT28-1&RSVDBIT1_BIT29-1&RSVDBIT1_BIT30-1&RSVDBIT1_BIT31-1&RSVDBIT1_BIT32-1,

PROCESSSWITCH2=LOAD_IRAT_HO_RNC_FILL_TL-0&SEND_IDT_JUDGE_IU_RESET-0&RNC_RBRECFG_DRD_FAIL_ROLLBACK_SWITCH1&RNC_CS_QUERY_UE_IMEI_SWITCH-0&RNC_PS_QUERY_UE_IMEI_SWITCH-1&FACH_DTCH_CONGEST_P2D0&RNC_RBSETUP_DRD_FAIL_ROLLBACK_SWITCH-1&PS_NOTIFYCN_NOTDOWNSIZE_SWITCH-0&ASU_RSP_TIMEOUT_HANDLE_SWITCH1&RB_RECFG_USER_INACT_SWITCH-0&RRC_SCRI_NORM_REL_SWITCH-0&CELLUPT_RLFAILURE_SRBREESTAB_SWITCH0&CU_OVERLAP_DSCR_SWITCH-0&TRB_RST_DSCR_SWITCH-0&RNC_FD_SCRI_FORCE_REL_SWITCH-0&USRPLN_PRORATION_SHARED_ALO0&FP_IUUP_TRACE_SWITCH-1&RNC_PCHR_OUTPUT_CTRL_SWITCH-1&DTMF_SWITCH-1&FAST_CS_FB_BASEDON_RIM_SWITCH0&L2U_SRVCC_WITH_PS_HO_SWITCH-0&ULTRA_FLASH_CSFB_SWITCH-0&RNC_PS_QUERY_UE_IMEISV_SWITCH-0,
PROCESSSWITCH3=FACH_DCCH_CONG_CTRL_SWITCH-0&RNC_F2D_RLC_SUSPEND_SWITCH-0&UM_RRCRELCMP_RLDEL_DELAY_SWITCH1&RNC_TVM_BASED_P2D_SWITCH-0&CS_RLFAIL_RRCSETUP_STAT_SWITCH-0&PS_INACT_NOTREL_FOR_CSPS_SWITCH1&RAB_DL_BITRATE_MOD_SWITCH-0&RAB_WAIT_IUUP_INIT_RESPONSE_SWITCH-0&CS_CALL_DROP_DEFINITION-0&PS_CALL_DROP_DEFINITION0&CCH_ABNORMOLREL_CAUSE_SWITCH-0&RNC_U2U_SWITCH-0&INTERRAT2U_RESUME_PS_ASAP_SWITCH-0&UE_TRB_RESET_IOT_SWITCH1&CUC_CMP_NO_ACTIVE_CFN_SWITCH-0&RNC_RDY_FOR_INTERRAT_COMPATIBLE_SWITCH-0,
PROCESSSWITCH4=PS_F2D_OVERLAP_CELLUPT_SWITCH-0&AMR_HHO_FAIL_ROLLBACK_SWITCH-1&PHY_RECFG_REEST_SWITCH0&IUR_RL_REEST_SWITCH-0&RB_SETUP_RL_REEST_SWITCH-0&RRC_CONN_SETUP_OPT_SWITCH-1&TCP_ACK_ACCELERATOR_SWITCH0&RRC_CELLFACH_TRB_RESET_TO_F2D_SWITCH-0&SEND_MSG_NULL_SWITCH-0&FD_PCH_IUR_CS_OPT_SWITCH0&CELLUPT_T314_T315_TIMEOUT_OPT_SWITCH-0&CS_HHO_ASYNC_CTRL_SWITCH-0&PS_HHO_ASYNC_CTRL_SWITCH0&IUR_HHO_ASYNC_CTRL_SWITCH-0&F2P_DATATRANS_OPTIMIZE_SWITCH-0&IRATHO_HOCANCEL_RL_REEST_SWITCH0&TRB_RESET_RL_REEST_SWITCH-0&RB_REL_RL_REEST_SWITCH-0&RB_SETUP_ENHANCE_RL_REEST_SWITCH-0&RAB_SETUPMOD_CNT_FIX_SWITCH0&PCH_UE_RLC_UNRECOVERABLEERROR_SWITCH-0&FAST_RETURN_LTE_BY_CELL_SELECT_SWITCH-0&UL_DUAL_MODE_UE_D2P_OR_D2I_SWITCH0&PHYCHRECFG_ENH_RL_REEST_SWITCH-0&RBRECFG_ENH_RL_REEST_SWITCH-0&SMC_STOP_RLC_SWITCH1&GTP_SN_IN_RAB_REL_INIT_BY_UTRAN_SWITCH-1&CMP_IU_QOS_GTP_PDU_SN_SWITCH-0&DL_TRB_RESET_BUFF_SWITCH0&RRC_CELLFACH_DL_TRB_RESET_TO_F2D_SWITCH-0&RAB_ASS_MOD_TNL_ADDR_SUP_SWITCH-1, RABDLBITRATE=0, CBSMSGID=5000,
IUBPRIVATEINTERFACESWITCH=RL_OpIndex_INCLUDED-0&PSCRR_OpIndex_INCLUDED-0, OPTIMIZATIONSWITCH=PAGGING_NUM_CTRL_SWITCH0&ASU_RL_RESET_SWITCH-0&MC_RL_RESET_SWITCH-0&FD_PCH_REENTERSA_FORCE_RRC_REL_SWITCH-0&UE_CRC_COMPATIBLE_SWITCH0&RNC_P2D_DRD_SWITCH-0&P2D_SWITCH-0&AMR_F2D_OVERLAP_CELLUPT_SWITCH-1&SRB_RESET_RL_SETUP_SWITCH0&RLFAIL_RL_SETUP_SWITCH-0&CS_RL_SETUP_SWITCH-0&PS_RL_SETUP_SWITCH-0&UE_SRB_RESET_SWITCH-1&RL_RESTORE_SWITCH0&RNC_EFD_D2F_SWITCH-1&RNC_RB_SCRI_NOT_DROP_SWITCH-1&RRC_RECONN_SWITCH-0&RRC_REPEAT_PFM_SWITCH1&F2D_NO_RSP_RRCREL_SWITCH-0&CS_SETUP_P2D_SWITCH-1&SYSHO_CIPHER_IE_SWITCH-0&P2P_GTPU_NOT_CFG_SWITCH1&RB_SETUP_CIPHER_TIME_ADJ_SWITCH-1&CS_PRI_MOD_NOT_INT_SWITCH-0&RAB_SETUP_TMSI_REALLOC_BUF_SWITCH0&IU_FAULT_REL_PS_RES_SWITCH-0&RB_RECFG_RL_REEST_SWITCH-0&F2P_DT_MSG_BUFFER_SWITCH-0&SCRI_COMPATIBLE_SWITCH0&GTPU_ERR_IND_DEF_SWITCH-1&IUR_SRV_CELL_CHG_MACHS_RESET_SWITCH-1&UL_INTEG_ALGO_COMPAT_SWITCH-0,
OPTIMIZATIONSWITCH2=DRNC_DCH_RCV_CELL_RESEL_MSG_DSCR_SWITCH-0&MULTIRAB_ATTESTAB_DEF_SWITCH0&PCH_UE_SRB_RESET_DSCR_SWITCH-0&DRNC_CELL_CODE_CONFLICT_OPT_SWITCH-0&RAB_FAIL_CAUSE_SWITCH0&PSPS_SETUP_REL_DEF_SWITCH-0&RRC_CON_REQ_TIMES_COMPATIBLE_SWITCH-0&SECU_CU_CROSS_SWITCH-1&HHO_CNT_CORRECT_SWITCH0&IRATHO_CNT_CORRECT_SWITCH-1&RB_CU_CROSS_COMPATIBLE_SWITCH-0&RNTI_ENH_ALLOC_AlGO_SWITCH-0&DRNC_LOAD_CTRL_SWITCH1&EFACH_CU_COMMON_HRNTI_SWITCH-1&PSCS_CALLDROP_FIX_SWITCH-1&CSABNREL_DUETO_PSREL_FIX_SWITCH-1,
FUNCTIONSWITCH=RRC_CONN_STATE_TO_NODEB_SWITCH-0&CS_SECMODE_PRI_CSPS_SWITCH-0&AMR_SILENT_DETECT_SWITCH1&IU_FLEX_CONG_DISCARD_SWITCH-0&UL_INTEG_ALGO_FOR_CELLUPDATE_SWITCH-0&AMRWB_SILENT_DETECT_SWITCH-0,
CELLPCHMAXPAGINGTIMES=5, URAPCHMAXPAGINGTIMES=5, OPTIMIZATIONSWITCH3=SYS_RELOC_OUT_SUCC_STAT_OPT_SWITCH1&RL_REEST_PS_ON_FACH_SWITCH-0&CELLUPDATE_MEASUREMENT_OPT_SWITCH-0&D2F_PROCEDURE_OPTIMIZATION_SWITCH1&F2D_PROCEDURE_OPTIMIZATION_SWITCH-0&FOREVER_PCH_CTRL_PLANE_SHARE_OPT-0&FOREVER_PCH_USER_PLANE_SHARE_OPT0&RAB_REL_SRV_CELL_CHG_CROSS_SWITCH-0&SCRIWITHCAUSE_OVERLAP_SWITCH-0&P2F_CUC_REPEAT_SWITCH0&UU_ABN_REL_INFO_NOTIFY_NODEB_SWITCH-0&D2F_AM_PROCEDURE_OPTIMIZATION_SWITCH-1&AM_D2F_F2D_RESTMR_OPTIMIZATION_SWITCH0&D2P_DT_MSG_BUFFER_SWITCH-0&CM_CODE_CONFLICT_OPT_SWITCH-1&H_SERV_CELL_CHANGE_MSG_OPT_SWITCH0&FAST_HSDPA_SERV_CELL_CHANGE_SWITCH-0&RLRST_ASU_SUCC_COUNTERS_CORRECT_SWITCH-0&COUNT_STATE_CHG_BY_RAB_EHN_SWITCH0&RAB_RELATED_COUNTER_OPT_SWITCH-0&CELLUPDATE_PROCEDURE_OPT_SWITCH-1&PTT_PAGING_PRD_CRRCT_SWITCH0&RRC_REL_STATUS_RSP_RAB_ASS_REQ_SWITCH-0&L2U_UP_DELAY_OPT_SWITCH-1&PRI_LDR_SYSHO_OUT_USE_SELECT_OPT_SWITCH-0,
NBDLAMRNOISEDETECTRATIO=0, WBDLAMRNOISEDETECTRATIO=0, IMPROVEMENTSWITCH=CONVERT_RELOC_FAIL_CAUSE_SWITCH0&DEAL_SRNS_CONTEXT_REQ_FIRST_SWITCH-0&DELAY_DRNC_CODE_REL_SWITCH-0&ROUT_IDT_BY_ROUTING_PARA_SWITCH0&COUNT_CS_REC_IU_REL_CMD_SWITCH-1&SEND_UE_CAP_ENQ_RELOC_CCH_SWITCH-0&REL_IUR_CCH_BEFORE_DSCR_SWITCH0&RELOC_CIPHER_PENDING_COMPATI_SWITCH-0&COUNT_SPECIAL_RAB_ATT_SWITCH-0&COUNT_STATE_CHG_BY_RAB_SWITCH0&DELAY_SEND_MEACTRL_SWITCH-0&TAKE_ACTIVE_TIME_DRD_SWITCH-0&CS_DISCONNECT_OPT_SWITCH0&NON_DCCC_RBRECFG_RL_REEST_SWITCH-0&SMC_RL_REEST_SWITCH-0&PSHO_CSFB_UE_CAP_ENQ_DELAY_SWITCH0&PAGING_OM_OPTIMIZE_SWITCH-0&DEACTIVE_CELLHSPA_H2F_SWITCH-0&OMIT_UE_CAP_ENQ_RELOC_DCH_SWITCH0&RAB_SETUP_CNT_CORRECT_SWITCH-1&FACH_DCCH_RRC_REL_NO_RSP_DELAY_USE_URNTI-0&FACH_CCCH_RRC_REL_NO_RSP_DELAY_USE_URNTI0&DCH_DISCARD_CELL_RESEL_CU_MSG_SWITCH-0&SYS_INIT_SPU_STATE_BROADCAST_OPT_SWITCH1&RB_RECFG_F2D_ISR_IC_FAIL_RRC_REL_SWITCH-0&PTT_RAB_SETUP_ATT_CNT_CORRECT_SWITCH0&P2D_DRD_FAIL_BACK_RESEL_CELL_SWITCH-0&TRB_RST_CU_NOT_REEST_UM_RLC_TRB_SWITCH0&ONE_CNNODE_SCCP_CONG_SEL_OTHER_SWITCH-1&CSFB_UE_DELAY_RAU_SWITCH-0&CSFB_UE_CS_IMEI_QUERY_DISABLE_SWITCH-0,
PROCESSSWITCH5=INTERRAT_LOAD_SINGLE_RPT_FOR_LTE_SWITCH-0&INTERRAT_LOAD_REPORT_FROM_LTE_SWITCH-0&UL_EVQI_SWITCH0&DL_EVQI_SWITCH-0&VIDEO_RATE_ADAPTION_SWITCH-0&VOIP_MANAGE_SWITCH-0&DIFF_SERVICE_ON_TERMINAL_SWITCH0&APP_GRP_RES_RSV_SWITCH-0&RIM_ON_ECO_SWITCH-0&SRBCHG_DRD_FAST_RB_SETUP_SWITCH-0&SRBNOCHG_DRD_FAST_RB_SETUP_SWITCH0&FACH_RB_RECFG_FAIL_SPEC_CAUSE_SWITCH-0&WBAMR_HHO_FAIL_ROLLBACK_SWITCH-0, PCHRRCRELREPAGINGTYPE1NUM=3,
OPTIMIZATIONSWITCH4=RB_RLREEST_AM_TRB_RLC_REEST_SWITCH-0&RB_SETUP_UM_TRB_RLREEST_ADJUD_OPT_SWITCH0&DRNC_RL_REEST_OPT_SWITCH-1&URA2FACH_OVERLAP_CELLUPT_PROC_SWITCH-0&RB_SETUP_F2D_USE_AM_RLC_SWITCH0&RB_RECFG_D2F_USE_AM_RLC_SWITCH-1&RB_RECFG_F2D_USE_AM_RLC_SWITCH-1&RRC_UE_USER_SMOOTH_OPT_SWITCH1&TRNC_LOAD_CTRL_SWITCH-0&IU_SIG_REL_PCH_PAGING_SWITCH-0&CPC_OPT_FOR_RLSETUP_SWITCH-1&D2P_L2DEACT_FAIL_OPT_SWITCH0&EFACH_RRC_REG_CMP_SWITCH-0&P2D_TSID_ERR_UE_RSP_MSG_DISCD_SWITCH-0&AMRC_ON_122_AMR_HHO_ROLL_BACK_SWITCH0&RELOC_IN_RG_COMB_INDEX_ALLOC_SWITCH-0&SCM_CU_CROSS_SWITCH-0&DRNC_HSPA_CM_OPT_SWITCH-0&IUB_TRANSID_OPT_SWITCH0&L2_ENHENCE_RECFG_OPT_SWITCH-0&ASYN_RL_REEST_OPT_SWITCH-0&RNC_IMSI_HO_OPT_SWITCH-

0&IUR_PRIQUEUE_INFO_TO_MODIFY_OPT_SWITCH-0&URA_PCH_LAC_RAC_CHG_NO_PAGING_SWITCH-0&PAGING_OVERLAP_CU_OPT_SWITCH0&SRVCC_RELOC_IN_USE_CS_KEY_SWITCH-1&SOCKET_RECEIVE_DATA_CORRECT_SWITCH-1&CU_PRI_OVERLAP_OTHER_PROC_SWITCH0&INTERRAT2U_INTEG_PROTECT_OPT_SWITCH-0&INTRA_NODEB_RLCC_INIT_CAP_OPT_SWITCH-0&DRNC_RL_PARA_UPT_OPT_SWITCH-1,
OPTIMIZATIONSWITCH5=U2L_RELOC_MSG_TAKE_ERAB_SWITCH-0&PS_DOMAIN_REL_RAB_SETUP_SWITCH0&PCH2FACH_PS_TRAFFIC_PFM_FIX_SWITCH-0&GSM_SYS_HO_IN_NO_UE_CAP_ENQ_SWITCH-0&D2P_TWO_SIDE_RLC_REEST_SWITCH0&D2F_SRNS_CONTEXT_REQ_OPT_SWITCH-0&DL_SIG_TRS_REQ_REL_UE_PRO_SWITCH-1&DSP_CAP_JUDGE_SWITCH1&MPU_FC_USER_PLN_RSR_CHK_SWITCH-1&RB_CU_FAIL_RRC_REL_CELL_OPT_SWITCH-0&RB_RFG_MSG_USE_NEW_SG_SWITCH0&SRB3_SRB4_RLC_RST_RRC_REL_SWITCH-0&WEAK_COV_NO_EXT_CS_RAB_SET_ACT_TM_SWITCH-0&PS_0K_STATIC_RELOC_IN_CMP_SWITCH0&ADD_DRL_PS_0K_TO_8K_SWITCH-0&CU_AL_RES_OPT_SWITCH-0&DRNC_SERV_CELL_CHG_BUGFIX_SWITCH-0&TRNC_TPC_INDEX_ALLOC_SWITCH0&IUR_ATM_TRAN_OPT_SWITCH-0&RELOC_REQ_CIPHER_COMP_SWITCH-0&STATIC_RELOC_FAIL_DRNC_CLR_RSR_SWITCH0&RNC_IN_POOL_IU_RESET_SWITCH-1&USE_EFD_WITHOUT_EFD_OFF_TAC_SWITCH-1&RAB_MOD_IUPS_ADMIFAIL_GTPU_REEST_SWITCH0&PS_U2L_USER_PLANE_DELAY_OPT_SWITCH-0&P2F_CU_CAUSE_CHG_OPT_SWITCH-0&P2F_REDIRECT_CELLUPDT_RESEND_OPT_SWITCH0&RELOC_IN_PROCESS_OPT_SWITCH-0&CU_ROUT_OPT_SWITCH-0, ULINTEGCHECKIGNORENUM=3,
OPTIMIZATIONSWITCH6=ASU_RSP_FAIL_REL_UE-0&CELL_PCH_UES_OPT_SWITCH-0&DRNC_NOTICE_NODEB_SRNC_VEST_SWITCH-0;