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Analytical Method DC Link Capacitor
Analytical Method DC Link Capacitor
M. N. Anwar
Mehrdad Teimor
Member, IEEE
Member, IEEE
NOMENCLATURE
Cc
Rc
Lc
Zc
Tcan
Ta
Rth(c-a)
Ri
Li
Icap
Icrms
Ip
Ic1- c6
Iq1, Id1
Ibat, Vbat
Iinv, V12
ia, ib, ic
%Irms
V12
Pi, Pf,
,T
f
s, D
I. INTRODUCTION
The dc-link-capacitor is a load-balancing energy storage
element between the dc (battery) and ac (load) sides of a VSI.
This component is connected parallel to the battery in order
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Iinv (A)
Ip
(a)
1/Ff
1/(6.Ff)
Ic1
Ic4
(b)
Id1 (A)
(c)
(d)
Ibat (A)
Iq1 (A)
(e)
time (s)
S5
Iinv (A)
Ia, Ic1, Ic4, (A)
S3
Ip
(a)
1/Ff
1/(6.Ff)
Ic1
Ic4
D1
Iq1 (A)
Id1
ia
Ph-a
Ph-c
ib
(c)
(d)
Ph-b
Ic4
S4
(b)
Id1 (A)
Iq1
Ic5
Fig. 2: General waveshapes of- (a) Iinv, which follows the envelop of
absolute ia, ib and ic, (b) ia, Ic1, Ic4 and iarms, (c) Id1 and Id1rms, (d) Iq1 and
Iq1rms, and (e) Ibat with a load power factor of 0.5 for PWM switching.
Ic6
S6
Ic2
ic
Load
Ibat (A)
S1
Dc-link-capacitor
Battery
Icap
Q1
Ic3
Leg-c
Iinv
Leg-a
Ibat
Ic1
Leg-b
(e)
S2
time (s)
Inverter
Fig. 1: Circuit diagram of a voltage stiff inverter (VSI) showing IGBTs (with
free-wheeling diode), battery, dc-link-capacitor and 3-phase load.
804
Fig. 3: General waveshapes of- (a) Iinv, which follows the envelop of
absolute ia, ib and ic, (b) ia, Ic1, Ic4 and iarms, (c) Id1 and Id1rms, (d) Iq1 and
Iq1rms, and (e) Ibat with a load power factor of 0.065 for PWM switching.
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Iinv (A)
(a)
1/Ff
Ic1
Ic4
(b)
Iq1 (A)
Ic4
Id1 (A)
(c)
Ibat (A)
(d)
(e)
time (s)
(a)
Ic4
Ic4
1/Ff
Ic1
1/(6.Ff)
Ic1
(b)
1.0
Iq1 (A)
Iinv (A)
Fig. 4: General waveshapes of- (a) Iinv, which follows the envelop of
absolute ia, ib and ic, (b) ia, Ic1, Ic4 and iarms, (c) Id1 and Id1rms, (d) Iq1 and
Iq1rms, and (e) Ibat with a load power factor of 0.6 for six-step switching.
(c)
Power Factor, Pf
Id1 (A)
0.5
Ibat (A)
(d)
0.0
-0.5
(e)
time (s)
IGBT Conductivity,
CQ
FWD Conductivity,
CD
Motoring
Ic1
0.1
Generating
1/(6.Ff)
0.2
0.3
0.4
0.5
0.6
0.7
-1.0
Fig. 5: General waveshapes of- (a) Iinv, which follows the envelop of
absolute ia, ib and ic, (b) ia, Ic1, Ic4 and iarms, (c) Id1 and Id1rms, (d) Iq1 and
Iq1rms, and (e) Ibat with a load power factor of 0.09 for six-step switching.
805
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Vbat
Cc
Ibat
Normalized Rc
-550
10
-400
1.0
25
850
0.1
102
10
Normalized Zc
Rc
Current source
Iinv
Lc
Ri
100
Dc-link
Li
Dc-link-capacitor
Battery
Dc-line
Icap
2
1.0
806
Normalized Cc
105
104
105
104
105
-400
250
0.1
850
102
103
1.0
104
-550
0.01
Fig. 7: Equivalent circuit diagram for the VSI of Fig. 1 replacing the power
switches with a current source.
103
-550
0.66
850
250
-400
0.33
0.0
102
103
Frequency (Hz)
6.Ff
2.Fs
Fs
12.Ff
(a)
Fs
2.Fs
6.Ff
(b)
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(1)
inv dc
( (
(2)
Fundamental
12.Ff
1.4
1.4
1.4
1.4
1.4
where,
I ()
bat
ac
Fs
22
47
73
127
151
2.Fs
20
38
43
44
46
.100
(4)
I
bat dc
Icrms = Rms
() = Rms
cap
PWM switching
18.Ff
0.6
0.6
0.6
0.6
0.6
(3)
I ()
= . sin( 6. .t + ) + . sin( 12. .t + ) +..........
..
bat
f1
f
f1
f2
f
f2
,
ac
Rms
86
77
67
48
38
%Irms =
A () + j.B () ,
I ( )
= I ()
.
bat
ac inv
ac C () + j.D ( )
90
80
70
50
40
B () = .R ().C ();
c
c
DC
s, 2. s, , Ms1, Ms2,
C () = 1 2. L () + L .C () and D () = . R () + R .C ().
c
i c
c
i c
Duty
ratio,
D (%)
A () = 1 2 .L ().C () ;
c
c
where,
I inv () = I
I ()
= M . sin( 6. .t) + M . sin( 12. .t) + M . sin( 18. .t) + ...
inv
f1
f
f2
f
f3
f
ac
A () + j.B ()
Ibat() = Iinv().
C () + j.D ()
,
V .C ()
bat c
+
2. R () + R .C () + j.. L () + L .C ()
c
i c
c
i c
where,
3.Fs
19
25
10
42
32
A () + j.B ()
() .
1
inv
ac C () + j.D ()
. (5)
b. Objective Function
As stated in Section I, the objective of putting the dc-linkcapacitor is to maintain a required amount of dc-line current
ripple (%Irms calculated by Eq. 4), which is set down by the
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Start
Iinv()|ac
Mf1.sin(6.f.t+0)
Mf2.sin(12.f.t+0)
Ms1.sin(s.t+0)
(a)
time(sec.)
Look-up table:
Find Cc, Rc and Lc = f (, T)
1/(6.Ff)
Ibat()|ac
f1.sin(6.f.t+f1)
f2.sin(12f.t+f2)
s1.sin(s.t+s1)
Calculation:
Solve Eqs.(4) and (5)
Plots:
%Irms vs. # of 'Cx' with Ri, Ff, T
etc. as constants.
Output: # of 'Cx' capacitor = 'x'
f1
(b)
No
time(sec.)
Fig. 10: General waveshape of the ac ripples on - (a) Iinv(A) and (b) Ibat(A)
with couple of their frequency components for PWM switching.
Plots:
Icrms vs. # of 'Cx' with Ri, Ff, T
etc. as constants.
Output: # of 'Cx' capacitor = 'x'
No solution found
within constraints
Yes
FFT of Iinv:
Find magnitudes and
frequencies of significant
components
(6)
808
No
Icrms Icmax ?
Yes
End
Fig. 11: Flowchart explaining the selection of dc-link-capacitor for a voltage
source inverter (VSI).
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(a)
(c)
Icmax
Fig. 13: Plots of (a) Ibat (A), (b) ia (A) and (c) total Icap (A) with time
(4ms/div) with 4x16 mF capacitance (Cc) at 88 Hz (Ff).
Fig. 12: Plots of %Irms and Icrms vs. number of capacitors with
Ri as a variable.
Experimental result
Ibat: 50 A/div
ia: 75 A/div
(b)
(c)
Fig. 14: Plots of (a) Ibat (A), (b) ia (A) and (c) total Icap (A) with time
(4ms/div) with (4x16 + 45) mF capacitance (Cc) at 88 Hz (Ff).
(a)
Analytical result
(4 x 16)= 64
%Irms
30%
Ierms
10
Itrms
40
%Irms
28.5%
Ierms
9.85
Itrms
39.4
(4 x 16 + 45)=109
18%
6.35
41.28
18.1%
6.2
40.3
V. CONCLUSIONS
The development of an analytical method for selecting dclink-capacitor for voltage stiff inverter (VSI) is discussed.
The effects of frequency, temperature, parasitic impedances,
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