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An023 Panel Instrmentos PDF
An023 Panel Instrmentos PDF
An023 Panel Instrmentos PDF
Application Note
AN023
Introduction
polarity features) it is only necessary to add display, 4
resistors, 4 capacitors, and an input filter if required (Figures
1 and 2).
The ICL7106 and ICL7107 are the first ICs to contain all the
active circuitry for a 31/2 digit panel meter on a single chip.
The ICL7106 is designed to interface with a liquid crystal
display (LCD) while the ICL7107 is intended for light-emitting
diode (LED) displays. In addition to a precision dual slope
converter, both circuits contain BCD to seven segment
decoders, display drivers, a clock and a reference. To build a
high performance panel meter (with auto zero and auto
A3 23
G3 22
BP 21
19 AB4
20 POL
C3 24
18 E3
G2 25
17 F3
V- 26
15 D3
16 B3
INT 27
14 E2
A-Z 29
BUFF 28
DISPLAY
13 F2
IN HI 31
IN LO 30
COM 32
CREF- 33
CREF+ 34
REF LO 35
TEST 37
REF HI 36
C3
TP4
R5
R
C2 2
C5
C1
9V
C4
OSC 3 38
OSC 2 39
OSC 1 40
R3
TP3
R1
R4
TP1TP2
TP5
IN
C1 = 0.1F
C2 = 0.47F
C3 = 0.22F
C4 = 100pF
C5 = 0.01F
R1 = 24k
R2 = 47k
R3 = 100k
R4 = 1k TRIMPOT
R5 = 1M
12 A2
11 B2
10 C2
9 D2
8 E1
7 G1
6 F1
5 A1
4 B1
3 C1
2 D1
1 V+
ICL7106
DISPLAY
C5
C1
-5V
R
C2 2
INT 27
V- 26
G2 25
C3 24
A3 23
G3 22
GND 21
14 E2
15 D3
16 B3
17 F3
18 E3
19 AB4
20 POL
DISPLAY
12 A2
11 B2
10 C2
9 D2
8 E1
7 G1
6 F1
5 A1
4 B1
3 C1
2 D1
ICL7107
1 V+
TO DECIMAL
POINT
C3
BUFF 28
A-Z 29
R6
13 F2
IN LO 30
IN HI 31
COM 32
CREF- 33
CREF+ 34
REF LO 35
REF HI 36
TEST 37
C4
OSC 3 38
OSC 2 39
OSC 1 40
R3
TP3
TP4
TP1TP2 R
1
R4
TP5
IN
R5
+5V
DISPLAY
C1 = 0.1F
C2 = 0.47F
C3 = 0.22F
C4 = 100pF
C5 = 0.01F
R1 = 24k
R2 = 47k
R3 = 100k
R4 = 1k TRIMPOT
R5 = 1M
R6 = 150
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002. All Rights Reserved
DISPLAY
1 V+
OSC 1 40
2 D1
OSC 2 39
3 C1
OSC 3 38
4 B1
TEST 37
5 A1
REF HI 36
6 F1
REF LO 35
7 G1
CREF 34
8 E1
CREF 33
9 D2
COMMON 32
10 C2
IN HI 31
11 B2
IN LO 30
12 A2
A-Z 29
13 F2
BUFF 28
14 E2
INT 27
15 D3
V - 26
16 B3
G2 25
17 F3
C3 24
18 E3
A3 23
19 AB4
G3 22
20 POL
BP 21
R3
C4
180k
50pF
TP1
TP2
R4
10k
R1
220k
C1
0.1F
TP3
C5
0.01F
R5
+
IN
1M
C2
0.01F
C3
R2
+
9V
180k
0.047F
TP4
DISPLAY
Assembly Instructions
The circuit board layouts and assembly drawings for both
kits are given in Figures 10, 11. The boards are single-sided
to minimize cost and simplify assembly. Jumpers are used to
allow maximum flexibility. For example, provision has been
made for connecting an external clock (Test Point #5).
Provision has also been made for separating REF Lo from
COMMON when using an external reference zener. In a
production instrument, the board area could be reduced
2
200.0mV
FULL SCALE
2.000V
FULL SCALE
C2 (Mylar)
0.47F
0.047F
R1
24k
1.5k (Note)
R2
47k
470k
C2
0.1F
0.022F
R1
220k
150k
R2
180k
1.8M
R4
10k
100k
NOTE: Changing R1 to 1.5k will reduce the battery life of the ICL7106
kit. As an alternative, the potentiometer can be changed to 25k.
ICL7106
BP
TO LCD
DECIMAL
POINTS
SEGMENTS
DECIMAL
POINT
SELECT
CONTROL
(V+/GND)
TEST
CD4030
GND
Capacitors
V+
1M
IT1750
ICL7106
BP
TEST
TO LCD
DECIMAL
POINT
21
37
TO LCD
BACKPLANE
The Reference
ICL7106/ICL7107
40
100k
39
100pF
38
2
2
SYSTEM CLOCK
OSC1
TEST
40
5V
37
5V
0V
ICL7107
ICL7106
OSC1
V+
CD4009
V+
REF HI
6.8V
ZENER
REF LO
IZ
ICL7106
ICL7107
V+
OSC 1
IN914
OSC 2
OSC 3
0.047
F
ICL7107
IN914
GND
V-
+
10
F
-
V-
FIGURE 8A.
V- = 3.3V
V+
Input Filters
V+
ICL7106
ICL7107
ICL8069
1.2V
REFERENCE
REF HI
REF LO
COMMON
FIGURE 8B.
FIGURE 8. USING AN EXTERNAL REFERENCE
Power Supplies
The ICL7106 kit is intended to be operated from a 9V dry
cell. INPUT Lo is shorted to COMMON, causing V+ to sit
2.8V positive with respect to INPUT Lo, and V- 6.2V
negative with respect to INPUT Lo.
The ICL7107 kit should be operated from 5V. Noisy
supplies should be bypassed with 6.8F capacitors to
ground at the point where the supplies enter the board.
INPUT Lo has an effective common mode range with
respect to GND of a couple of volts.
The precise value is determined by the point at which the
integrator output ramps within ~0.3V of one or other of the
supply rails. This is governed by the integrator time constant,
the magnitude and polarity of the input, the common mode
voltage, and the clock frequency: for further details, consult
the data sheet. Where the voltage being measured is
floating with respect to the supplies, INPUT Lo should be
tied to some voltage within the common mode range such as
GROUND or COMMON. If a -5V supply is unavailable,
suitable negative rail can be generated locally using the
circuit shown in Figure 9.
Preliminary Tests
Auto Zero
With power on and the inputs shorted, the display should
read zero. The negative sign should be displayed about 50%
of the time, an indication of the effectiveness of the autozero system used in the ICL7106 and ICL7107. Note that
some competitive circuits flash negative on every alternate
conversion for inputs near zero. While this may look good to
the uninitiated, it is not a true auto zero system!
Over-Range
Inputs greater than full scale will cause suppression of the
three least significant digits; i.e., only 1 or -1 will be displayed.
Polarity
The absence of a polarity signal indicates a positive reading.
A negative reading is indicated by a negative sign.
Further evaluation should be performed with the help of a
precision DC voltage calibrator such as Fluke Model 343A.
Alternatively a high quality 41/2 digit DVM can be used,
provided its performance has been measured against that of
a reliable standard.
Polypropylene Capacitors
1. Plessey Capacitors, West Lake Village, California
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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