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  • Exercise of FPGA-Based Digital System Design: The BPSK Receiver

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    Đặng Hoài Sơn
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    This document provides instructions for simulating and implementing a BPSK demodulator on an FPGA. It describes: 1) The schematic of the BPSK receiver circuit, which includes a block to convert input data from excess to 2's complement representation and uses 32 samples per symbol with a 12-bit flip flop enabled by a 54400 pulse signal for bit synchronization. 2) Developing a Verilog test bench file to simulate the project and using a TX BPSK module to supply input data with matching communication parameters. 3) Experimentally verifying the circuit by assigning TX and RX pinouts and using ADC and DAC circuits for external interfaces, with output pins for debugging.

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    FPGA

    Original Title

    6-RX_BPSK_15-16

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    This document provides instructions for simulating and implementing a BPSK demodulator on an FPGA. It describes: 1) The schematic of the BPSK receiver circuit, which includes a block to convert input data from excess to 2's complement representation and uses 32 samples per symbol with a 12-bit flip flop enabled by a 54400 pulse signal for bit synchronization. 2) Developing a Verilog test bench file to simulate the project and using a TX BPSK module to supply input data with matching communication parameters. 3) Experimentally verifying the circuit by assigning TX and RX pinouts and using ADC and DAC circuits for external interfaces, with output pins for debugging.

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    6 views2 pages

    Exercise of FPGA-Based Digital System Design: The BPSK Receiver

    Uploaded by

    Đặng Hoài Sơn
    This document provides instructions for simulating and implementing a BPSK demodulator on an FPGA. It describes: 1) The schematic of the BPSK receiver circuit, which includes a block to convert input data from excess to 2's complement representation and uses 32 samples per symbol with a 12-bit flip flop enabled by a 54400 pulse signal for bit synchronization. 2) Developing a Verilog test bench file to simulate the project and using a TX BPSK module to supply input data with matching communication parameters. 3) Experimentally verifying the circuit by assigning TX and RX pinouts and using ADC and DAC circuits for external interfaces, with output pins for debugging.

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    © All Rights Reserved
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    of 2

    Exercise of

    FPGA-Based Digital System Design


    Prof. C. Abbate - A.A. 2015/2016

    The BPSK Receiver


    Introduction
    In this exercise a BPSK demodulator on FPGA will be simulated and realized. The schematic of the
    circuit is reported in the next picture. Please use the same folder MODEM_BPSK for the project.
    Moreover, change the instance names.

    As visible in the schematic, if the input data is represented as excess, and additional block must
    convert this data in 2 complement representation. We suppose 1 period of sinusoid for symbol.
    Moreover, use 32 samples for every period in order to design the flip flop.

    Please, note that the TFF is used in order to generate the local carrier. Moreover the 54400 pulsed
    signal is used on order to enable and synchronous load the 12 bits flip flop. This flip flop is
    reset by SSync (bit synchronization signal).
    Please analyze and comment the schematic. Ask the teacher in case of doubts.

    Project Simulation
    Please write a Verilog test beng file in order to simulate de project. Moreover, use the TX BPSK
    in order to supply the input data to the receiver (please change TX or RX in order to have the same
    communication parameters). Analyze all the signals in the system. Please comment on the results.

    Experimental Verification of the Project.


    Please, assign the pin of TX and RX BPSK and verify the circuit. Please use the ADC and DAC
    circuits in order to use external interface. Use output pins in order to have a debug.

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