Professional Documents
Culture Documents
09 Memories
09 Memories
09 Memories
Digital IC-konstruktion
Memories
Viktor wall
p of Electrical and Information Technology
gy
Dept.
Lund University
C t
Courtesy:
Sven
S
Mattisson,
M tti
EMP
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
E h Canceller
Echo
C
ll Chip
Chi
RAMs
Size
ca. 5 x 6 mm2
10 RAMs
250kbits
ROMs
2 ROMs
30kbits
Source:
So
rce Semiconductor
Semicond ctor Memor
Memory: Technologies and Global Markets
Markets, April 2010
From http://www.electronics.ca/presscenter/articles/1272/1/Global-Market-ForSemiconductor-Memory-To-Be-Worth-79-Billion-In-2014/Page1.html
0.35m, 5 Metal Layer CMOS, >2 million transistors. Anders Berkeman 2002
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
Random
Access
Nonvolatile Read-Only
y
RWM
Memories
(Nonvolatile)
Non-Random (NVRWM)
Read-Write Memories
(RWM)
Access
SRAM
FIFO
PROM
ROM
DRAM
LIFO(Stack)
EPROM
PLA
Shiftregister
g
Registerg
Bank CAM
EPROM =
E2PROM
FLASH
EEPROM or
E2PROM =
Flash=
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
E
Emerging
i Technologies
T h l i
MRAM = Magnetoresistive RAM
Electric current switches the magnetic polarity and
Change in magnetic polarity sensed as resistance change
Polymer memories
Change
g in resistance due to ionic transport
p
with
applied electric field
AND MORE...
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
1.8
Flip-flops
Flip
flops
Dual port memory
Single port memory
Double width memory
1.6
1.4
1.2
squa
are mm
1
0.8
0.6
0.4
0.2
0
500
1000
3500
4000
4500
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
Memory Addressing
D al Port F
Dual
Functionality
nctionalit by
b using
sing
Single Port Memories
M bits
S ingle port R A M
32 16
32x16
S ingle port R A M
32x16
A ddress counter
0
1
31:16
31:16
S ingle port R A M
32x32
15:0
15:0
ADDR
nW E
Word 1
S2
SN-3
SN-2
SN-1
Word N-3
Word N-2
Word N-1
Storage
Cell
Addres
ss Decod
der
S0
Word 0
N Words
W
=
Address b
bits
b)
NW
Words =
N Ad
ddress bits
a)
S0
S1
log2 N
M bits
Word 0
Word 1
Storage
Cell
Word N-3
Word N-2
Word N-1
A ddress counter
IInput-Output
tO t t
(M bits)
IInput-Output
tO t t
(M bits)
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
Column Decoding
Large Memories
2K Columns
Addrress bits
Address
s Decode
er
S0
Word 0
Word 1
Word N-3
Word N-2
Word N-1
Sense Amplifiers/
Drivers
Large memories
Disproportional
height and width
bizarre
bi
shape
h
long delays
AK
AK+1
AL-1
Reduced
R
d
d Height
H i ht by
b
Column Decoding
Addrress Deco
oder
M bits
bit
Reduced
to 2L-K
One complete
O
l t word
d
line is accessed
Word Line (WL)
Long Wordline
Wasted power
Sense Amplifiers/
Drivers
A0
Column Decoder
AK-1
Input-Output
(M bits)
bit )
Input-Output
(M bits)
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
Hierarchical Memory
Row
Addr
Col
Addr
Bl k
Block
Addr
Col
Addr
Block
Addr
Memory Bus
Mux/Drivers
Global Data Bus
Large Buffers
L
B ff
to drive bus
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
A
Address
s Decode
er
Addrress bits
S0
Word 0
W d1
Word
Storage
Cell
Register cells
>10tran/bit
Word N-3
Word N-2
Word N-1
Sense Amplifiers/
Di
Drivers
Input-Output
(M bits)
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
ROM array
Memory Generators
Silicon Vendors and/or cell library usually offers
a memory generators to handle internal
memory issues.
VDD
Pull Up
Word
GND
Addr
Row
Addr
Word
Col
Addr
Block
Addr
Word
GND
Memory Bus
Mux/Drivers
Word
bit
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
bit
bit
bit
Digital IC-konstruktion
Digital IC-konstruktion
VDD
Initially BL pulled up
Pull Up
BL
BL
WL
BL pulled
ll d
down when
WL=1
WL
1out
0out
No transitors
= always
pulled up
WL[0]
GND
A
0
0
1
1
B
0
1
0
1
Q
1
0
0
0
WL[1]
One transistor ON
pulls down Bit Line
WL[2]
WL[3]
GND lines
overhead
BL[0]
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
A
0
0
1
1
B
0
1
0
1
Q
1
0
0
0
WL[1]=0
One transistor ON
pulls down Bit Line
WL[2]=1
WL[3]=0
GND lines
overhead
1
0
1
0
Select WL[2] WL[0,1,3]=0 and WL[2] = 1
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Cell (11 x 7)
Digital IC-konstruktion
Digital IC-konstruktion
WL[1]
BL[1]
WL[3]
BL[3]
[ ]
on
on
WL[2]
BL[2]
on
A
0
0
1
1
B
0
1
0
1
Q
1
1
1
0
All transistors ON
pulls down Bit Line
Non-selected WL =1
VDD
Pull Up
BL[0]
BL[1]
BL[2]
BL[3]
WL[0]
B
0
1
0
1
Q
1
1
1
0
All transistors ON
pulls down Bit Line
Non-selected WL =1
WL[1]
WL[3]
off
off
WL lines reversed
WL[2]
Long delay
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
Cell (8 x 7)
Pull Up
Programmming using
the Metal-1 Layer
y Onlyy
V DD
WL[0]
GND
BL
WL[1]
No contact to VDD or GND necessary;
d ti ll reduced
drastically
d
d cell
ll size
i
Loss in performance compared to NOR ROM
rword
WL
WL[2]
C bit
cword
GND
WL[3]
BL[0] BL[1] BL[2] BL[3]
Polysilicon
Diffusion
Metal1 on Diffusion
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
E i l t Transient
Equivalent
T
i V t Model
M d l for
f MOS NAND ROM
DD
Pull Up
BL[0]
BL[1]
BL[2]
BL[3]
WL[0]
Driver
BL
WL[1]
CL
r bit
WL[3]
r word
WL
WL
cbit
cword
WL[2]
WL
P l ili
Polysilicon
Word
W d Line
Li
Contact
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
Pseudo NMOS
Problems
VOL depends on transistor ratios
Static power consumption
prech
Pre-charge
devices
NOR field
One transistor ON
pulls
ll down
d
Bit Line
Li
WL[0]
GND
Alternative
Fully complimentary
Large area
Pre-charged memories
4 x 4 NMOS NOR
Precharged
g ROM
WL[1]
WL[2]
GND
WL[3]
BL[0]
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
BL[1]
BL[2]
BL[3]
Clocked
R d
Reduced
d static
t ti
power consumption
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
Wh t iis a Fl
What
Flash
h memory?
?
Wh t iis a Fl
What
Flash
h memory?
?
FLASH
FLASH
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
Fl ti Gate
Floating
G t Transistor
T
i t (FAMOS)
Flash EEPROM
BL
Control gate
Control gate
WL
n+
Floating gate
n+
erasure
n1 source
programming
i
n1 drain
p-substrate
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
FLASH stucture
FLASH write,
write e.g.
e g trap charge
VDD
VDD
Pull Up
Pull Up
word0
word0
GND
GND
word1
word1
word2
word2
GND
GND
word3
d3
word3
d3
= trapped charge. Transitor is always off Same content as ROM.
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
12 V
G
BL 0
BL 1
6V
D
BL 1
1V
WL 0
12 V
S
BL 0
5V
G
0V
WL 1
0V
6V
0V
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
WL 0
5V
D
0V
WL 1
0V
1V
0V
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
BL 0
array
NOR
BL 1
G
12 V
WL 0
0V
S
NAND
12 V
WL 1
0V
open
open
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
Living in the stage of 20GB memory after passing through the dark
dark-age
age of 1GB in 2002...
from www.samsung.com
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Flash
l h
Courtesy Intel
EPROM
O
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
R d W it Memories
Read-Write
M
i (RAM)
Static (SRAM)
M2
M5
Vdd
M4
Q
Q
M1
M6
M3
Dynamic (DRAM)
BL
BL
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
WL
Vdd
Q
M5
WL
M4
Q=0
Q=1
M1
M6
Q=Vdd
Vdd
Q
Vdd
M5
M4
Q=0
Q=1
M1
M6
Vdd
Q=Vdd
BL=0
BL
Read 1:
BL and BL
precharged to 1
BL
BL dicharged
through M1-M5
Important not to
change
c
a ge Q
Q!
Digital IC-konstruktion
Digital IC-konstruktion
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
match precharged
Vdd
M4
Q
Q
M1
If Q = BL
e g BL=1 & Q=1
e.g.
M6
Write cycle
WWL
1
BL
BL
For instance in
switches and routers
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
X
M1
M3
M2
VDD-VT
Read cycle
CS
BL1
Write
VDD
WWL
RWL
M3
BL1
RWL
BL2
Read
BL2
VDD-V
VT
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
1 ttransistor
i t DRAM C
Cell
ll
BL
WWL
WL
RWL
M3
M1
M2
M1
CS
BL1
Write
BL2
Read
CBL
CS
Write:
Data placed on BL
WL raised and CS charged
g
or discharged
Read:
BL precharged
Charge distribution gives
stored
t
d value
l
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
R t
Restore
off 1 ttransistor
i t DRAM C
Cell
ll
BL
VBL
V(1)
VPre
WL
M1
CBL
CS
V(0)
Sense amp. activated
Word line activated
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
Sense Amplifier
Differential Sensing
PC
VDD
S.A.
VDD
Operation
EQ
WL
Signal Restoration
Low swing in core
Reduced power consumption
Requires signal restoration
Disable PC and EQ
E bl WL
Enable
Memory cell
x
Sense
Differential input
Common Mode rejection
((Only
y in 6-transistor cell))
BL
Differential
Sense
Amplifier
Turn on Sense
BL
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
Sense Amplifiers
Sense Amplifiers
VDD
EQ
BL
VDD
Analog Amplifiers.
y
x
SE
BL
SE
VDD
Cross C
C
Coupled Inverters
Initialized to metastable point by
equalization (EQ)
Very fast
SE
VBL
SE
VPre
V(1)
V(1)
V(0)
Sense amp. activated
Word line activated
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
2 to 4 D
2-to-4
Dynamic
namic NOR Decoder
GND
GND
OFF
WL3=11
WL2=10
ON
Add
Address
Decoders
D
d
WL1=01
WL0=00
VDD
A0
1
WLs are precharged
A0
A1
A1
A0A1=11
Consumes power
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
VDD
VDD
WL3=11
OFF
WL3=11
VDD
VDD
WL2=10
VDD
S i Transistors
Series
T
i t
WL2=10
ON
VDD
WL1=01
WL1=01
VDD
Slow
VDD
WL0=00
A0
A0
A1
A1
WL0=00
A0A1=11
A0
A0
A1
A1
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
PLA versus
ers s ROM
PLA = Programmable
P
bl Logic
L i Array
A
PLA- Programmable
g
Logic
g Array
y
Structured approach to random logic, i.e.
implementing Boolean function
Two level logic, NOR-NOR or NAND-NAND
X0X1
AND
plane
l
Product terms
OR
plane
l
X2
F
Functionality
ti
lit Identical
Id ti l to
t ROM
Main difference:
ROM fully populated
PLA: One element per minterm, several WL valid
X0
X1
X2
f0
f1
f 0 x0 x 1 x 2
f 1 x0 x 1 x 2 x 2 x0 x 1
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
PLA
Pull upp
GND
NAND - NAND
Pull upp
VDD
GND
GND
GND
GND
AND - OR
GND
GND
NOR - NOR
VDD
x0
x0
x1
x1
x2
x2
f 0 x0 x 1 x 2
f0
f1
f 1 x0 x 1 x 2 x 2 x0 x 1
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
P
Pre-charged
h
d PLA,
PLA NOR-NOR
NOR NOR
Pull upp
GND
Pull upp
VDD
GND
GND
GND
GND
GND
GND
VDD
x0
f 0 x0 x1 x2
x0
x1
x1
x2
x2
x0 x1 11 WL 1 f 0 0 f 0 1
f0
f1
x0 x1 0 WL 0 f 0 1 f 0 0
E
Espresso=
B
Boolean
l
Minimization
Mi i i ti
.i 7
.o 20
Input
.type f
.phase 11111111111111111111
0000010 00000100101010010000
0000011 00000100101010010000
0000100 -------------0110100
0010011 00001111101011000100
0011010 00100100001100010101
0101100 -------------1110000
1011010 0010010000110
0010010000110--10101
10101
1110110 10000101011111010000
1110111 10000101011111010000
1111100 10001010101111110000
1111101 10001010101111110000
1111110 10001--0101111110000
1111111 10001010101111110000
.e
.i 7
.o 20
#.phase
.p 9
0000100
11111-1
111110
1111100101100
0000010010011
-011010
11101111111-.e
Minimized
11111111111111111111
00000000000000110100
00000010000000000000
00000010000000000000
00000000000001110000
00000100101010010000
00001111101011000100
00100100001100010101
10000101011111010000
10001000101111110000
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
Digital IC-konstruktion
Embedded RAM
I it a problem?
Is
bl ? Why
Wh is
i it a problem?
bl ?
FFT Design
D i
8k points FFT for DVB
(Digital Video Broadcasting)
Several embedded
memories whos
who s
properties and size
is crucial to the
implementation
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Digital IC-konstruktion
OFDM Synchronization
Frame
Memories are a
dominant part of
the construction
Stefan Johansson
Funding: INTELECT
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/