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(Codientu - Org) AVR4 PDF
(Codientu - Org) AVR4 PDF
NLU
CNG HC AVR
AVR4TIMER/COUNTER V CHUYN I ADC
Tho thun: ti liu ny thuc quyn s hu ca tc gi, bn c th t do tham kho
ti liu nhng khng c php s dng in thnh sch bo, ng ln cc din n
hay website, nhng bn c th dng ng link http://www.dieukhientudong.net
hng ti ti liu. Lin h tc gi qua email: thanhtam.h@gmail.com.
I.
Bn s i n u.
Trong bi 3 ti gii thiu khi qut phng php lp trnh bng ngn ng C cho AVR vi
WinAVR v cch s dng ngt trong AVR. Bi 4 ny chng ta s kho st cc ch hot ng
ca phng php iu khin cc b nh thi, m (Timer/Counter) trong AVR. Cng c phc v
cho bi ny vn l b cng c WinAVR v phn mm m phng Proteus. Ti vn dng chip
Atmega8 lm v d. Mt iu khng may mn l khng phi tt c cc b Timer/Counter trn
tt c cc dng chip AVR l nh nhau, v th nhng g ti trnh by trong bi ny c th s khng
ng vi cc dng AVR khc nh AT90STuy nhin ti cng s c gng ch ra mt s im
khc bit c bn cc bn c th t mnh iu khin cc chip khc.
Sau bi ny, ti hy vng bn s:
- Nm bt c bn cc b Timer/Counter c trn AVR.
- S dng cc Timer/Counter nh cc b nh thi.
- S dng cc Timer/Counter nh cc b m.
- S dng cc Timer/Counter nh cc b to xung iu rng PWM.
- Vit mt v d iu khin ng c RC servo bng PWM.
II.
AUTO.NLU
xung iu rng PWM dng cho cc mc ch iu khin. C th to 2 tn hiu PWM c lp trn
cc chn OC1A (chn 15) v OC1B (chn 16) bng Timer/Counter1. Cc b Timer/Counter kiu
ny c tch hp thm kh nhiu trong cc chip AVR sau ny, v d Atmega128 c 2 b,
Atmega2561 c 4 b
Timer/Counter2: tuy l mt module 8 bit nh Timer/Counter0 nhng Timer/Counter2 c
n 4 ch hot ng nh Timer/Counter1, ngoi ra n n cn c s dng nh mt module
canh chnh thi gian cho cc ng dng thi gian thc (ch asynchronous).
Trong phm vi bi 4 ny, ti ch yu hng dn cch s dng 4 ch hot ng ca cc
Timer/Counter. Ch asynchronous ca Timer/Counter2 s c b qua v c th ch ny
khng c s dng ph bin.
Trc khi kho st hot ng ca cc Timer/Counter, chng ta thng nht cch gi tt tn
gi ca cc Timer/Counter l T/C, v d T/C0 ch Timer/Counter0
III. S dng Timer/Counter.
C mt s nh ngha quan trng m chng ta cn nm bt trc khi s dng cc T/C trong
AVR:
- BOTTOM: l gi tr thp nht m mt T/C c th t c, gi tr ny lun l 0.
- MAX: l gi tr ln nht m mt T/C c th t c, gi tr ny c quy nh bi
bi gi tr ln nht m thanh ghi m ca T/C c th cha c. V d vi mt b
T/C 8 bit th gi tr MAX lun l 0xFF (tc 255 trong h thp phn), vi b T/C 16
bit th MAX bng 0xFFFF (65535). Nh th MAX l gi tr khng i trong mi
T/C.
- TOP: l gi tr m khi T/C t n n s thay i trng thi, gi tr ny khng nht
thit l s ln nht 8 bit hay 16 bit nh MAX, gi tr ca MAX c th thanh i
bng cch iu khin cc bit iu khin tng ng hoc c th nhp tr tip thng
qua mt s thanh ghi. Chng ta s hiu r v gi tr TOP trong lc kho st T/C1.
1. Timer/Counter0
Thanh ghi: c 4 thanh ghi c thit k ring cho hot ng v iu khin T/C0, l:
-
Cc bit CS00, CS01 v CS02 gi l cc chip chn ngun xung nhp cho T/C0
(Clock Select). Chc nng cc bit ny c m t trong bng 1.
Bng 1: chc nng cc bit CS0X
AUTO.NLU
Khi bit TOIE0=1, v bit I trong thanh ghi trng thi c set (xem li bi 3 v iu
khin ngt), nu mt trn xy ra s dn n ngt trn.
TIFR (Timer/Counter Interrupt Flag Register): l thanh ghi c nh cho tt c cc b
T/C. Trong thanh ghi ny bit s 0, TOV0 l c ch th ngt trn ca T/C0. Khi c
ngt trn xy ra, bit ny t ng c set ln 1. Thng thng trong iu khin cc
T/C vai tr ca thanh ghi TIFR khng qu quan trng.
AUTO.NLU
y chnh l tng cho hot ng ca chc nng m s kin trn T/C0. Bng cch thay i
trng thi chn T0 (chn 6 trn chip Atmega8) chng ta s lm tng gi tr thanh ghi TCNT0 hay
ni cch khc T/C0 c th dng m s kin xy ra trn chn T0. Di y chng ta s xem
xt c th cch iu khin T/C0 theo 1 ch nh thi gian v m.
- B nh thi gian: chng ta c th to ra 1 b nh th ci t mt khong thi gian no
. V d bn mun rng c sau chnh xc 1ms th chn PB0 thay i trng thi 1 ln (nhp nhy),
bn li khng mun dng cc lnh delay nh trc nay vn dng v nhc im ca delay l
CPU khng lm g c trong lc delay, v th trong nhiu trng hp cc lnh delay rt hn ch
c s dng. By gi chng ta dng T/C0 lm vic ny, tng l chng ta cho b m T/C0
hot ng, khi n m 1ms th n s t kch hot ngt trn, trong trnh phc v ngt trn chng
tat hay i trng thi chn PB0. Ti minh ha tng nh trong hnh 1.
CPU nop
DELAY
CPU nop
CPU nop
1ms
1ms
1ms
PB0 off
PB0 on
PB0 off PB0 on
CPU runs CPU runs CPU runs
Timer/Counter
1ms
1ms
1ms
Overflow Overflow Overflow Overflow
PB0 on
PB0 off PB0 on
PB0 off
Hnh 1. So snh 2 cch lm vic
AUTO.NLU
1ms, vy ta hon ton c th s dng prescaler=8 to ra mt khong nh th 1ms. Bc tip
theo l xc nh gi tr khi u ca TCNT0 T/C0 m ng 1ms (1000us). ng vi
prescaler=8 chng ta bit l c 8us th TCNT0 tng 1 n v, d dng tnh c b m cn
m 1000/8=125 ln ht 1ms, do gi tr ban u ca TCNT0 phi l 256-125=131. Bn c
th quan st hnh 2 hiu thu o hn.
count 125 times x 8us =1000us
Overflow
interrupt
count more
//vng lp v tn
//do nothing
}
return 0;
}
//trinh phuc vu ngat tran T/C0
ISR (TIMER0_OVF_vect ){
PORTB ^=1; //doi trang thai Bit PB0
TCNT0=131; //gan gia tri khoi tao cho T/C0
}
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AUTO.NLU
on code rt n gin, bn ch cn ch n 3 dng khai bo cho T/C0 (dng 9, 10, 11).
Vi dng 9: TCCR0=(1<<CS01) l 1 cch set bit CS01 trong thanh ghi iu khin TCCR0 ln 1, 2 bit
CS02 v CS00 c gi tr 0 (bn xem li bi 3 v cch set cc bit c bit trong cc thanh ghi), tm li
dng ny tng ng TCCR0=2, gi tr Prescaler c chn bng 8 (tham kho bng 1). Dng 10 chng
ta gn gi tr khi to cho thanh ghi TCNT0. V dng 11 set bit TIOE0 ln 1 cho php ngt xy ra khi
c trn T/C0. Trong trnh phc v ngt trn T/C0, chng ta s thc hin i trng thi chn PB0 bng
ton t XOR (^), ch n ngha ca ton t XOR: nu XOR mt bit vi s 1 th bit ny s chuyn
trng thi (t 0 sang 1 v ngc li). Cui cng v quan trng l chng ta cn gn li gi tr khi to cho
T/C0.
Bn c th v mt mch in m phng n gin dng 1 Oscilloscope nh trong hnh 3 kim tra
hot ng ca on code.
AUTO.NLU
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Ni dung trong chng trnh chnh l khai bo cc hng giao tip cho cc PORT, PORTB
l ouput xut kt qu m ra led 7 on, PORTD c khi bo input v cc button c ni
vi PORT ny. T/C0 c khai bo s dng ngun kch ngoi t T0, dng cnh xung thng qua
dng TCCR0=(1<<CS02)|(1<<CS01), bn cng c th khai bo tng ng l TCCR0=6 (tham kho
bng 1). Gi tr ca b m s c xut ra PORTB kim tra. im ch trong on chng trnh ny
l macro bit_is_clear, y l mt macro c nh ngha trong file sfr_defs.h dng kim tra 1 bit
trong mt thanh ghi c bit c c xa (bng 0) hay khng, trong trng hp ca on code trn:
if(bit_is_clear(PIND,7)) TCNT0=0; ngha l kim tra xem nu chn PD7 c ko xung 0 (button 2
c nhn) th s reset b m v 0.
AUTO.NLU
AUTO.NLU
Nhn chung thuc ht cch phi hp cc bit trong 2 thanh ghi TCCR1A v
TCCR1B l tng i phc tp v T/C1 c rt nhiu mode hot ng, chng ta s
kho st chng trong phn cc ch hot ng ca T/C1 bn di. y, trong
thanh ghi TCCR1B c 3 bit kh quen thuc l CS10, CS11 v CS12. y l cc bit
chn xung nhp cho T/C1 nh truong T/C0. Bng 2 s tm tt cc ch xung nhp
trong T/C1.
Bng 2: chc nng cc bit CS12, CS11 v CS10
AUTO.NLU
Bit 2 trong TIMSK l TOIE1, bit quy nh ngt trn cho thanh T/C1 (tng t
trng hp ca T/C0).
Bit 3, OCIE1B l bit cho php ngt khi c 1 Match xy ra trong vic so snh
TCNT1 vi OCR1B.
Bit 4, OCIE1A l bit cho php ngt khi c 1 Match xy ra trong vic so snh
TCNT1 vi OCR1A.
Bit 5, TICIE1 l bit cho php ngt trong trng hp Input Capture c dng.
Cng vi vic set cc bit trn, bit I trong thanh ghi trng thi phi c set nu
mun s dng ngt (xem li bi 3 v iu khin ngt).
TIFR (Timer/Counter Interrupt Flag Register): l thanh ghi c nh cho tt c cc b
T/C. Cc bit t 2 n 5 trong thanh ghi ny l cc c trng thi ca T/C1.
AUTO.NLU
Cc mode hot ng: c tt c 5 ch hot ng chnh trn T/C1. Cc ch hot ng
c bn c quy nh bi 4 bit Waveform Generation Mode (WGM13, WGM12, WGM11
WGM10) v mt s bit ph khc. 4 bit Waveform Generation Mode li c b tr nm trong 2
thanh ghi TCCR1A v TCCR1B (WGM13 l bit 4, WGM12 l bit 3 trong TCCR1B trong khi
WGM11 l bit 1 v WGM10 l bit 0 trong thanh ghi TCCR1A) v th cn phi hp 2 thanh ghi
TCCR1 trong lc iu khin T/C1. Cc ch hot ng ca T/C1 c tm tt trong bng sau 3:
Bng 3: cc bit WGM v cc ch hot ng ca T/C1.
2.1.
AUTO.NLU
List 3. nh th 10ms vi T/C1
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/delay.h>
int main(void){
DDRB=0xFF;
PORTB=0x00;
//vng lp v tn
//do nothing
}
return 0;
}
//trinh phuc vu ngat tran T/C1
ISR (TIMER1_OVF_vect ){
PORTB ^=1; //doi trang thai Bit PB0
TCNT1=55535; //gan gia tri khoi tao cho T/C1
}
2.2.
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AUTO.NLU
List 4. Phi hp CTC vi m s kin
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/delay.h>
volatile usigned char val=0; //khai bao 1 bien tam val va khoi tao =0
int main(void){
DDRB=0xFF;
//PORTB la output PORT
PORTB=0x00;
TCCR1B=(1<<WGM12)|(1<<CS12)|(1<<CS11);// CS12=0, CS11=0,
//CS10=1: chon Prescaler = 1
OCR1A=4;
//gan gia tri can so sanh
TIMSK(1<<OCIE1A);; // cho phep ngat khi gia tri dem bang 4
sei();
//set bit I cho phep ngat toan cuc
while (1){
//vng lp v tn
//do nothing
}
return 0;
}
//trinh phuc vu ngat compare match
ISR (TIMER1_COMPA_vect ){
val++;
if (val==10) val=0; //gioi han bien val tu 0 den 9
PORTB =val; //xuat gia tri ra PORTB
}
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AUTO.NLU
ta bit rng TCNT1 tng ln t 0, v th m 5 s kin th cn t gi tr so snh l 4 (0, 1,
2, 3, 4). Dng 11 set bit cho php ngt khi c Compare match xy ra (dng cho channel A).
Mode 12 ca CTC (WGM13=1, WGM12=1, WGM11=0, WGM10=0) cng tng t
mode 4 nhng ci khc l gi tr cn so snh c cha trong thanh ghi ICR1 (khng phi
OCR1A hay OCR1B). Khi nu mun dng ngt th bn phi dng ngt Input capture. C
th
dng
8
trong
list
4
i
thnh:
TCCR1B=(1<<WGM13)|( (1<<WGM12)|(1<<CS12)|(1<<CS11); dng 10: ICR1=4 v
dng 20: ISR (TIMER1_CAPT_vect ){
Mt kh nng khc ca CTC l xut tn hiu xung vung trn chn OC1A (chn 15 trn
Atmega8) bng cch set cc bit Compare Output Mode trong thanh ghi TCCR1A. Tuy nhin
vic to cc tn hiu output trong mode CTC khng tht s th v. V vy chng ta s kho
st cch to tn hiu output trong 1 ch chuyn nghip v th v hn, ch PWM.
Trc khi bt u lm vic vi cc ch PWM ti ngh cn thit gii thiu th no l
PWM v nhc li cc khi nim gi tr m ca Timer1 (hay bt k timer no khc) trn
AVR. Trc ht, PWM hay Pulse Width Modulation c hiu theo ngha ting Vit l
xung iu rng l khi nim ch tn hiu xung m thng th chu k (Time period) ca n
c c nh, duty cycle (thi thi gian tn hiu mc HIGH) ca n c th c thay i.
Bn xem 1 v d v PWM trong hnh 5.
AUTO.NLU
Nu nhn button th ng c hot ng, th button th ng c dng. Tuy nhin do tc
nhn v th ca con ngi c hn, bn s thy ng c hot ng hi sng (ripple).
iu g xy ra nu bn nhn v th button vi vn tc 5000 ln/giy. Cu tr li l tay bn s
b gy v button s b hng (^^). 5000 ln/s l iu khng tng, tuy nhin nu bn lm c
nh th th tng thi gian cho 1 ln nhn+th l 1:5000=0.0002s = 200us. C s khc bit
no khng gia trng hp thi gian nhn = 150us, thi gian th 50us v trng hp thi
gian nhn l 50us cn thi gian th l 150us. Bn s d dng tm cu tr li, trong trng
hp 1 ng c s quay vi vn tc nhanh hn trng hp 2. l tng c bn s dng
PWM iu khin vn tc ng c (v iu khin nhiu th khc na). bin ci khng
tng trn (5000 ln/s) thnh hin thc, chng ta s thay th ci button c kh kia bng 1
cng tc in t (electronics switch). Thng th cc chip MOSFET c dng lm cc
kha in t. MOSFET thng c 3 chn G (gate), D (drain) v S (source). V d 1
MOSFET knh N trng thi thng thng 2 chn D v S ko c dng in chy qua, nu
in p chn G ln hn chn S khong 3V tr ln th dng in c th chy t D sang S. hy
xem cch m t tng ng 1 MOSFET vi 1 button trong hnh 7.
12V
Microcontroller
(AVR)
Driver
PWM
AUTO.NLU
Hnh 9: cc mc gi tr ca T/C1.
BOTTOM lun c c nh l 0 (gi tr nh nht), MAX lun l 0xFFFF (65535).
TOP l gi tr nh do ngi dng nh ngha, gi tr ca TOP c th c c nh l 0xFF
(255), 0x1FF (511), 0x3FF 91023) hoc nh ngha bi cc thanh ghi ICR1 hoc OCR1A.
thc cht i vi ng dng PWM th TOP chnh l Time period ca PWM. Do mc ch s
dng m c th chn TOP l cc gi tr c nh hay cc thanh ghi, ring vi ti, cho mc
ch to tn hiu PWM ti chn TOP nh ngha bi thanh ghi ICR1. Ouput Compare l gi
tr so snh ca b Timer. Trong ch PWM th Output Compare quy nh Duty cycle. Vi
T/C1, Output Comapre l gi tr trong cc thanh ghi OCR1A v OCR1B. Do c 2 thanh ghi
c lp A v B, tng ng chng ta c th to ra 2 tn hiu PWM trn 2 chn OC1A v
OC1B bng T/C1. n lc chng ta tm hiu cch to PWM trn AVR.
2.3.
AUTO.NLU
Ti s gii thch hot ng ca Fast PWM knh A thng qua 1 trng hp c th,
mode 14 (WGM13=1, WGM12=1, WGM11=1, WGM10=0). Trong mode 14, gi tr TOP
(cng l chu k ca PWM) c cha trong thanh ghi ICR1, khi hot ng thanh ghi
TCNT1 tng gi tr t 0, gi s cc bit ph COM1A=1, COM1A0=0, lc ny trng thi ca
chn OC1A (chn 15) l HIGH (5V), khi TCNT1 tng n bng gi tr ca thanh ghi
OCR1A th chn OC1A c xa v mc LOW (0V), thanh ghi m TCNT1 vn tip tc
tng n khi no n bng gi tr TOP cha trong thanh ghi ICR1 th TCNT1 t ng reset
v 0 v chn OC1A tr v trng thi HIGH, ci ny gi l Clear OC1A/OC1B on Compare
Match, set OC1A/OC1B at TOP m bn thy trong hng 4 bng 4. Hnh 10 m t cch to
xung PWM trn chn OC1A mode 14.
AUTO.NLU
AUTO.NLU
Bn xem hnh 12b), iu khin servo bn cn cp cho dy iu khin mt tn hiu
PWM c Time Period khong 20ms, duty cycle ca PWM s quyt nh gc xoay ca servo.
Vi Duty cycle l 1ms, servo xoay v v tr 0o, khi duty cycle =2ms, gc xoay s l 180o, t
bn c th tnh c duty cycle cn thit khi bn mun servo xoay n 1 v tr bt k gia
0o v 180o. Sau khi hiu cch iu khin servo, chng ta c th d dng vit code iu khin
chng, ch cn to cc xung PWM bng T/C1. on code cho v d ny c trnh by trong
list 5.
List 5. iu khin servo bng PWM
#include <avr/io.h>
#include <avr/interrupt.h>
int main(void){
DDRB=0xFF;
PORTB=0x00;
MCUCR|=(1<<ISC11)|(1<<ISC01);
//ngat canh xuong
GICR |=(1<<INT1)|(1<<INT0); //cho php 2 ngat hoat dong
TCCR1A=(1<<COM1A1)|(1<<COM1B1)|(1<<WGM11);
TCCR1B=(1<<WGM13)|(1<<WGM12)|(1<<CS10);
OCR1A=1000;
//Duty cycle servo1=1000us=1ms (0 degree)
OCR1B=1500;
//Duty cycle servo2=1500us=1.5ms (90 degree)
ICR1=20000;
//Time period = 20000us=20ms
sei();
while (1){
}
return 0;
}
//trinh phuc vu ngat ngoai
ISR (INT0_vect ){
if (OCR1A==1000) OCR1A=1500; //thay doi goc xoay servo1 den 90 do
else OCR1A = 1000; // thay doi goc xoay servo1 den 0 do
}
ISR (INT1_vect ){
if (OCR1B==1000) OCR1B=1500; //thay doi goc xoay servo1 den 90 do
else OCR1B = 1000; // thay doi goc xoay servo1 den 0 do
}
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AUTO.NLU
trc. Dng 11 v 12 thc hin set cc bit iu khin Timer1, trc ht l cc bit COM. Bn
thy ti ch set 2 bit COM1A1 v COM1B1: (1<<COM1A1)|(1<<COM1B1). Hai bit
COM1A0 v COM1B0 khng set tc mc nh bng 0. i chiu vi bng 4 bn thy chng
ta s dng Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at TOP cho tt c 2
knh A v B. Chng ta set 3 bit WGM13, WGM12 (thanh ghi TCCR1B, dng 12) v
WGM11 (thanh ghi TCCR1A, dng 11) nh th thu c t hp (WGM13=1, WGM12=1,
WGM11=1, WGM10=0) tc l mode 14 c chn (bng 3). Cn li chng ta set bit CS10
khai bo rng ngun xung clock cho Timer1 bng clock cho vi iu khin (prescaler=1)
tc l 1us trong tng hp f=1Mhz. (nu bn dng cc trnh bin dch khc khng h tr
nh ngha tn cc bit th 2 dng 11 v 12 tng ng: TCCR1A=0xA2; TCCR1B=0x19).
Dng 15 chng ta khai nhp gi tr cho ICR1 cng l Time period cho PWM,
ICR1=20000 chng ta thu c Time period =20000 us = 20ms tha yu cu ca servo. Hai
dng 13 v 14 khai bo gi tr ban u ca cc duty cycle ca 2 knh PWM, cc gi tr ny
nh v tr gc xoay ca cc servo. Trong 2 trnh phc v ngt, cc gi tr ny c thay i
khi cc button c nhn.
2.4.
Phase correct PWM cung cp mt ch to xung PWM c phn gii cao (high
resolution) nn c gi l Phase correct PWM. Tng t Fast PWM, cng c 5 mode hot
ng thuc Phase correct PWM l cc mode 1, 2, 3, 10 v 11 (xem bng 3). Nm mode
ny tng ng cc mode 5, 6, 7, 14 v 15 ca fast PWM. V cch iu khin, Phase correct
hu nh ging fast PWM, ngha l nu bn bit cch s dng cc mode ca fast PWM th
bn s hon ton iu khin c Phase correct PWM. Khc nhau c bn ca 2 ch ny
l trong cch hot ng, nu Fast PWM c chu k hot ng trong 1 single-slope (mt sn)
th Phase correct PWM li dual-slope (hai sn). Ly v d mode 10 ca Phase correct PWM
tng ng vi mode 14 ca Fast PWM, trong mode ny thanh ghi ICR1 cha TOP v
OCR1A (hoc OCR1B i vi knh B) cha gi tr so snh. Khi hot ng, thanh ghi
TCNT1 tng t 0, khi TCNT1 bng vi OCR1A th chn OC1A c xa xung mc LOW
(ti ang ni trng hp COM1A1=1, COM1A0=0), TCNT1 tip tc tng n TOP, khi
TCNT1=TOP th TCNT1 KHNG c t ng reset v 0 nh trng hp Fast PWM m
TCNT1 bt u m ngc, tc gim tng gi tr t TOP v 0. Trong lc TCNT1 gim, n
1 lc n s bng gi tr ca OCR1A ln th 2, v ln ny, chn OC1A c set ln mc
HIGH, TCNT1 tip tc gim n 0 th 1 chu k hon tt. R rng 1 chu k l qu trnh m
trong 2 sn nn ta gi Phase correct PWM l dual-slope. Cng v tnh cht dual-slope m
tn hiu PWM trong ch ny c tnh i xng, thch hp cho cc ng dng iu khin
ng c. Hnh 13 m t cch m Phase correct PWM hot ng tron mode 10 vi ng ra o
(COM1A1=1, COM1A0=0).
TC
N
T1
AUTO.NLU