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3 The TTL Nand Gate
3 The TTL Nand Gate
3.1
3.2
Logical Operation
IN1
IN2
T1
T2
T3
T4
OUPUT
LO
LO
ONfor
OFF
OFF
ON
ON
HI
LO
HI
ONfor
OFF
OFF
ON
ON
HI
HI
LO
ONfor
OFF
OFF
ON
ON
HI
HI
HI
ONrev
ON
ON
OFF
OFF
LO
VCC
R3
R1
130
1.6k
RB
N3
4k
N1
Input 1
Input 2
N5
T4
N6
N2
T2
T1
N7
N4
Output
(no load)
T3
R2
1k
Fig. 3.2
IB
I3
130
R1
1.6k
RB
N3
4k
N1
Input 1
Input 2
0.1 V
R3
N5
T4
N6
N2
N7
T1
Output
(no load)
N4
R2
1k
Fig. 3.3
(iii) With T4 operating at the point of cut-in its base current and hence
its collector current can
be taken as zero. This means that there is no voltage drop across
either resistor R1 or R3
and so the potential at both sides of these resistors is equal to
the supply voltage VCC giving:
Node N3, Node N5 : VN3 VN5 VCC 5V
(v)
VN4 0V
The current drawn from the supply can then be obtained as:
IB
1.025mA
RB
4k
I1
IB
I3
130
R1
N5
1.6k
RB
N3
4k
N1
Input 1
Input 2
5V
5V
R3
N6
N2
T2
T1
N7
N4
Output
(no load)
T3
R2
1k
Fig. 3.4
Node N1 :
VN5 VCC 5V
The current drawn from the supply this time is given by the sum of I B
and I1 with I3 = 0:
Then:
V VN1 5 2.3V
IB CC
0.675mA
RB
4k
and
I1
2.56mA
R1
1.6k
If the NAND gate is assumed to spend half of its time in each logic
state then the average power consumption can be expressed as:
PAVE
10.56mW
2
2