EXPERIMENT - 6

AIM: Design and simulate an inverter using Quasi-Floating gate technique.

SOFTWARE USED: ORCAD PSPICE 16.6
THEORY : The QFGMOST appears as a developed version of the FG-MOST to overcome
some of its drawbacks. It has been discussed previously that the relatively high bias capacitance
value of the FG-MOST leads to an increase in the silicon area and a reduction of the effective
transconductance and GBW. Besides, FG-MOST has uncertain residual charge trapped at the
floating gate. Using the QFG-MOST, the occupied chip area is minimized and the initial charge
is no longer an issue . Since the floating gate is tied through a large value resistor to a proper bias
voltage, depending on the transistor type. Practically, a leakage resistance of a reverse biased PN junction of a diode connected MOS transistor MR is implemented rather than a typical resistor.
QFG-MOST may have a multiple input terminals like the FG-MOST. Besides, it can be
fabricated in any MOS technology, nevertheless, the double poly technology is recommended to
obtain better results. The input terminal is capacitively connected to the floating gate as FGMOST case.
CIRCUIT DIAGRAM:

1 .8 V d c

1 .8 V d c

0
1 .8 V d c

M 3

M 4

0
C in 1
R in 1
Vin

M 2

C in 2
R in 2

M 1

SIMULATION:

1. DC ANANYSIS
A. PSPICE CODE:

m4 4 5 5 5 pmos w=20u l=0.36u

m2 2 7 1 1 pmos w=20u l=0.36u
c1 4 5 1p
m3 3 6 6 6 pmos w=20u l=0.36u
m1 2 3 0 0 nmos w=5u l=0.36u
c2 6 3 1f
cin1 7 3 2f
rin1 7 3 100k
cin2 7 4 2f
rin2 7 4 100k
vin 7 0 dc 1v
cfgd1 3 2 1f
cfgs1 3 0 1f
rfgd1 3 2 100k
rfgs1 3 0 100k
cfgd2 4 2 1f
cfgs2 4 1 1f
rfgd2 4 2 100k
rfgs2 4 1 100k
vbias3 6 0 1.8v
vbias4 5 0 1.8v
vdd 1 0 1.8v
.dc vin 0v 1.8v 0.1v
.probe
.end
B. DC CHARACTERISTICS
2.0V

1.5V

(1.0861,1.0861)
1.0V

0.5V

0V
0V

0.2V
V(7)

0.4V

0.6V

0.8V

1.0V

V(2)
vin

1.2V

1.4V

1.6V

1.8V

2. TRANSIENT ANANYSIS
A. PSPICE CODE:
m4 4 5 5 5 pmos w=20u l=0.36u
m2 2 7 1 1 pmos w=20u l=0.36u
c1 4 5 1p
m3 3 6 6 6 pmos w=20u l=0.36u
m1 2 3 0 0 nmos w=5u l=0.36u
c2 6 3 1f
cin1 7 3 2f
rin1 7 3 100k
cin2 7 4 2f
rin2 7 4 100k
vin 7 0 pulse ( 0v 1.8v 0 0 0 10n 20n)
cfgd1 3 2 1f
cfgs1 3 0 1f
rfgd1 3 2 100k
rfgs1 3 0 100k
cfgd2 4 2 1f
cfgs2 4 1 1f
rfgd2 4 2 100k
rfgs2 4 1 100k
vbias3 6 0 1.8v
vbias4 5 0 1.8v
vdd 1 0 1.8v
.tran 0.1ns 40ns 1ns
.probe
.end

B. TRANSIENT CHARACTERISTICS
2.0V

1.0V

SEL>>
0V
V(7)
2.0V

1.0V

0V
0s

4ns

8ns

12ns

16ns

20ns

V(2)
Time

C. OUTPUT FILE:

24ns

28ns

32ns

36ns

40ns

**** 11/15/14 18:56:20 ***** PSpice 16.6.0 (October 2012) ***** ID# 0 ********
***
****

INITIAL TRANSIENT SOLUTION

TEMPERATURE = 27.000 DEG C

******************************************************************************

NODE VOLTAGE

NODE VOLTAGE

NODE VOLTAGE

NODE VOLTAGE

1)

1.8000 (

2)

1.7014 (

3)

1.8000 (

4)

1.8000

5)

1.8000 (

6)

1.8000 (

7)

0.0000 (

8)

0.0000

VOLTAGE SOURCE CURRENTS

NAME
CURRENT
vin
vbias3
vbias4
vdd

5.203E-05
0.000E+00
-8.272E-25
-4.244E-04

TOTAL POWER DISSIPATION 7.64E-04 WATTS

CALCULATIONS:

RESULT: Designed and simulated an inverter using Quasi-Floating gate technique.