MICROPROCESSORS AND APPLICATIONS

Third module
1. Differentiate memory mapped IO and IO mapped IO schemes

2. What are vectored interrupts?

An interrupt vector is a pointer to where the ISR(Interrupt Service Routine) is stored
in memory.
All interrupts (vectored or otherwise) are mapped onto a memory area called the
Interrupt Vector Table (IVT).
The IVT is usually located in memory page 00 (0000H - 00FFH).
3. Explain the interrupt structure of 8085.
There are 5 interrupt inputs:
TRAP (nonmaskable)
RST7.5
RST6.5
RST5.5
INTR

The INTR input.

The INTR input is the only non-vectored interrupt.
INTR is maskable using the EI/DI instruction pair.
RST 5.5, RST 6.5, RST 7.5 are all automatically vectored.
RST 5.5, RST 6.5, and RST 7.5 are all maskable.

TRAP is the only non-maskable interrupt in the 8085

TRAP is also automatically vectored

4. With an example, explain the interfacing of DAC to 8085.

The interfacing of DAC 0808 with microprocessor 8085 is shown below. Here,
programmable peripheral interface, 8255 is used as parallel port to send the digital data
toDAC.

Program:
MVI A, 80H ; Initialization -control word for 8255 to Configure all ports as output
ports
OUT 03
MVI A, DATA ; Load 8-bit data to be sent at the input of 0808 DAC
OUT 00 ; Send data on port A
5. Write an assembly a language program to generate the following waveforms using a control switch
a) Sawtooth Waveform b) Triangular waveform c)square waveform
(a) Saw tooth Wave Generation
MVI A,80
OUT 00
START: MVI A,00
L1: OUT 02
INR A
JNZ L1
JMP START
(b) Triangular Wave Generation
START: MVI L,00
L1: MOV A,L
OUT 02
INR L
JNZ L1
MVI L,FF
L2: MOV A,L
OUT 02
DCR L
JNZ L2
JMP START
(c) Square Wave Generation
MVI A,80
OUT 00
START: MVI A,00
OUT 02
CALL DELAY
MVI A,FF
OUT 02
CALL DELAY
JMP START
DELAY: MVI B,05
L1: MVI C,FF
L2: DCR C
JNZ L2
DCR B
JNZ L1
RET

Fourth module
6. Explain the control word format of 8255 for IO mode.

D0, D1, D3, D4 are assigned for lower port C, port B, upper port C and port A respectively. When these

bits are 1, the corresponding port acts as an input port. For e.g., if D 0 = D4 = 1, then lower port C and port
A act as input ports. If these bits are 0, then the corresponding port acts as an output port. For e.g., if D 1 =
D3 = 0, then port B and upper port C act as output ports.
D2 is used for mode selection of Group B (port B and lower port C). When D 2 = 0, mode 0 is selected
and when D2 = 1, mode 1 is selected.
D5 & D6 are used for mode selection of Group A ( port A and upper port C). The selection is done as
follows:

D6

D5

Mode

As it is I/O mode, D7 = 1.

For example, if port B and upper port C have to be initialized as input ports and lower port C and port A as
output ports (all in mode 0):
1.
2.
3.
4.

Since it is an I/O mode, D7 = 1.

Mode selection bits, D2, D5, D6 are all 0 for mode 0 operation.
Port B and upper port C should operate as Input ports, hence, D 1 = D3 = 1.
Port A and lower port C should operate as Output ports, hence, D 4 = D0 = 0.

Hence, for the desired operation, the control word register will have to be loaded with 8A (hex).
Mode 0 - Simple I/O
In this mode, the ports can be used for simple I/O operations without handshaking signals. Port A, port B
provide simple I/O operation. The two halves of port C can be either used together as an additional 8-bit port,
or they can be used as individual 4-bit ports. Since the two halves of port C are independent, they may be
used such that one-half is initialized as an input port while the other half is initialized as an output port.Mode 0
- Output mode
Mode 1 (Input/output with Hand shake)

In this mode, input or output is transferred by hand shaking Signals.

Handshaking signals is used to transfer data between whose data transfer is not same.
MODE 2:bi-directional I/O data transfer
This mode allows bidirectional data transfer over a single 8-bit data bus using handshake signals.
This feature is possible only Group A
Port A is working as 8-biy bidirectional.
PC3-PC7 is used for handshaking purpose.
The data is sent by CPU through this port , when the peripheral request it.
CONTROL WORD FORMATS:
In the INPUT mode , When RESET is High all 24 pins (3-ports) be a input mode.
7. What do you mean by DMA?
Direct memory access (DMA) is a process in which an external device takes
over the control of system bus from the CPU.
DMA is for high-speed data transfer from/to mass storage peripherals, e.g. harddisk
drive, magnetic tape, CD-ROM, and sometimes video controllers.
For example, a hard disk may boasts a transfer rate of 5 M bytes per second, i.e.

1 byte transmission every 200 ns. To make such data transfer via the CPU is
both undesirable and unnecessary.
The basic idea of DMA is to transfer blocks of data directly between memory and
peripherals. The data dont go through the microprocessor but the data bus is
occupied.
Normal transfer of one data byte takes up to 29 clock cycles. The DMA transfer
requires only 5 clock cycles.
Nowadays, DMA can transfer data as fast as 60 M byte per second. The transfer
rate is limited by the speed of memory and peripheral devices.
8. With neat diagram explain the architecture of programmable interrupt controller.

The Programmable Interrupt Controller (PlC) functions as an overall manager in an

Interrupt-Driven system. It accepts requests from the peripheral equipment, determines which of the
incoming requests is of the highest importance (priority), ascertains whether the incoming request has
a higher priority value than the level currently being serviced, and issues an interrupt to the CPU
based on this determination
Functional Block Diagram Description
Interrupt Request Register (IRR) and In-Service Register (ISR)
The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Register
(lRR) and the In- Service Register (lSR). The IRR is used to indicate all the interrupt levels which are
requesting service, and the ISR is used to store all the interrupt levels which are currently being serviced
Priority Resolver
This logic block determines the priorities of the bits set in the lRR. The highest priority is selected and
strobed into the corresponding bit of the lSR during the INTA sequence.
Interrupt Mask Register (IMR)
The lMR stores the bits which disable the interrupt lines to be masked. The IMR operates on the output of
the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower priority.
Data Bus Buffer
This 3-state, bidirectional 8-bit buffer is used to interface the PIC to the System Data Bus. Control
words and status information are transferred through the Data Bus Buffer.
Read/Write Control Logic

Cascade Buffer/Comparator

9. With neat schematic explain 8237 DMA Controller.

10.

With neat schematic explain 8255 PPI..

Data Bus buffer:

It is a 8-bit bidirectional Data bus.
Used to interface between 8255 data bus with system bus.
The internal data bus and Outer pins D0-D7 pins are connected in internally.
The direction of data buffer is decided by Read/Control Logic.
Read/Write Control Logic:
This is getting the input signals from control bus and Address bus
Control signal are RD and WR.
Address signals are A0,A1,and CS.
8255 operation is enabled or disabled by CS.
Group A and Group B control:

Group A and B get the Control signal from CPU and send the command to the individual control
blocks.
Group A send the control signal to port A and Port C (Upper) PC7-PC4.
Group B send the control signal to port B and Port C (Lower) PC3-PC0.

PORT A
This is a 8-bit buffered I/O latch.
It can be programmed by mode 0 , mode 1, mode 2 .
PORT B:
This is a 8-bit buffer I/O latch.
It can be programmed by mode 0 and mode 1.
PORT C
This is a 8-bit Unlatched buffer Input and an Output latch.
It is splitted into two parts.
It can be programmed by bit set/reset operation.
11. Explain the different operating modes of 8254 timer.
Mode 0: Events counter.
o Mode 0 is typically used for event counting.
o After the Control Word is written, OUT is initially low
o Will remain low until the Counter reaches zero.
o OUT then goes high and remains high until a new count or a new Mode 0 Control word is
written into the Counter.
o GATE e 1 enables counting; GATE e 0 disables counting.
Mode 1: One shot pulse
OUT will be initially high.
OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse,will
remain low until the Counter reaches zero.
OUT will then go high and remain high until the CLK pulse after the next trigger.
Mode 2: Continuous pulses, one clock pulse wide
This Mode functions like a divide-by-N counter.
It is typically used to generate a Real Time Clock interrupt.
OUT will initially be high.
When the initial count has decremented to 1, OUT goes low for one CLK pulse.
OUT then goes high again, the Counter reloads the initial count and the process is
repeated.
Mode 2 is periodic; the same sequence is repeated indefinitely.
Mode 3: Continuous square-wave as long as Gate is 1
Mode 3 is typically used for Baud rate generation.
Mode 3 is similar to Mode 2 except for the duty cycle of OUT.
OUT will initially be high.
When half the initial count has expired, OUT goes low for the remainder of the
count.
Mode 3 is periodic; the sequence above is repeated indefinitely.
Mode 4: Software triggered one-shot pulse
OUT will be initially high.
When the initial count expires, OUT will go low for one CLK pulse then go high
again.
The counting sequence is ``triggered' by writing the initial count.
GATE e 1 enables counting; GATE e 0 disables counting.
Mode 5: Hardware triggered one-shot pulse
OUT will initially be high.
Counting is triggered by a rising edge of GATE.
When the initial count has expired, OUT will go low for one CLK pulse then go
high again.
12. Explain and interface a seven segment display and keyboard to 8085

 Intels 8279 is a general purpose keyboard display controller that simultaneously drives the display of
a system and interfaces a keyboard with the CPU, leaving it free for its routine task.
The important features of 8279 are,

Simultaneous keyboard and display operations.

Scanned keyboard mode.
Scanned sensor mode.
8-character keyboard FIFO.
1 6-character display.
Right or left entry 1 6-byte display RAM.
Programmable scan timing.

Fifth module
13. List the features of Intel 8086.
8086 is a 16bit processor. Its ALU, internal registers works with 16bit binary
word
- 8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits
or 8 bit at a time
- 8086 has a 20bit address bus which means, it can address upto 220 = 1MB memory
location
- Frequency range of 8086 is 6-10 MHz
14. Explain the common mode signals of 8086.
RD* - Pin no. 34, Type O
Read: Read strobe indicates that the processor is performing a memory of I/O read cycle,
depending on the state of the S2 pin. This signal is used to read devices which reside on the 8086 local bus.
RD* is active LOW during T2, T3 and TW of any read cycle, and is guaranteed to remain HIGH in T2 until the
8086 local bus has floated.
This signal floats to 3-state OFF in hold acknowledge.
READY Pin no. 22, Type I
READY: is the acknowledgement from the addressed memory or I/O device that it will
complete the data transfer. The READY signal from memory / IO is synchronized by the 8284A Clock
Generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized. Correct
operation is not guaranteed if the setup and hold times are not met.
TEST* - Pin No 23 Type I
TEST* : input is examined by the Wait instruction. If the TEST* input is LOW execution
continues, otherwise the processor waits in an idle state. This input is synchronized internally during each
clock cycle on the leading edge of CLK.
RESET Pin no. 21 Type I
Reset: causes the processor to immediately terminate its present activity. The signal must be
active HIGH for at least four clock cycles. It restarts execution, as described in the instruction set description,
when RESET returns LOW. RESET is internally synchronized.
BHE*/S7- Pin No. 34 Type O
Bus High Enable / Status: During T1 the Bus High Enable signal (BHE*) should be used to
enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices tied to the

upper half of the bus would normally use BHE* to condition chip select functions. BHE* is LOW during T1
for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the
bus. The S,7 status information is available during T2, T3 and T4. The signal is active LOW and floats to 3state OFF in hold. It is LOW during T1 for the first interrupt acknowledge cycle.
15. Explain the signals used in maximum mode operation of 8086.
RQ*/GT0*, RQ*/GT1* - Pin no. 30, 31 Type I/O
Request /Grant: pins are used by other local bus masters to force the processor to release the
local bus at the end of the processors current bus cycle. Each pin is bidirectional with RQ*/GT0* having
higher priority than RQ*/GT1*. RQ*/GT* has an internal pull up resistor so may be left unconnected.
LOCK* - Pin no. 29 Type O
LOCK* : output indicates that other system bus masters are not to gain control of the system
bus while LOCK* is active LOW. The LOCK* signal is activated by the LOCK prefix instruction and
remains active until the completion of the next instruction. This signal is active LOW, and floats to 3-state
OFF in hold acknowledge.
QS1, QS0 Pin no. 24, 25 Type O
Queue Status: the queue status is valid during the CLK cycle after which the queue operation
is performed.
QS1 and QS0 provide status to allow external tracking of the internal 8086 instruction queue.
16. Explain the function of the following pins
a. NMI
Non Maskable Interrupt: an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to
via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A
transition from a LOW to HIGH initiates the interrupt at the end of the current instruction. This input is
internally synchronized.
b. DT/R
Data Transmit / Receive: needed in minimum system that desires to use an 8286/8287 data bus transceiver. It
is used to control the direction of data flow through the transceiver. Logically DT/R* is equivalent to S 1* in
the maximum mode, and its timing is the same as for M/IO*. (T=HIGH, R=LOW). This signal floats to 3state OFF in local bus hold acknowledge.
c. DEN
Data Enable: provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver.
DEN* is active LOW during each memory and I/O access and for INTA cycles. For a read or INTA* cycle it
is active from the middle of T2 until the middle of T4, while for a write cycle it is active from the beginning of
T2 until the middle of T4. DEN* floats to 3-state OFF in local bus hold acknowledge.
d. BHE.
Bus High Enable / Status: During T1 the Bus High Enable signal (BHE*) should be used to enable data onto
the most significant half of the data bus, pins D15-D8. Eight bit oriented devices tied to the upper half of the
bus would normally use BHE* to condition chip select functions. BHE* is LOW during T1 for read, write,
and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S,7
status information is available during T2, T3 and T4. The signal is active LOW and floats to 3-state OFF in
hold. It is LOW during T1 for the first interrupt acknowledge cycle
17. Explain the interrupts of 8086.
NMI Pin no. 17 Type I
Non Maskable Interrupt: an edge triggered input which causes a type 2 interrupt. A
subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable
internally by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current
instruction. This input is internally synchronized.
INTR Pin No. 18 Type I
Interrupt Request: is a level triggered input which is sampled during the last clock cycle of
each instruction to determine if the processor should enter into an interrupt acknowledge operation. A
subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally
masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active
HIGH.
18. Draw and explain the register organization of 8086 processor.
All the registers of 8086 are 16-bit registers. The general purpose registers can be used as either 8-bit
registers or 16-bit registers.

The register set of 8086 can be categorized into 4 different groups. The register organization of 8086 is shown
in the figure.
AX

AH

AL

BX

BH

BL

SS

CX

CH

CL

DS

DX

DH

DL

ES

General data registers

Registers

BP

Segment
registers

FLAGS/
PSW

SI
DI
IP

Pointers and index

Register organization of 8086

General Data Registers:
The registers AX, BX,CX and DX are the general purpose 16-bit registers.
AX is used as 16-bit accumulator. The lower 8-bit is designated as AL and higher 8-bit is designated as AH. AL
can be used as an 8-bit accumulator for 8-bit operation.
All data register can be used as either 16 bit or 8 bit. BX is a 16 bit register, but BL indicates the lower 8-bit of
BX and BH indicates the higher 8-bit of BX.
The register CX is used default counter in case of string and loop instructions.
The register BX is used as offset storage for forming physical address in case of certain addressing modes.
DX register is a general purpose register which may be used as an implicit operand or destination in case of a
few instructions.
Segment Registers:
The 8086 architecture uses the concept of segmented memory. 8086 able to address to address a memory
capacity of 1 megabyte and it is byte organized. This 1 megabyte memory is divided into 16 logical segments.
Each segment contains 64 kbytes of memory.
There are four segment register in 8086
Code segment register (CS)
Data segment register (DS)
Extra segment register (ES)
Stack segment register (SS)
Code segment register (CS):
is used fro addressing memory location in the code segment of the memory, where the executable program is
stored.
Data segment register (DS):
points to the data segment of the memory where the data is stored.
Extra Segment Register (ES)
: also refers to a segment in the memory which is another data segment in the memory.
Stack Segment Register (SS):
is used fro addressing stack segment of the memory. The stack segment is that segment of memory which is
used to store stack data.
While addressing any location in the memory bank, the physical address is calculated from two parts:
- The first is segment address, the segment registers contain 16-bit segment base addresses, related to
different segment.
- The second part is the offset value in that segment.
The advantage of this scheme is that in place of maintaining a 20-bit register for a physical address, the
processor just maintains two 16-bit registers which is within the memory capacity of the machine.
Pointers and Index Registers.
The pointers contain offset within the particular segments.
- The pointer register IP contains offset within the code segment.
- The pointer register BP contains offset within the data segment.
- He pointer register SP contains offset within the stack segment.
The index registers are used as general purpose registers as well as for offset storage in case of indexed, base
indexed and relative base indexed addressing modes.
The register SI is used to store the offset of source data in data segment.

The register DI is used to store the offset of destination in data or extra segment.
The index registers are particularly useful for string manipulation.

Flag Register
The 8086 flag register contents indicate the results of computation in the ALU. It also contains some flag bits
to control the CPU operations.
19. Explain the signals used in minimum mode operation of 8086.
HOLD, HLDA Pin no. 31, 30 Type I/O
HOLD: indicates that another master is requesting a local bus hold. To be acknowledged,
HOLD must be active HIGH. The processor receiving the hold request will issue HLDA (HIGH) as an
acknowledgement in the middle of a T1 clock cycle. Simultaneous with the issuance of HLDA the processor
will float the local bus and control lines. After HOLD is detected as being LOW, the processor will LOWer the
HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines.
The same rules as apply regarding when the local bus will be released.
HOLD is not an asynchronous input. External synchronization should be provided if the system can not
otherwise guarantee the setup time.
WR* - Pin no. 29 Type O
Write: indicates that the processor is performing a write memory or write I/O cycle,
depending on the state of the M/IO* signal. WR* is active for T2, T3 and TW of any write cycle. It is active
LOW, and floats to 3-state OFF in local bus hold acknowledge.
M/IO* - Pin no. 28 type O
Status line: logically equivalent to S2 in the maximum mode. It is used to distinguish a
memory access from an I/O access. M/IO* becomes valid in the T4 preceding a bus cycle and remains valid
until the final T4 of the cycle (M=HIGH), IO=LOW). M/IO* floats to 3-state OFF in local bus hold
acknowledge.
DT/R* - Pin no. 27 Type O
Data Transmit / Receive: needed in minimum system that desires to use an 8286/8287 data
bus transceiver. It is used to control the direction of data flow through the transceiver. Logically DT/R* is
equivalent to S1* in the maximum mode, and its timing is the same as for M/IO*. (T=HIGH, R=LOW). This
signal floats to 3-state OFF in local bus hold acknowledge.
DEN* - Pin no. 26 Type O
Data Enable: provided as an output enable for the 8286/8287 in a minimum system which
uses the transceiver. DEN* is active LOW during each memory and I/O access and for INTA cycles. For a
read or INTA* cycle it is active from the middle of T2 until the middle of T4, while for a write cycle it is active
from the beginning of T2 until the middle of T4. DEN* floats to 3-state OFF in local bus hold acknowledge.
ALE Pin no. 25 Type O
Address Latch Enable: provided by the processor to latch the address into the 8282/8283
address latch. It is a HIGH pulse active during T1 of any bus cycle. Note that ALE is never floated.
INTA* - Pin no. 24 Type O
INTA* is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2,
T3 and TW of each interrupt acknowledge cycle.
20. What are the advantages and disadvantages of physical memory of 8086?
21. Draw the memory read cycle in maximum mode of 8086.

22. Draw the memory write cycle in maximum mode of 8086.

23. With neat schematic, explain the architecture of 8086.

24. Explain the memory organization of 8086.

In an 8086 based system, the 1Mbyte memory is physically organized as odd bank and even bank, each of
512kbytes, addressed in parallel by the processor.Byte data with even address is transferred on D7 D0 and
byte data with odd address is transferred on

D15 D8 .The processor provides two enable signals, BHE and

A0 for selecting of either even or odd or both the banks.

FIG

BHE

A0

Function

0
0
1
1

0
1
0
1

Whole word
Upper byte/ odd address
Lower byte/even address
none

D15 D0 / A15 A0 are the

common signal line in 8086 as

AD15 AD0

If the address bus contains

FFFFOH

BHE 0 , then it reads the 16 bits data from memory location FFFFOH and FFFF1H .
If BHE 1 , it reads the 8 bits data from memory location FFFFOH
If

25. Explain the maximum mode operation of 8086

In the maximum mode of operation of 8086, wherein either a numeric coprocessor of the
type 8087 or another processor is interfaced with 8086. The Memory, Address Bus, Data Buses are shared
resources between the two processors. The control signals for Maximum mode of operation are generated by
the Bus Controller chip 8788. The three status outputs S0*, S1*, S2* from the processor are input to 8788.
The outputs of the bus controller are the Control Signals, namely DEN, DT/R*, IORC*, IOWTC*, MWTC*,
MRDC*, ALE etc. These control signals perform the same task as the minimum mode operation. However the
DEN is an active HIGH signal which has to be converted to active LOW by means of an inverter.

26. Explain the minimum mode operation of 8086

A minimum mode of 8086 configuration depicts a stand alone system of computer where no other
processor is connected. This is similar to 8085 block diagram with the following difference.
The Data transceiver block which helps the signals traveling a longer distance to get boosted up. Two
control signals data transmit/ receive are connected to the direction input of transceiver
(Transmitter/Receiver) and DEN* signal works as enable for this block.