CICeNEWS 189

2016(CIC)
Prof. Massimo Alioto

GaN25
105IC (10)

/http://www.cic.org.tw/login/login.jsp
CIC

/Publisher

267

/Publisher

www.cic.narlabs.org.tw

/Chief Editor

+886-3-5773693

/Managing Editor

+886-3-5774064

/Designer

+886-3-5783372


2016(CIC)

(CIC)
82527

2016
MorSensor

CIC Special Session

CIC
MorSensor
2016

WiFi2016 MorSensor
90
MorSensor
CIC Short Course
Low-noise and Offset Compensated Read-out Circuit for
CMOS-MEMS Accelerometer
500

2016

(
)


()

MorSensor

MorSensor

Prof. Massimo Alioto

729Massimo Alioto

Prof. Massimo Alioto

2.5D/3D IC2.5D/3D IC

Prof. Massimo AliotoMorSensor

Prof. Massimo AliotoIEEE FellowIEEE Transactions on VLSI Systems

IEEEACM50

Prof. Massimo Alioto()

(Prof. Massimo Alioto
)

(Schematic)(PreSimulation)(Layout)

(Design Rule)(Design Rule CheckDRC)

DRC(Layout Versus Schematic

LVS)DRC
LVS
Mentor GraphicsCalibreLVS
Calibre LVS

LVS
Mentor GraphicsCalibre Virtuoso-XLLaker
LayoutCalibreLVS
Calibre LVS

1.
Calibre LVS(Command Line)(Graphical User Interface
GUI)Command Lin
GUILVS
Calibre
GUI
LVSRVE(Result View Environment)

SoCCommand Line

2.
Calibre LVS(Layout vs Netlist)(Netlist
vs Netlist)(Netlist Extraction)
LVS

3.
Calibre LVS

()PIN Swapping
RVEHighlight

LVS
1. (Command Line) Rule.lvs Vi

SOURCE PATH test.src.net

(Netlist)

SOURCE PRIMARY test

(NetlistTop Cell Name)

SOURCE SYSTEM SPICE

(Netlist)

LAYOUT PATH test.gds

(GDS)

LAYOUT PRIMARY test

(GDSTop Cell Name)

LAYOUT SYSTEM GDSII

(GDS)

LVS REPORT lvs.rep

(LVS Report)

MASK SVDB DIRECTORY svdb

(RVE)

Calibre -lvs -hier -auto -turbo -64 Rule.lvs

RVE(1)SVDB DIRECTORY

1RVE
2. (GUI)Calibre LVS(2)
Command LineRun LVSRVE

2LVS
GUIGUI InputsExport from layout

view Export from schematic view Calibre

_Rule.lvs_ GUI ( 3)
Rule.lvsGUI Run LVSCalibre
-lvs _LVS.rule_Calibre LVS
RVE

10

3GUI
Command LineRule.lvsViGUI
_LVS.rule_Rule.lvs

LVS
1. LVSPIN(4)
PINLVS

4PIN

11

PINLayerRule.lvs(5)PORT Layer TEXT

LayerLayerTEXT

DEPTHALL

PRIMARYPRIMARYTOPPINPIN
(Hierarchical)LAYOUT TOP LAYER
PADME1(METAL)(VIA)

5Rule.lvs PIN
2. MOSOP
MatchMatching
NMOS W=2uL=0.5uM=3MOS(6)

6NMOS
Dummy PolyMOSPoly
PolyDummy Poly
MOSBody(7)

12

7Dummy Poly
MOSDummy MOS
MOSDummy MOS
(DGS)(8)

8Dummy MOS
Dummy MOSLVSLVS
Dummy MOSMOSLVS
(1) Calibre LVS

Calibre LVS GUILVS OptionsGatesAB(

9)LayoutNetlistMOS(DGS)
LVSDummy MOS

13

9LVS Options

Calibre LVS Command Line Rule.lvs LVS FILTER

UNUSED OPTION LayoutNetlistAB(10)
MOS(DGS)LVSDummy MOS

10Rule.lvs
GUICommand LineLVS.report1
NMOS(M=3)5NMOSAB
1(11)

14

11LVS.report
(2) Dummy MOS
NMOS(12)Dummy
MOSDummy MOS
(DGS)Body(B)NMOSBody
12

12NMOS

15

Dummy MOSDummy MOS

LVS.report(12)1NMOS(M=3)2NMOS
(M=1)5NMOS3
(13) Pre-Simulation
Dummy MOSPost-Simulation

13LVS.report
(3) Dummy MOSLVS Block Layer

Dummy MOSLVS Block LayerLayerLVS

DIFF(MOS)Layer
LayerStream Layer
DataTypeDummy MOS14

14LVS Block Layer

16

LVS Block LayerDummy MOSLVS.report

1 NMOS (M=3) 5 NMOS
Dummy MOSLVS Block Layer
1(15)

15LVS.report
3.
(Wafer)P-subPMOSN-WellPMOS
BodyNMOS
BodySourecNMOSP-sub
NMOS BodyLVS

INVINVVDDVSS
INVVCCGND(16)INV(17)PIN
(18)

162INV

17

172INV

18LVS
RVEMM2INVNMOS(16)Body
GNDVSSINVNMOS
DoubleGND
Layer(19)BodyLayerLVS Rule

20PsubDoubleGND
DoubleGND LayerPsub

18

19Layer

20LVS.rule Psub
DoubleGNDLVS(
21)

19

21LVS
DoubleGND LayerLVS
Triple-Well
NMOSBody
(Foundry)22Process AProcessB
NMOS Substrate NMOS Body
SubstrateFoundryNMOSModel
NMOSSourceNMOS
Model

22Triple-Well

20


Design Rule
FoundryTape-Out
Calibre LVSCalibre LVS
RVE

21


GaN25

WIN 0.25um GaN/SiC HEMTGaN25-105B

1. Design Kit Ver.1.2.1.3.3 (for NP25-00)

1. Design Manual Ver.1.0.2 (for NP25-00)

2. Model Handbook Ver.1.2.0 (for NP25-00)

GaN25-105B
()(Switch Item)
Diva_DRC_Readme_GaN25.pdf
GaN25CIC

(a)
CIC -> -> -> : GaN25 ->
GaN25HPDK001
(b)
CIC -> -> -> : GaN25 ->
GaN25HPDR001GaN25HPDM001

Tel(03)5773693 #201
E-Mailycchen@narlabs.org.tw

22


ICIC
102IC/ICIC
IC
104-105105IC
72288

IC

IC

105/07/22

105/07/22

105/08/08~
105/08/31

105/09/12~
105/09/30

105/10/01()

IC
http://www.cic.org.tw/icdesign

105/08/08~
105/08/31

1.
(1)
(2) ()

2.
(1)
(2)
3.
E-mail

105/09/12~
105/09/30

1.
2.
/
3.

1. (2B
)
105/10/02() 2.
3. (
)

http://www.cic.org.tw/icdesign
03-5773693*225

icdesign@cic.narl.org.tw

23

CIC

24

25

26


TN90GUTM-105C

TN90GUTM-105C-A0001

38 GHz

0.600*0.900

TN90GUTM-105C-A0003

94~102GHz

0.989*0.979

TN90GUTM-105C-A0004

15 GHz CMOS

1.070*0.930

TN90GUTM-105C-A0005

10 GHz

0.959*0.817

TN90GUTM-105C-A0006

W-band 0.976*0.802

TN90GUTM-105C-A0007

94GHz

0.989*0.913

TN90GUTM-105C-A0008a

1.655*1.653

TN90GUTM-105C-A0009a

()

0.829*0.817

TN90GUTM-105C-A0010

TN90GUTM-105C-A0011

0.585*0.770

TN90GUTM-105C-A0012

0.753*0.732

TN90GUTM-105C-A0013

5~11.7 GHz

1.375*0.863

TN90GUTM-105C-A0015

Marchand BalunV

0.760*0.970

0.729*0.486

27

()

TN90GUTM-105C-A0016

40 Gb/s

1.135*0.830

TN90GUTM-105C-A0018

0.569*0.583

TN90GUTM-105C-A0020

40 Gb/s

1.170*0.800

TN90GUTM-105C-A0021

5~12.6 GHzCMOS

1.522*0.866

TN90GUTM-105C-A0022

90 nm CMOS 5GHz~12GHz
1.210*0.817

TN90GUTM-105C-A0023

0.119mm^25.8GHz

TN90GUTM-105C-A0024

K-band CMOS
0.649*0.809

TN90GUTM-105C-A0025

10 GHz

0.572*0.679

TN90GUTM-105C-A0028

0.948*0.815

0.440*0.630

,,
94TN90GUTM-105C-A0029 ,,
GHz CMOS
,

1.816*0.715

TN90GUTM-105C-A0030

60GHz

0.790*0.720

TN90GUTM-105C-A0032

0.918*0.651
60-GHz CMOS

28

Wafer Mapping (IC)

29