ECE 6430 - Digital MOS ICs

Instructor: Prof. Kevin Kornegay, TSRB 535, 404-385-6010,

E-mail: kornegay@ece.gatech.edu

Office Hours: M, W, F 12:15-1:15 pm, or via appointment

TA Support: TBA

Lecture: MWF 10:50 - 11:50 am Van Leer C340

Prerequisites: None

Corequisites: None

Course Objective: Detailed analysis of the operation and design of high performance
MOS digital integrated circuits. Emphasis is on current design techniques with examples
from the literature. At the conclusion of this course, the student will be expected to
understand the analysis and design of key digital system building blocks.

Textbook(s):
Uyemura, CMOS Logic Circuit Design, Kluwer Academic Pub., 1999.

Class Web: http://t-square.gatech.edu (login with your GT prism account) and select the
ECE 6430 link. All homework assignments, design projects, submissions,
announcements, and course reference material can be retrieved from this site.
Course Grading Policy: Your grade will be determined using the following weighting
scheme: two in class exams (30%) on 6/11/10 and 7/9/10, one 3 hour final exam (30%)
at 8-10:50 AM on 8/2/10, and homework (10%). Grades will be assigned on a curve and
will not necessarily be consistent with 100>A>90, 90>B>80, etc.
Homework: Homework will be assigned and graded on a periodic basis.
Computer Usage: You are expected to be able to continue your use of SPICE or
PSPICE as needed.
Attendance: You are responsible for all course materials, announcements, notes, etc.
made during our regular class meeting times. Prompt arrival to class is appreciated.
Academic Honesty: It is the responsibility of the instructor to encourage an
environment where you can learn and your accomplishments will be rewarded fairly.
Any behavior which compromises the basic rules of academic honesty as described in the
General Catalog will not be tolerated.
Classroom Behavior: Smoking, drinking and eating is prohibited in the classroom by
Institute rules.
References: All reference material will be available via T-Square

Topical Outline:

MOSFETs
Physics of the MOS system
MOSFET I-V equations
Layout and parasitics

Static Logic Gates

CMOS inverter: DC and transient analysis
Pass transistor networks
Complex logic gates
Series-parallel networks
Pseudo nMOS networks and arrays
Adders
SRAM cells and arrays
Driver chain sizing
Input/Output networks

Transmission Gate Networks

CMOS TG analysis
Multiplexors
Logic networks
Adder circuits

Dynamic Logic Families

Clocks and synchronization
DRAMs
Precharge/evaluate ripple logic
Domino logic families
Basic DL analysis and modified P/E chains
Self-Resetting logic
MODL
NORA and related families
Advanced single and dual phase techniques
Clock distribution techniques
Applications to current high-performance systems design

Differential Logic Families

CVSL fundamentals
DSL and related families
Current design strategies