Misc.

Topics, Synthesis, System level

design languages
Lecture 10

TISU-Group

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TIE341 Digital Design with HDLs

Misc 1

Buffer ports
Buffer ports can be used to model designs where output
signals are also used internally in driving component
inout-port may have different value read than written, if the
actual signal associated with the port is resolved

Example:
entity counter is
port (clk, reset : in bit; count : buffer integer range 0 to 1023);
end counter;
architecture rtl of counter is
begin
countp: process(clk, reset)
begin
if (reset = '1') then
count <= 0;
elsif (clk'event and clk='1') then
count <= (count+1) mod 1024;
end if;
end process;
end rtl;

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TIE341 Digital Design with HDLs

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Misc 2

Buffer ports
Avoid using BUFFER ports. They cause easily type
conflicts in large projects (between OUT and BUFFER
types)
Better solution: internal signal
entity counter is
port (clk, reset : in bit; count : out integer range 0 to 1023);
end counter;
architecture rtl of counter is
signal count_i : integer range 0 to 1023;
-- internal count signal
begin
count <= count_i; -- internal signal associated to out port
countp: process(clk, reset)
begin
if (reset = '1') then
count_i <= 0;
elsif (clk'event and clk='1') then
count_i <= (count_I+1) mod 1024;
end if;
end process;
end rtl;

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TIE341 Digital Design with HDLs

Misc 3

Linkage port
Linkage ports are used to connect signal to foreign (non-VHDL)
design entities
Foreign language interface is simulator dependent (for example with
Modelsim linkage ports are not needed)
See simulator documentation if foreign language interface is needed

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TIE341 Digital Design with HDLs

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Misc 4

Conversion functions in association

lists
Conversion functions can be used with association lists:
f1(formal) => actual
formal => f2(actual)
f1(formal) => f2(actual)

(out, inout, buffer, linkage)

(in, inout, linkage)
(inout, linkage)

Example conversion between std_logic and std_ulogic types

component LATCH is
port (d : in std_ulogic_vector;
q : out std_ulogic_vector
...);
end component ROM;
signal source, destination : std_logic_vector(31 downto 0);
. . .
inst_latch : component latch
port map (d => std_ulogic_vector(destination),
std_logic_vector(q) => source, );

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TIE341 Digital Design with HDLs

Misc 5

Postponed processes
Postponed processes are triggered after all non-postponed
processes at the same simulation time are executed.
Example set-reset flipflop with output verification:
entity SR_flipflop is
port (s_n, r_n : in bit; q, q_n : inout bit);
begin
postponed process (q, q_n) is
begin
assert (now = 0 fs or q = not q_n)
report "implementation error: q != q_n";
end postponed process;
end SR_flipflop;
architecture dataflow of SR_flipflop is
begin
gate_1 : q <= s_n nand q_n;
gate_2 : q_n <= r_n nand q;
end dataflow;

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TIE341 Digital Design with HDLs

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Misc 6

Postponed processes
The condition that triggers a postponed process may not obtain when the
process is finally executed
because some other process may execute and remove that condition

Postponed process must not schedule transactions on signals with delta

delays
because then the postponed process should have postponed (a paradox)

Concurrent statements can be made postponed (because they are actually

only a shorter notation of process)
Concurrent assertion
postponed assert (now = 0 fs or q = not q_n)
report "implementation error: q != q_n";

Concurrent procedure call

postponed receive_frame(clock, dlines, framearray);

Concurrent signal assignment

postponed Dout <= Din after 10 ns;

Not provided in VHDL-87!

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TIE341 Digital Design with HDLs

Misc 7

Shared variables
Normal variables are defined in processes, functions or procedures.
Shared variables are visible for multiple processes
signals are also, but they represent a part of the structure of a design (serves to
interconnect modules in the design)
variables are artifacts of simulation only

Shared variables can be declared in entity declarations, architecture bodies,

block and generate statements and in packages
Example:
architecture instrumented of controller is
shared variable operation_count : natural := 0;
. . .
begin
. . .

Language specification does not define the behavior of concurrent reads and
writes to shared variable in the the same simulation cycle
shared variables consept is still in the development stage

Not provided in VHDL-87!

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TIE341 Digital Design with HDLs

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Misc 8

Synthesis issues

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TIE341 Digital Design with HDLs

Misc 9

Logic synthesis
RTL-level
code

Constraints

Logic
synthesis

Gate level
netlist

Technology
libraries

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TIE341 Digital Design with HDLs

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Misc 10

Coding for synthesis

Preferred coding style for synthesis
By following synthesis guidelines we achieve
Testability
Performance
Simplification for static timing analysis
Gate-level circuit behavior that matches to the original RTL code

Synthesis tools work best with synchronous, register based

logic
process (clock) -- synchronous reset
begin
if (clock'event and clock = '1') then
if (reset = '1') then
. . .
else
. . .
end if;
end if;
end process

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process (clock, reset) is --asynchronous reset

begin
if (reset = '1') then
. . .
elsif (clock'event and clock = '1') then
. . .
end if;
end process;

TIE341 Digital Design with HDLs

Misc 11

Partitioning
Register all outputs

clock
reset
process (clock, reset)
begin
if (reset = '1') then
output <= reset_value;
elsif (clock'event and clock = '1') then
output <= f(input);
end if;
end process;

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Misc 12

Guidelines for clocking and reset

Keep the number of clock domains as small as possible
Avoid mixed clock edges
Duty cycle of the clock becomes critical issue
some clock generators may have problems to generate 50/50 duty
cycles (especially in high clock frequencies)
Scan based testing methodologies require separate handling of positive
and negative-edge triggered flipflops

Avoid gated clocks (use enable signals instead)

Increases clock skew
Limits testability
Improper timing of a gated clock can generate glitches to clock!

Avoid internally generated clocks and resets

Testability
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TIE341 Digital Design with HDLs

Misc 13

Coding style for synthesis

Avoid combinational feedback loops
May produce races and hazards
Cannot be tested with any ATPG algorithm

comb

Bad:
comb

Good:

comb

comb

comb

comb

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Misc 14

Coding style for synthesis

Specify complete process sensitivity lists for combinational processes
RTL and gate level simulations may differ

process (a)
begin
c <= a or b
end

a
c
b

b
c

a
b

Synthesized
netlist

Post-synthesis
simulation
waveform

RTL simulation
waveform

For sequential processes, sensitivity list must include the

clock and asynchronous reset (if used) signals.
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TIE341 Digital Design with HDLs

Misc 15

Coding style for synthesis

All possible states states have to be encoded. Enumeration type must have 2n
states.

Bad:
type ample is (red, yellow, green);
Good:
type ample is (red, yellow, green, dummy);

CASE and IF statements have to decode all conditions

ELSE clause
default value

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Misc 16

Incomplete IF-statement
Entity adder is
port(a, b: in integer range 0 to 127;
ena : in boolean;
c : out integer range 0 to 255
);
end adder;
architecture bad_code of adder is
begin
add: process(a, b, ena)
begin
if (ena=true) then
c <= a + b;
end if;
end process;
end bad_code;

What happens when

ena=false?
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TIE341 Digital Design with HDLs

Misc 17

Coding state machines

Separate the state machine HDL description into two processes:
Combinational process which defines outputs and the next state
Sequential process which holds the current state

Use enumerated type for state vector

Better readability
Remember to code also unused states (so that there's 2n states)
Other possibility is "one hot" state encoding, i.e. one flipflop for each state

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TIE341 Digital Design with HDLs

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Misc 18

State machine example

architecture rtl of entname is
type state_type is (s0, s1, s2, s3);
signal state, next_state : state_type;
signal con1, con2, con3 : std_ulogic;
signal out1, out2 : std_ulogic;
signal clk, reset : std_ulogic;
-- . . .
begin
state_logic : process (state, con1, con2,
con3) is
begin
case state is
when s0 =>
out1 <= '0';
out2 <= '0';
next_state <= s1;
when s1 =>

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out1 <= '1';

if con1 = '1' then
next_state <= s2;
else
next_state <= s1;
end if;
when s2 =>
out2 <= '1';
next_state <= s3;
when s3 =>
if con2 = '0' then
next_state <= s3;
elsif con3 = '0' then
out1 <= '0';
next_state <= s2;
else
next_state <= s1;
end if;
end case;
end process state_logic;

TIE341 Digital Design with HDLs

state_register : process (clk, reset)

is
begin
if reset = '0' then
state <= s0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process state_register;
end architecture rtl;

Misc 19

Coding style for synthesis

Avoid asynchronous logic
Asynchronous logic is difficult to design and verify. Correct timing and
functionality may be technology dependent
If asynchronous logic is needed, partition design so that asynchronous
logic is in separate module

Avoid glue logic at the top level

Generally synthesis tools cannot work across module boundaries.
Combinational logic at the top level could not be optimized
Try to partition code so that VHDL architectures contain either structural
code (component instantiations) or functional code (processes).

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TIE341 Digital Design with HDLs

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Misc 20

System level design languages

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TIE341 Digital Design with HDLs

Misc 21

System level design

System on Chip (SoC)

uP
core

User
logic

memory

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Std
interface

User logic

DSP
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3rd
party
IP

Misc 22

SoC design flow

Environment
Specify
Product

Hardware

Software
Co-Design

Implement
Co-Verify
Verify

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Code

Reuse
IP

Reuse
IP

SW Code
Implement

Design

HW Design
Reusable
IP
Integration

Implement

System
to
RTL

RTL
to
GDSII

Verify

Verify

TIE341 Digital Design with HDLs

Misc 23

SystemC
SystemC is C++ -based system level design language
C++ unifies hardware and software design

SystemC is an ANSI C++ based class library and methodogy for

creating cycle-accurate model of software, hardware and interfaces on
SoC
For HW modeling: notion of time (clocks), concurrency, processes,
signals, HW data types
For SW modeling: interrupts
For system modeling: abstract communication
Can be compiled, linked and debugged with public domain standards
compatible tools (GCC 2.95 and DDD 3.2)
Current version (2.0) of class library can be freely downloaded from
www.systemc.org

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Misc 24

Abstraction levels in SystemC

Untimed functional (UTF) level
System is decomposed into functional modules which communicate over
abstract communication channels
All concurrent processes are executed at zero time
"Executable specification"

Timed functional (TF) level

Some processes can be assigned a run time

Bus cycle accurate (BCA) model

Processes in system are synchronized using a clock signal for transactions
Behavior may be left untimed

Cycle accurate (CA) level

system behavior is clock cycle accurate (~RTL)

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TIE341 Digital Design with HDLs

Misc 25

SystemC design flow

UTF

Design exploration
Performance analysis

TF
HW/SW partition

Multitasking
Abstract RTOS
Inter process comm.
Scheduling / priority

Target RTOS

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Abstr.
RTOS

BCA

Abstr.
RTOS

CA
(RTL)

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Misc 26

HW/SW partitioning in systemC

Communication
Communication and behavior separated
Master / slave ports
RPC mechanism (process can call a function in another module)

P1
(master)

P2
(slave)

Built-in bus protocols

Full handshake, enable handshake, no handshake
Point-to point (p2p) and multipoint (mp) communication
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TIE341 Digital Design with HDLs

Misc 27

System C
Fixed point types
suitable for e.g. signal processing applications

Fixed precision integer types

Modularity through C++ objects
Modules
Processes

C++ streams
Tools from EDA vendors

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Misc 28

Example of SystemC code: Main

int sc_main (int argc , char *argv[]) {
// top level signals and variables
sc_signal< sc_lv<13> >
sc_signal< my_custom_type >

signal_in;
signal_out;

sc_clock main_clk("MAIN_CLOCK", 10, 0.5, 0.0); // generate master clock

source source1("Test_bench_source");
source1 << main_clk << signal_in;

// test bench source

ex_module ex1("Our_DUT");
// DUT(synthesizable part)
ex1 << main_clk << signal_in << signal_out;
sink sink1("Test_bench_sink");
sink1 << main_clk << signal_out;

// test bench sink

sc_start( main_clk, -1 ); // starts clock

return 0;
}

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TIE341 Digital Design with HDLs

Misc 29

Example of SystemC module

declaration
// example module declaration
SC_MODULE(ex_module) {
// inputs and output ports to module
sc_in_clk
CLK;
sc_in< sc_lv <13> >
in_port1;
sc_out<my_custom_type >
out_port2;
// local variables
sc_uint<26>
sc_int<32>

local_variable;
array[16];

void ex_process();
//Constructor
SC_CTOR(ex_module) {
SC_CTHREAD(ex_process, CLK.pos());
}
//Destructor
~ ex_module() { }
};

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Misc 30

Example of SystemC process

void ex_module::ex_process(void) {
// process_variables
sc_int<4>
index;
// initializations
local_variable = SETUP_VALUE;
for (index=0 ;index<16 ; index++)
array[index] = 0;
// process body
while (1) {

wait(); // wait at clock

}
}

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Misc 31