ECE 4141 VLSI Design

Created by Ahmad Anwar Zainuddin and Dr. Anis Nurashikin Nordin

Experiment 2: Inverter Pspice Simulation

Overview
The main goal of this tutorial is to walk through using the analog simulator ( Pspice).

To perform a DC simulation to plot a VTC curve (voltage transfer characteristic) for inverter
To perform a DC simulation and combine it with a parametric analysis to optimize transistor
sizes for an inverter

CMOS Technology : 0.35um

Introduction:
An inverter circuit outputs a voltage representing the opposite logic-level to its input. Inverters can be
constructed using a single NMOS transistor or a single PMOS transistor coupled with a resistor. Since
this 'resistive-drain' approach uses only a single type of transistor, it can be fabricated at low cost.
However, because current flows through the resistor in one of the two states, the resistive-drain
configuration is disadvantaged for power consumption and processing speed. Alternatively, inverters
can be constructed using two complementary transistors in a CMOS configuration. This configuration
greatly reduces power consumption since one of the transistors is always off in both logic states.
Processing speed can also be improved due to the relatively low resistance compared to the NMOS-only
or PMOS-only type devices. Inverters can also be constructed with bipolar junction transistors (BJT) in
either a resistortransistor logic (RTL) or a transistortransistor logic (TTL) configuration.

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Inverter Pspice Tutorial

1. Select File and hit New Project . After that, name your project in the Name and location path
Then click OK to continue.

After that, name your project in the Name and location path Then selectAnalog or Mixed A/D
to continue.Then hit OK.

Select Create a blank project . Then hit OK. The Pspice schematic interface is shown and may
start the circuit construction.

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2. On the Pspice schematic, select Place and click on Part.

Then find all needed components (full inverter circuit as depicted below) and plug and place them
on the schematic board interface. Put voltage source of V1=3.5Volts and V2= 3.5Volts. This is
because we are using 0.35um technology file, the minimum is 3.5Volts.

V1

P1

3.5

M2

0
V1 = 3.5
V2 = 0
TD = 0
TR = 10ns
TF = 10ns
PW = 1u
PER = 2u

V2

V
V

M1
N1

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Thing to remember:
Since we are dealing with the model of 0.35 um CMOS technology, make sure the code sourcefile
.model as shown below is replaced inside Pspice PMOS and NMOS devices.
* n-MOS Model 3 :
* Standard
.MODEL N1 NMOS LEVEL=3 VTO=0.60 KP=200.000E-6
+LD =0.000U THETA=0.300 GAMMA=0.400
+PHI=0.300 KAPPA=0.010 VMAX=130.00K
+CGSO= 0.0p CGDO= 0.0p
*
* p-MOS Model 3:
* high speed pMOS
.MODEL P1 PMOS LEVEL=3 VTO=-0.60 KP=52.000E-6
+LD =0.000U THETA=0.300 GAMMA=0.400
+PHI=0.300 KAPPA=0.010 VMAX=100.00K
+CGSO= 0.0p CGDO= 0.0p

Method:
a. Open the PSpice and paste the .model from source file. Click on the NMOS device> right
click> Edit PSpice Model.

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b. Replace the model and save it properly.

c. Repeat the same thing to PMOS by copying the PMOS .model netlist

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3. After complete the inverter circuit. Click on New Simulation Profile.

To run DC Analysis, create your simulation name dc analysis.

Then, in this section, Select DC Sweep analysis and click on Primary Sweep. Fill in the name of
voltage source and define your sweep type.

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4. Run the DC simulation. Output is shifted to the left

This graph is known as the voltage transfer characteristic curve (VTC).

The plot window will appear showing the voltage across the capacitor (the load) on the y-axis, vs.
the input voltage to the inverter, swept from 0 to 3.5 volts, on the x-axis
Find the x-coordinate: 1.75 volts and determine the y-coordinate from the result.
However, it shows the X-coordinate Y-Coordinate.
Because our NMOS and PMOS have different resistance values when they are ON when x=1.75
volts, y is not equal to 1.75. We must change the size of our devices to make the ON resistance
of the PMOS and NMOS equal for our inverter. We will do this by using a parametric sweep
analysis to help us size our devices.

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5. Prior to Parametric Sweep Analysis. It is important to know how to change the width and length
of both PMOS and NMOS basically.
a) Double click on the PMOS and NMOS devices. Then it displays the length and width channel.
For PMOS device, make it (W/L) to (2.2um/0.4um), whilst NMOS device turn (W/L) to
(1.4um/0.4um).
Length Channel

Width Channel

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b) Re-simulate the circuit and find the output as well.

The adjustment of W/L for both devices

The VTC Output

However, same result was obtained. It shows the X-coordinate Y-Coordinate.

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6. Then we move to parameter sweep to figure out the X-coordinate = Y-Coordinate.

We can obtain and adjust the PMOS Width.
a)

Place part > PARAM/SPECIAL and click ok.

b) Double click on PARAMETERS:

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c)

Add new row and apply. Please put name as width and value = 1u.

d) The new width section was created. Then, please double click on it and choose Display
name and value.
e)

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f)

Set the global parameter. Double click at PMOS width and set value= {width}

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g) Set the PMOS using DC Sweep.

h) Run and simulate the output

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i)

Four VTC outputs are plotted as shown in figure below. (Vin vs. Vout of the inverter). Each
curve represents a DC analysis, using a different value of the W,width parameter.

j)

The value of W for each graph is listed along the top of the graph, and it is color
coordinated. Find out that which Width parameter exhibits the x-coordinate = y-coordinate
= 1.75 volts.

k) Otherwise the Width needs to be re-adjusted again to obtain the optimum size of the
PMOS.
7. Once you have found the value for w that makes the output wave pass through the midpoint,
1.75 volts, you have perfectly sized the PMOS transistor to match the NMOS transistor.
Essentially, they now have the same value for their resistance is equal when operating.
8. Save your simulation state. Edit your inverter schematic, and change the PMOSs width to be
equal to the value you have obtained it.

Home Work: (Dateline: 4 November 2015 )

Design and simulate a NAND gate device using SPICE. Essentially you have to calculate theoretically the
optimum size for the PMOS. Then, you may repeat the procedures above trying both of its inputs
together to size the transistors in a NAND gate.

Prepared by: Ahmad Anwar Zainuddin