EXPERIMENT-3

AIM- To implement and verify the functionality of 2 input NAND and NOR gate using S-Edit.
TOOLS REQUIRED- S-Edit Tanner Tool, T-Spice 12..6
SCHEMATICa) NAND gate

Schematic for 2 input NAND gate

T-SPICE CODEa) NAND gate

.model nmos nmos
.model pmos pmos
vdd vdd gnd 5v
.tran 1n 100n
VIn In gnd PULSE(0 5 0 1n 1n 10n 20n)
VIn2 In2 gnd PULSE(0 5 0 1n 1n 10n 20n)
.print v(Out) v(In) v(In2)
.end

OUTPUT- a) NAND gate

Output of 2 input NAND gate

SCHEMATICb) NOR gate

Schematic for 2 input NOR gate

T-SPICE CODEb) NOR gate

.model nmos nmos
.model pmos pmos
vdd vdd gnd 5v
.tran 1n 100n
VIn In gnd PULSE(0 5 0 1n 1n 10n 20n)
VIn2 In2 gnd PULSE(0 5 0 1n 1n 10n 20n)
.print v(Out) v(In) v(In2)
.end

OUTPUT- b) NOR gate

Output of 2 input NOR gate

RESULT-

The truth table for 2 input NAND gate is as follows:

A
0
0
1
1

B
0
1
0
1

C=(AB)
1
1
1
0

The truth table for 2 input NOR gate is as follows:

A

0
0
1
1

0
1
0
1

The above mentioned truth tables are verified.

C=(A+B)

1
0
0
0