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Instructions Language of The Computer
Instructions Language of The Computer
Instructions Language of The Computer
Instructions: Language
of the Computer
2.1 Introduction
Instruction Set
Simplified implementation
n
n
add a, b, c # a gets b + c
All arithmetic operations have this form
Design Principle 1: Simplicity favours
regularity
Arithmetic Operations
Arithmetic Example
n
C code:
f = (g + h) - (i + j);
# temp t0 = g + h
# temp t1 = i + j
# f = t0 - t1
Assembler names
n
n
Register Operands
C code:
f = (g + h) - (i + j);
n f, , j in $s0, , $s4
Memory Operands
n
FIGURE 2.3 Actual MIPS memory addresses and contents of memory for those words. The changed addresses are
highlighted to contrast with Figure 2.2. Since MIPS addresses each byte, word addresses are multiples of 4: there are 4
bytes in a word. Copyright 2009 Elsevier, Inc. All rights reserved.
C code:
g = h + A[8];
n g in $s1, h in $s2, base address of A in $s3
lw $t0, 32($s3)
add $s1, $s2, $t0
offset
# load word
base register
C code:
A[12] = h + A[8];
n h in $s2, base address of A in $s3
Immediate Operands
n
Cannot be overwritten
n
n
Range: 0 to +2n 1
Example
n
Using 32 bits
n
0 to +4,294,967,295
Chapter 2 Instructions: Language of the Computer 15
n
n
Range: 2n 1 to +2n 1 1
Example
n
Using 32 bits
n
2,147,483,648 to +2,147,483,647
Chapter 2 Instructions: Language of the Computer 16
n
n
Signed Negation
n
Complement means 1 0, 0 1
x + x = 1111...1112 = 1
x + 1 = x
Example: negate +2
n
n
Sign Extension
n
MIPS instructions
n
n
Register numbers
n
n
n
Representing Instructions
op
rs
rt
rd
shamt
funct
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
Instruction fields
n
n
n
n
n
n
R-format Example
op
rs
rt
rd
shamt
funct
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
$s1
$s2
$t0
add
17
18
32
000000
10001
10010
01000
00000
100000
000000100011001001000000001000002 = 0232402016
Chapter 2 Instructions: Language of the Computer 22
Hexadecimal
n
Base 16
n
n
0
1
2
3
n
4
5
6
7
0100
0101
0110
0111
8
9
a
b
1000
1001
1010
1011
c
d
e
f
1100
1101
1110
1111
rs
rt
constant or address
6 bits
5 bits
5 bits
16 bits
op
Instructions represented in
binary, just like data
Instructions and data stored
in memory
Programs can operate on
programs
n
Standardized ISAs
Java
MIPS
Shift left
<<
<<
sll
Shift right
>>
>>>
srl
Bitwise AND
&
&
and, andi
Bitwise OR
or, ori
Bitwise NOT
nor
Logical Operations
Shift Operations
n
n
rs
rt
rd
shamt
funct
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
op
AND Operations
n
$t1
$t0
OR Operations
n
$t1
$t0
NOT Operations
n
Change 0 to 1, and 1 to 0
a NOR b == NOT ( a OR b )
Register 0: always
read as zero
$t1
$t0
Conditional Operations
j L1
n
Compiling If Statements
n
C code:
if (i==j) f = g+h;
else f = g-h;
n
f, g, in $s0, $s1,
C code:
while (save[i] == k) i += 1;
n
$t1,
$t1,
$t0,
$t0,
$s3,
Loop
$s3, 2
$t1, $s6
0($t1)
$s5, Exit
$s3, 1
Basic Blocks
n
Otherwise, set to 0
n
n
1 < +1 $t0 = 1
# unsigned
Steps required
1.
2.
3.
4.
5.
6.
Procedure Calling
Register Usage
n
n
n
n
n
n
n
C code:
int leaf_example (int g, h, i, j)
{ int f;
f = (g + h) - (i + j);
return f;
}
n Arguments g, , j in $a0, , $a3
n f in $s0 (hence, need to save $s0 on stack)
n Result in $v0
MIPS code:
leaf_example:
addi $sp, $sp, -4
sw
$s0, 0($sp)
add $t0, $a0, $a1
add $t1, $a2, $a3
sub $s0, $t0, $t1
add $v0, $s0, $zero
lw
$s0, 0($sp)
addi $sp, $sp, 4
jr
$ra
Procedure body
Result
Restore $s0
Return
Non-Leaf Procedures
n
n
C code:
int fact (int n)
{
if (n < 1) return f;
else return n * fact(n - 1);
}
n Argument n in $a0
n Result in $v0
MIPS code:
fact:
addi
sw
sw
slti
beq
addi
addi
jr
L1: addi
jal
lw
lw
addi
mul
jr
$sp,
$ra,
$a0,
$t0,
$t0,
$v0,
$sp,
$ra
$a0,
fact
$a0,
$ra,
$sp,
$v0,
$ra
$sp, -8
4($sp)
0($sp)
$a0, 1
$zero, L1
$zero, 1
$sp, 8
$a0, -1
0($sp)
4($sp)
$sp, 8
$a0, $v0
#
#
#
#
#
#
#
#
#
#
#
#
#
#
if so, result is 1
pop 2 items from stack
and return
else decrement n
recursive call
restore original n
and return address
pop 2 items from stack
multiply to get result
and return
Memory Layout
n
n
95 graphic, 33 control
ASCII, +96 more graphic characters
Character Data
Byte/Halfword Operations
n
n
lb rt, offset(rs)
n
sb rt, offset(rs)
n
lh rt, offset(rs)
sh rt, offset(rs)
C code (nave):
Null-terminated string
void strcpy (char x[], char y[])
{ int i;
i = 0;
while ((x[i]=y[i])!='\0')
i += 1;
}
n Addresses of x, y in $a0, $a1
n i in $s0
n
MIPS code:
strcpy:
addi
sw
add
L1: add
lbu
add
sb
beq
addi
j
L2: lw
addi
jr
$sp,
$s0,
$s0,
$t1,
$t2,
$t3,
$t2,
$t2,
$s0,
L1
$s0,
$sp,
$ra
$sp, -4
0($sp)
$zero, $zero
$s0, $a1
0($t1)
$s0, $a0
0($t3)
$zero, L2
$s0, 1
0($sp)
$sp, 4
#
#
#
#
#
#
#
#
#
#
#
#
#
lhi $s0, 61
ori $s0, $s0, 2304 0000 0000 0111 1101 0000 1001 0000 0000
32-bit Constants
Branch Addressing
n
Forward or backward
op
rs
rt
constant or address
6 bits
5 bits
5 bits
16 bits
PC-relative addressing
n
n
Jump Addressing
n
address
6 bits
26 bits
80000
19
add
80004
22
32
lw
$t0, 0($t1)
80008
35
bne
21
80016
19
19
80020
Loop: sll
Exit:
Loop
20000
80024
bne $s0,$s1, L2
j L1
L2:
Synchronization
Synchronization in MIPS
n
n
Returns 1 in rt
Returns 0 in rt
$t0,$zero,$s4
$t1,0($s1)
$t0,0($s1)
$t0,$zero,try
$s4,$zero,$t1
Static linking
Assembler Pseudoinstructions
n
n
n
Loading a Program
n
Dynamic Linking
n
Lazy Linkage
Indirection table
Stub: Loads routine ID,
Jump to linker/loader
Linker/loader code
Dynamically
mapped code
Compiles
bytecodes of
hot methods
into native
code for host
machine
Interprets
bytecodes
C Sort Example
$s2, $a0
$s3, $a1
$s0, $zero
$t0, $s0, $s3
$t0, $zero, exit1
$s1, $s0, 1
$t0, $s1, 0
$t0, $zero, exit2
$t1, $s1, 2
$t2, $s2, $t1
$t3, 0($t2)
$t4, 4($t2)
$t0, $t4, $t3
$t0, $zero, exit2
$a0, $s2
$a1, $s1
swap
$s1, $s1, 1
for2tst
$s0, $s0, 1
for1tst
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
Move
params
Outer loop
Inner loop
Pass
params
& call
Inner loop
Outer loop
addi $sp,$sp, 20
sw $ra, 16($sp)
sw $s3,12($sp)
sw $s2, 8($sp)
sw $s1, 4($sp)
sw $s0, 0($sp)
#
#
#
#
#
#
#
#
#
#
#
#
#
#
140000
Instruction count
120000
2.5
100000
80000
1.5
60000
40000
0.5
20000
0
none
O1
O2
Clock Cycles
180000
160000
140000
120000
100000
80000
60000
40000
20000
0
none
O3
O1
O2
O3
O2
O3
CPI
2
1.5
1
0.5
0
none
O1
O2
O3
none
O1
3
2.5
2
1.5
1
0.5
0
C/none
C/O1
C/O2
C/O3
Java/int
Java/JIT
2.5
2
1.5
1
0.5
0
C/none
C/O1
C/O2
C/O3
Java/int
Java/JIT
3000
2500
2000
1500
1000
500
0
C/none
C/O1
C/O2
C/O3
Java/int
Java/JIT
Lessons Learnt
n
move $t0,$zero
loop1: sll $t1,$t0,2
add $t2,$a0,$t1
move $t0,$a0
# p = & array[0]
sll $t1,$a1,2
# $t1 = size * 4
add $t2,$a0,$t1 # $t2 =
#
&array[size]
loop2: sw $zero,0($t0) # Memory[p] = 0
addi $t0,$t0,4 # p = p + 4
slt $t3,$t0,$t2 # $t3 =
#(p<&array[size])
bne $t3,$zero,loop2 # if ()
# i = 0
# $t1 = i * 4
# $t2 =
#
&array[i]
sw $zero, 0($t2) # array[i] = 0
addi $t0,$t0,1
# i = i + 1
slt $t3,$t0,$a1 # $t3 =
#
(i < size)
bne $t3,$zero,loop1 # if ()
# goto loop1
# goto loop2
n
n
MIPS
1985
1985
Instruction size
32 bits
32 bits
Address space
32-bit flat
32-bit flat
Data alignment
Aligned
Aligned
15 32-bit
31 32-bit
Memory
mapped
Memory
mapped
Date announced
Instruction Encoding
Further evolution
n
Pentium 4 (2001)
n
n
New microarchitecture
Added SSE2 instructions
Chapter 2 Instructions: Language of the Computer 83
And further
n
n
Register
Register
Register
Immediate
Register
Memory
Memory
Register
Memory
Immediate
Address in register
Address = Rbase + displacement
Address = Rbase + 2scale Rindex (scale = 0, 1, 2, or 3)
Address = Rbase + 2scale Rindex + displacement
Chapter 2 Instructions: Language of the Computer 86
Variable length
encoding
Postfix bytes specify
addressing mode
n Prefix bytes modify
operation
n
Operand length,
repetition, locking,
Implementing IA-32
n
n
n
Simple instructions: 11
Complex instructions: 1many
Fallacies
Fallacies
n
Pitfalls
n
Increment by 4, not by 1!
Design principles
1.
2.
3.
4.
Layers of software/hardware
n
Concluding Remarks
c.f. x86
Concluding Remarks
n
Instruction class
MIPS examples
SPEC2006 Int
SPEC2006 FP
Arithmetic
16%
48%
Data transfer
35%
36%
Logical
12%
4%
Cond. Branch
34%
8%
Jump
j, jr, jal
2%
0%