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SR Latch Differential Input Latch: VDD M2 M1 M6 M5 CLK CLK VDD
SR Latch Differential Input Latch: VDD M2 M1 M6 M5 CLK CLK VDD
M2
M1
M6
M5
CLK
VDD
O+
M6
M3
M7
M7
M5
M4
VDD
SR1
VDD
CLK
out+
OUT+
SR
out-
OUT-
VDD
O-
O+
OUT-
M2
OUT+
M0
R
M3
VDD
M8
M4
M0
M1
IN+
IN-
O-
VDD
IN+
IN-
V_in+
V_in-
V_CLK
val0=0.0
val1=1.2
val0=1.2
val1=0
val0=0.0
val1=1.2
M9
gnd
gnd
CLK
gnd
gnd
SR Latch
CLK
0.6
0.4
0.2
SEL>>
-0.106
OUT+
1.2
1
0.8
0.6
0.4
0.2
0
OUT1.2
1
0.8
0.6
0.4
0.2
0
R
1.2
1
0.8
0.6
0.4
0.2
0
0
10n
20n
30n
40n
50n
S
SymSpice
time, s
60n
70n
80n
90n
100n
1.2
0.8
0.4
0
CLK
1.9
1.6
V
1.2
0.8
SEL>>
-0.1
IN+
1.9
1.6
V
1.2
0.8
0.4
0
IN2
1.6
V
1.2
0.8
0.4
0
out+
2
1.6
V
1.2
0.8
0.4
0
0
0.5n
1n
1.5n
2n
2.5n
outSymSpice
time, s
3n
3.5n
4n
4.5n
5n
M10
M11
VDD
M8
A
VDD
M0
M3
A
M1
VDD
IN
OUT
IN
Abar
M1
Bbar
M5
M6
M1
Bbar
M7
B
OUT
M0
M1
B
A
out
VDD
M9
Abar
M0
M0
out
M2
Abar
M3
A
A
M2
gnd
Transmission Gate
Bbar
XOR Gate
CLK
Vdd
CLKbar
M8
M3
VDD
M5
Vdd
Vdd
Q
M4
Data
gnd
gnd
M7
M2
gnd
gnd
CLK
CLKbar
gnd
Vdd
M15
CLKbar
PHIbar
Vdd
CLK
Vdd
PHI
M14
gnd
Vdd
M17
CLK
CLKbar
M16
M1
M9
M0
M6
gnd
Regular FF
gnd
M4
B
gnd
NOR Gate
M11
Inverter
gnd
M10
gnd
Vdd
INV
IN
Data
Vdd
CLK
OUT
I2
IN
OUT
IN
PHIbar
I3
INV
regular_FF
PHI
OUT
IN
INV
VDD
I0
TG
PHIbar
VDD
VDD
Vdd
PHIbar
Vdd
I1
PHI
OUT
VDD
I4
VDD
VDD
Vdd
Data
out
out
I5
XOR
I6
Vdd
VDD
VDD
INV
VDD
IN
Vdd
VDD
OUT
I1
Vdd
PHIbar
NOR
B
PHI
PHIbar
CLK
VDD
V_Data
V_CLK
val0=0.0
val1=1.1
val0=0.0
val1=1.1
gnd
gnd
CLK
clk_gatin_ckt
D
Q
I0
0.8
0.4
SEL>>
-0.1
CLK
1.2
0.8
0.4
0
D
1.2
0.8
0.4
0
Q
1.2
0.8
0.4
0
PHI
1.2
0.8
0.4
0
0
10n
20n
30n
40n
50n
PHIbar
SymSpice
time, s
60n
70n
80n
90n
100n
0.6
0.4
0.2
SEL>>
-0.1
CLK
1.2
1
0.8
0.6
0.4
0.2
0
-0.1
Data
1.2
1
0.8
0.6
0.4
0.2
0
-0.121
0
10n
20n
30n
40n
50n
Q
SymSpice
time, s
60n
70n
80n
90n
100n