Professional Documents
Culture Documents
Dsd&Dica Lab
Dsd&Dica Lab
LABORATORY MANUAL
For
DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING
CERTIFICATE
Department
Program
B.Tech
Year
III Year
Semester
I Semester
IQAC Members
Name
Signature(s)
:
:
HOD - ECE
CONTENTS
S.NO
DESCRIPTION
PAGE NO
1.
Course Description
2.
General Instructions
3.
Additional Instructions
vi
4.
University Syllabus
vii
5.
List of Experiments
viii
6.
ix
7.
11
8.
3 to 8 Decoder-74138
23
9.
28
10.
4-Bit Comparator-7485
36
11.
D-Flip-Flop-7454
41
12.
Decade Counter-7490
45
13.
4-Bit Counter-7493
50
14.
Shift Register-7495
55
15.
60
16.
65
17.
68
18.
ALU design
71
ADDITIONAL EXPERIMENTS
19.
76
20.
8 X 3 Encoder
83
21.
T-Flip-Flop
89
PEO 1
PEO 2
Our Graduates will function effectively as individual and within a team with good
leadership qualities.
PEO 3
Our Graduates will recognize the need for continuous self-improvement and with
good moral values.
Page i
Programme Outcomes
An ability to design and conduct experiments, as well as to analyze and interpret data
c
d
An ability to design a system, component, or process to meet desired needs within realistic
constraints such as economic, environmental, social, political, ethical, health and safety
manufacturability,
andon
sustainability
An ability to function
multidisciplinary teams
h
i
An ability to use the techniques, skills, and modern engineering tools necessary for
engineering practice
An ability to implement MATLAB, Embedded systems design for electronics and
communications engineering applications.
Course Objectives:
To expose the students to basic principle of operation of Digital Circuits with experimental
experience and also to impart industry oriented learning.
Course Outcomes:
S.No
Course Outcomes
Student gains knowledge about simulation of design of logic gates using VHDL
1
Programming Language on Xilinx Software Package
Student gains Knowledge about simulation of design of 8 x 1 Multiplexer 74151 and 2 x
4 de-multiplexer 74155 using VHDL Programming Language on Xilinx Software
2
Package
Student gains Knowledge about simulation of design of D-Flip Flop 7474 using VHDL
3
Programming language on Xilinx Software package
Student gains Knowledge about simulation of design of Shift registers using VHDL
4
Programming language on Xilinx Software package
Page ii
S.No
Programme
Programme
Educational
Outcomes
Objectives
Course Outcomes
Student gains knowledge about simulation of design of
logic gates using VHDL Programming Language on
Xilinx Software Package
Student gains Knowledge about simulation of design of 8 x
1 Multiplexer 74151 and 2 x 4 de-multiplexer 74155 using
VHDL Programming Language on Xilinx Software Package
Student gains Knowledge about simulation of design of DFlip Flop 7474 using VHDL Programming language on
Xilinx Software package
Student gains Knowledge about simulation of design of
Shift registers using VHDL Programming language on
Xilinx Software package
PEO I
PEO I
PEO I
PEO I
Assessment Strategy
A variety of learning strategies are used throughout the course.
S.No
different Teaching
Criteria
Day to Day Work
Record
Internal Examination
Total Marks
Marks
10
5
10
25
Page iii
Criteria
Pre practical
Practical
Post practical
Viva
Total Marks
Marks
30
10
10
10
50
Criteria
Internal
External
Total Marks
Marks
25
50
75
GENERAL INSTRUCTIONS
SAFETY:
1. When students are doing experiment they have to be very care full.
2. Students should have the prior knowledge about the lab they are doing.
3. If any kind of wrong thing happened while doing the experiment. Students have to
immediately switch off power supply on the work table.
4. Wearing loose garments inside the lab is strictly prohibited .
ATTENDANCE:
1. Students have to come to the laboratory with proper dress code and ID Cards.
2. Students have to bring Observation note book , Record note book and calculators etc.. to
the Laboratory.
3. Students have to sign in the log register after entering into the lab and before leaving the
laboratory.
4. Students have to show their observations with results after completion of their experiments
and they have to get is signed.
5. After completion of experiment students have to submit their completed records to the
faculty of their lab with in a week.
Page iv
RECORD:
1. As the name Implies, it is a record: permanent record for reference. Write neatly; Draw
circuit diagrams neatly and label correctly.
2. Complete the record before you come for next lab class.
3. Bring the record for submission during next lab class.
Page v
Page vi
T P C
0 3 2
1.
Gates
2.
3.
4.
5.
D- Flip-Flop - 7474
6.
7.
8.
9.
10.
11.
12.
ALU design
Page vii
Page viii
II CYCLE
8. Decade Counter-7490
9. 4-Bit Counter-7493
10. Shift Register-7495
11. Universal Shift Registers-74194/95
12. RAM (16X4)-74189(Read and Operation)
13. Stack and Queue implementation using RAM
14. ALU design
15. 8 X 3 Encoder
Page ix
iii. The current status of the ISE project is maintained when exiting the
software.
iv. To restart your session, start the ISE software again. ISE displays the
contents and state of your project with the last saved changes.
Accessing Help
At any time during the tutorial, you can access online help for additional information about
a variety of topics and procedures in the ISE software as well as related tools.
Page 1
Page 2
When the table is complete, your project properties should look like the following:
Page 3
Click New Source in the New Project Wizard to add one new source to your project.
Select VHDL Module as the source type in the New Source dialog box.
Type in the file name and gate.
Verify that the Add to project checkbox is selected.
Click Next.
Define the ports for your VHDL source.
Page 4
In the Port Name column, type the port names on three separate rows: a, b and c.
In the Direction column, indicate whether each port is an input, output, or inout.
For a, b select in from the list. For c select out from the list.
Page 5
Page 6
Page 7
Click on the Simulation button from menu bar and select the
source name.
Page 8
Page 9
Assign the values and run the constants the output waveform is
Page 10
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs
and
one
output.
At
any
given
moment,
every
terminal
is
in
one
of
the
two binary conditions low (0) or high (1), represented by different voltage levels. The logic state
of a terminal can, and generally does, change often, as the circuit processes data. In most logic
gates, the low state is approximately zero volts (0 V), while the high state is approximately five
volts positive (+5 V).
AND:
The AND gate is so named because, if 0 is called "false" and 1 is called "true," the gate acts in
the same way as the logical "and" operator.
OR:
The OR gate gets its name from the fact that it behaves after the fashion of the logical inclusive
"or." The output is "true" if either or both of the inputs are "true." If both inputs are "false," then
the output is "false."
NOR:
The NOR gate is a combination OR gate followed by an inverter. Its output is "true" if both
inputs are "false." Otherwise, the output is "false."
Page 11
PIN DIAGRAMS:
AND GATE
Input
OR GATE
Output
Input
Output
PROCEDURE:
Enter your project name and project setting select automotive Spartan 3E in family.
Page 12
Go to project, click on new source. A new source wizard will open. Select VHDL module
and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
If any syntax errors occur they will appear on console window while compiling.
In process window click ISM simulator, now click on behavioral check syntax, simulate
behavioral model.
Select your input & click on force constant. Enter value in force clock to value.
Page 13
Step 4: End
Page 14
Page 15
OR GATE ALGORITHM:
Page 16
Page 17
Page 18
Page 19
Step 4: End
Page 20
Page 21
VIVA QUESTIONS:
1. Implement the following function using VHDL coding. (Try to minimize if you can).
F(A,B,C,D)=(A+B+C) . (A+B+D). (B+C+D) . (A+B+C+D)
2. What will be the no. of rows in the truth table of N variables?
3. What are the advantages of VHDL?
4. Design Ex-OR gate using behavioral model?
5. Implement the following function using VHDL code f=AB+CD.
6. What are the differences between half adder and full adder?
7. What are the advantages of minimizing the logical expressions?
8. What does a combinational circuit mean?
9. Implement the half adder using VHDL code?
10. Implement the full adder using two half adders and write VHDL program in structural
model?
Page 22
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
In digital electronics, a decoder can take the form of a multiple-input, multiple-output
logic circuit that converts coded inputs into coded outputs, where the input and output codes are
different e.g. n-to-2n , binary-coded decimal decoders. Decoding is necessary in applications
such as data multiplexing, 7 segment display and memory address decoding.
3:8 decoder
It uses all AND gates, and therefore, the outputs are active- high. For active- low outputs,
NAND gates are used. It has 3 input lines and 8 output lines. It is also called as binary to octal
decoder it takes a 3-bit binary input code and activates one of the 8(octal) outputs corresponding
to that code.
PIN DIAGRAM:
Page 23
PROCEDURE:
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module
and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
If any syntax errors occur they will appear on console window while compiling.
In process window click ISM simulator, now click on behavioral check syntax, simulate
behavioral model.
Select your input & click on force constant. Enter value in force clock to value.
ALGORITHM:
Page 24
Page 25
Page 26
VIVA QUESTIONS:
Page 27
AIM:
To design and simulate MUX & DEMUX using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
Multiplexing is defined as the process of feeding several independent signals to a common load,
one at a time. The device or switching circuitry used to select and connect one of these several
signals to the load at any one time is known as a multiplexer.
The reverse function of multiplexing, known as de-multiplexing, pertains to the process of
feeding several independent loads with signals coming from a common signal source, one at a
time. A device used for de-multiplexing is known as de-multiplexer.
Multiplexing and de-multiplexing, therefore, allow the efficient use of common circuits to feed a
common load with signals from several signal sources , and to feed several loads form a single,
common signal source, respectively.
PIN DIAGRAM:
Page 28
PROCEDURE:
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module
and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
If any syntax errors occur they will appear on console window while compiling.
In process window click ISM simulator, now click on behavioral check syntax, simulate
behavioral model.
Select your input & click on force constant. Enter value in force clock to value.
Page 29
If en =1 then
o/p=0
Step 4: END
Page 30
Page 31
Page 32
Page 33
Page 34
VIVA QUESTIONS :
Page 35
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
A comparator is a special combinational circuit designed primarily to compare the relative
magnitudes of two binary numbers. If a comparator receives two n-bit numbers A and B as
inputs and the outputs are A>B, A=B, A<B. Depending upon the relative magnitudes of the two
numbers, one of the outputs will be high.
IC7485 is a bit comparator. It can be used to compare two 4-bit binary words. These ICs, can
cascade to compare words of almost any length.
PIN DIAGRAM:
Page 36
PROCEDURE:
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module
and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
If any syntax errors occur they will appear on console window while compiling.
In process window click ISM simulator, now click on behavioral check syntax, simulate
behavioral model.
Select your input & click on force constant. Enter value in force clock to value.
ALGORITHM:
Page 37
Define ports with agtbin, aeqbin, altbin,a,b as i/ps and agtbout ,aeqbout altbout as o/ps
Step 3: Declare the architecture as
If a=b then aeqbout=1 else
If a<b then agtbout=1 else
If a>b then altbout=1 else
Step 4: End
Page 38
Page 39
OUTPUT WAVEFORM:
RESULT:
VIVA QUESTIONS:
Page 40
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
The D-flip flop has only a single data input .The data input is connected to the S input of an RSflip flop, while the inverse of D is connected to the R input. This prevents that the input
combination ever occurs. To allow the flip flop to be in a holding state, a D-flip flop has a
second input called Enable. The Enable-input is AND with the D-input, such that when
Enable=0, the R & S of the RS-flip flop are 0 and the state is held. When the Enable-input is 1,
the S input of the RS flip flop equals the D input and R is the inverse of D determines the value
of the output Q when Enable is 1. When Enable returns to 0, the most recent input D is
remembered.
PROCEDURE:
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module
and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
If any syntax errors occur they will appear on console window while compiling.
Page 41
In process window click ISM simulator, now click on behavioral check syntax, simulate
behavioral model.
Select your input & click on force constant. Enter value in force clock to value.
Page 42
Page 43
VIVA QUESTIONS:
Page 44
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the
clock input of the next. The J and K inputs of each flip flop are set to 1 to produce a toggle at
each cycle of the clock input. For each two toggles of the first cell, a toggle is produced in the
second cell, and so on down to the fourth cell. This produces a binary number equal to the
number of cycles of the input clock signal. This device is sometimes called a ripple through
counter. The same device is useful as a frequency divider, a BCD counter or decade counter can
be constructed from a straight binary counter by terminating the ripple through counting when
the count reaches decimal 9(binary 1001). Since the next toggle would set the two most
significant bit, a NAND gate tied from those two outputs to the asynchronous clear line will start
the count over after 9. A frequency divider can be constructed from J-K flip flops by taking the
output of one cell to the clock input of the next. The J and K inputs of each flip flop are set to 1
to produce a toggle at each cycle of the clock input. For each two toggles of the first cell, a
toggle is produced in second cell, so its output is at half the frequency of the first. The output of
the fourth cell is 1/16 the clock frequency. The same device is useful as a binary counter.
Page 45
PIN DIAGRAM:
\
PROCEDURE:
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module
and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
If any syntax errors occur they will appear on console window while compiling.
In process window click ISM simulator, now click on behavioral check syntax, simulate
behavioral model.
Select your input & click on force constant. Enter value in force clock to value.
Page 46
ALGORITHM:
Step 1: Use the libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED
Step 2: Declare the entities
Define ports with clk, en as i/ps and count out as o/ps
Step 3: Declare the architecture as
Declare a temporary count initializing with 0
If en=1 and clk=1 then
Temp count = temp count +1
Count out= temp count
Step 4: END
Page 47
Page 48
VIVA QUESTIONS:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Page 49
AIM:
To design and simulate MOD 16 counter (4-bit) using IC7490 in VHDL behavioral
modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the
clock input of the next. The J and K inputs of each flip flop are set to 1 to produce a toggle at
each cycle of the clock input. For each two toggles of the first cell, a toggle is produced in the
second cell, and so on down to the fourth cell. This produces a binary number equal to the
number of cycles of the input clock signal. This device is sometimes called a ripple through
counter. The same device is useful as a frequency divider, a BCD counter or decade counter can
be constructed from a straight binary counter by terminating the ripple through counting when
the count reaches decimal 9(binary 1001). Since the next toggle would set the two most
significant bit, a NAND gate tied from those two outputs to the asynchronous clear line will start
the count over after 9. A frequency divider can be constructed from J-K flip flops by taking the
output of one cell to the clock input of the next. The J and K inputs of each flip flop are set to 1
to produce a toggle at each cycle of the clock input. For each two toggles of the first cell, a
toggle is produced in second cell, so its output is at half the frequency of the first. The output of
the fourth cell is 1/16 the clock frequency. The same device is useful as a binary counter.
Page 50
PIN DIAGRAM:
PROCEDURE:
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module
and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
If any syntax errors occur they will appear on console window while compiling.]\
In process window click ISM simulator, now click on behavioral check syntax, simulate
behavioral model.
Select your input & click on force constant. Enter value in force clock to value.
Page 51
ALGORITHM:
Step 1: Use the libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED
Step 2: Declare the entities
Define ports with clk, dir as i/ps and count out as o/ps
Step 3: Declare the architecture as
Declare a temporary count initializing with 0
If clk=1 and dir =1
Temp count=tempcnt+1
Count out = Temp count
If clk=1 and dir =0
Temp count=tempcnt-1
Count out = Temp count
Step 4:- END
Page 52
Page 53
VIVA QUESTIONS:
Page 54
AIM:
To design and simulate the right shift and parallel shift register using IC 74x95 using
VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
These 4-bit Registers feature parallel and serial inputs parallel outputs mode control and
two clock inputs. The registers have 2 modes of operation parallel load& shift right. Parallel
loading is accomplished by applying the four bits of data and taking the mode control input high.
The data is loaded into the associated Flip flops and appears at the outputs after the high-to-low
transition of the clock-2 input. During loading the entry of serial data is inhibited. Shift right is
accomplished on the high to low transition of clock 1 when the mode control is high by
connecting the output of each flip-flop to the parallel input of the previous Flip flop and serial
data is entered at input D. the clock input may be applied simultaneously to clock 1 and clock 2
if both modes can be clocked from the same source changes at the mode control input should
normally be made while both clock inputs are low however conditions described in the last three
lines of the truth table will also ensure that Register contents are protected DM7495s datasheet
is the same as DM7495
PIN DIAGRAM:
Page 55
PROCEDURE:
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module
and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
If any syntax errors occur they will appear on console window while compiling.
In process window click ISM simulator, now click on behavioral check syntax, simulate
behavioral model.
Select your input & click on force constant. Enter value in force clock to value.
ALGORITHM:
Step 1: Use the libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED
Step 2: Declare the entities
Page 56
Page 57
Page 58
VIVA QUESTIONS:
Page 59
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
These 4-bit Registers feature parallel and serial inputs parallel outputs mode control and two
clock inputs. The registers have 3 modes of operation parallel load, shift right and shift left.
Parallel loading is accomplished by applying the four bits of data and taking the mode control
input high. The data is loaded into the associated Flip flops and appears at the outputs after the
high-to-low transition of the clock-2 input. During loading the entry of serial data is inhibited.
Shift right is accomplished on the high to low transition of clock 1 when the mode control is low
shift left is accomplished on the high to low transition of clock 2 when the mode control is high
by connecting the output of each flip-flop to the parallel input of the previous Flip flop and serial
data is entered at input D. the clock input may be applied simultaneously to clock 1 and clock 2
if both modes can be clocked from the same source changes at the mode control input should
normally be made while both clock inputs are low however conditions described in the last three
lines of the truth table will also ensure that Register contents are protected DM7495s datasheet
is the same as DM7495.
Page 60
PIN DIAGRAM:
PROCEDURE:
Enter your project name and project setting select automotive Spartan 3E in family.
Go to project, click on new source. A new source wizard will open. Select VHDL module
and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
If any syntax errors occur they will appear on console window while compiling.
In process window click ISM simulator, now click on behavioral check syntax, simulate
behavioral model.
Select your input & click on force constant. Enter value in force clock to value.
Page 61
ALGORITHM:
Step 1: Use the libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED
Step 2: Declare the entities
Define ports with clk, d ,s as i/ps and q as o/ps
Step 3: Declare Architecture
If clk =1 then
When s= 00 then q<=d else
When s= 00 then q<=data rigt shift else
When s= 00 then q<=data left shift else
When s= 00 then q<=parallel load
Step 4: END
Page 62
Page 63
VIVA QUESTIONS:
1. What is shift register.
2. What is the difference between universal shift register and shift register
3. Write the structural programming of universal shift register.
Page 64
En_1
RW
Operation
Write
Page 65
Inhibit
ALGORITHM:
Step 1: Use the libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED
Step 2: Declare the entities
Define ports with en, rd ,wr,d as i/ps and q as o/ps
Step 3: Declare Architecture
If en=1 and rd =1
Then data will read from memory else
o/p is zzzz
If en=1 and wr =1
Then data will write into memory else
o/p is zzzz
Step 4: END
Page 66
OUTUT WAVEFORMS:
RESULT:
VIVA QUESTIONS:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Write the behavioral code for IC 74x189 without declaring the function.
Explain about different types of RAMs?
How to specify the memory size?
Explain read and write operations?
What are the differences between RAM and RAM?
Explain the steps of a compilation process of a VHDL program?
Why configurations are needed?
What is binding?
What is subprogram in vhdl
Page 67
Page 68
Step 4: END
MODEL WAVEFORM OF STACK OPERATION:
Page 69
Write the behavioral code for IC 74x189 without declaring the function.
Explain about different types of RAMs?
How to specify the memory size?
Explain read and write operations?
What are the differences between RAM and RAM?
Explain the steps of a compilation process of a VHDL program?
Why configurations are needed?
What is binding?
What is subprogram in vhdl
Page 70
AIM:
To design and simulate 4 bit ALU operation using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
Arithmetic and logic unit (ALU) is a digital circuit that performs integer arithmetic and
logical operations. The ALU is a fundamental building block of the central processing unit of a
computer, and even the simplest microprocessors contain one for purposes such as maintaining
timers. The processors found inside modern CPUs and graphics processing units (GPUs)
accommodate very powerful and very complex ALUs; a single component may contain a
number of ALUs.
PIN DIAGRAM:
Page 71
PROCEDURE:
Enter your project name and project setting select automotive Spartan 3E in
family.
Go to project, click on new source. A new source wizard will open. Select VHDL
module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
If any syntax errors occur they will appear on console window while compiling.
In process window click ISM simulator, now click on behavioral check syntax,
simulate behavioral model.
Select your input & click on force constant. Enter value in force clock to value.
Page 72
ALGORITHM:
Step 1: Use the libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED
Step 2: Declare the entities
Define ports with clk, d,w,r as i/ps and f as o/ps
Step 3: Declare Architecture
For different selection lines of d differner arthamatic and logical operations has been
occurred between the w and r and the output is saved in f;
Step 4:-END
Page 73
Page 74
VIVA QUESTIONS:
Page 75
ADD-ON EXPERIMENTS
13. HALF ADDER AND FULL ADDER
AIM:
To design and simulate the Half Adder, Full Adder using VHDL behavioral modeling.
SOFTWARE REQUIRED:
THEORY:
HALF ADDER:
The half adder is an example of a simple, functional digital circuit built from two logic gates.
The half adder adds to one-bit binary numbers (AB). The output is the sum of the two bits (S)
and the carry (C). Note how the same two inputs are directed to two different gates. The inputs
to the XOR gate are also the inputs to the AND gate. The input "wires" to the XOR gate are tied
to the input wires of the AND gate; thus, when voltage is applied to the A input of the XOR gate,
the A input to the AND gate receives the same voltage.
FULL ADDER:
The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit binary
numbers, a sum (S) and a carry (C1). The full-adder is usually a component in a cascade of
adders, which add 8, 16, 32, etc. binary numbers. The carry input for the full-adder circuit is
from the carry output from the circuit "above" itself in the cascade. The carry output from the
full adder is fed to another full adder "below" itself in the cascade. If you look closely, you'll see
the full adder is simply two half adders joined by an OR.
Page 76
PROCEDURE:
Enter your project name and project setting select automotive Spartan 3E in
family.
Go to project, click on new source. A new source wizard will open. Select VHDL
module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
If any syntax errors occur they will appear on console window while compiling.
In process window click ISM simulator, now click on behavioral check syntax,
simulate behavioral model.
Select your input & click on force constant. Enter value in force clock to value.
ALGORITHM:
Step 1: Use the libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED
Step 2: Declare the entities
Page 77
OUTPUT WAVEFORMS:
Page 78
ALGORITHM:
Step 1: Use the libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED
Step 2: Declare the entities
Define ports with a,b Cin as i/ps and Cout , Sum as o/ps
Step 3: Declare Architecture
Sum as a sum with xor operation of a ,b,Cin . carry with AND operation of a and b
Cin.
Step 4:-END
RTL SCHEMATIC:
Page 79
Page 80
OUTPUT WAVEFORMS:
RESULT:
VIVA QUESTIONS:
1. Write the truth table of half adder and full adder and explain.
2. What is the difference between half adder and full adder.
3. Write the program code in structural.
Page 81
14. 8 x 3 ENCODER
AIM: To design and simulate 8 x 3 Encoder using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
An Encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has
2n (or fewer ) input lines and output lines. In encoder the output lines generate the binary code
corresponding to the input value. The figure shows the general structure of the encoder circuit.
As Shown in the figure the decoded information is presented as 2n inputs producing n possible
outputs.
A Priority Encoder is a encoder Circuit that includes the priority Function. In Priority
encoder , if two or more inputs are equal to 1 at the same time, the input having the highest
Priority will take precedence.
Page 82
Truth Table
Inputs
Outputs
D7
D6
D5
D4
D3
D2
D1
D0
PROCEDURE:
Enter your project name and project setting select automotive Spartan 3E in
family.
Go to project, click on new source. A new source wizard will open. Select VHDL
module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
If any syntax errors occur they will appear on console window while compiling.
Page 83
In process window click ISM simulator, now click on behavioral check syntax,
simulate behavioral model.
Select your input & click on force constant. Enter value in force clock to value.
ALGORITHM:
Page 84
RTL SCHEMATIC:
Page 85
Page 86
OUTPUT WAVEFORMS:
RESULT:.
VIVA QUESTIONS:
1. Write the VHDL code for the encoder using CASE statement.
2. Write the VHDL code for the encoder using WITH statement.
3. Write the VHDL code for the encoder WHEN--ELSE statement.
4. Write the structural program for encoder.
5. What does priority encoder mean?
6. How many encoders are needed to construct 16X4 encoder ?
7. What is the difference between decoder and encoder?
Page 87
AIM:
To design and simulate T- Flip Flops IC 7474 using VHDL behavioral modeling.
SOFTWARE REQUIRED:
Xilinx ISE Simulator V 12.1
THEORY:
If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is
strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described by
the characteristic equation:
(or, without benefit of the XOR operator, the
equivalent:
Excitation table
Comment
Comment
0 0
No change
0 1
No change
1 0
toggle
1 Complement
1 1
toggle
1 Complement
When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock
frequency is 4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This
Page 88
'divide by' feature has application in various types of digital counters. A T flip-flop can also
be built using a JK flip-flop (J & K pins are connected together and act as T) or D flip-flop
(T input and Qprevious is connected to the D input through an XOR gate).
PROCEDURE:
Enter your project name and project setting select automotive Spartan 3E in
family.
Go to project, click on new source. A new source wizard will open. Select VHDL
module and enter your file name. But do not give keywords as file name.
Now define module will be opened. Fill input, output details in port.
If any syntax errors occur they will appear on console window while compiling.
In process window click ISM simulator, now click on behavioral check syntax,
simulate behavioral model.
Select your input & click on force constant. Enter value in force clock to value.
Page 89
Page 90
Page 91
RESULT:
VIVA QUESTIONS:
Page 92