MAHAVEER INSTITUTE OF SCIENCE AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

IV B.TECH

I-SEM I-MID EXAMINATIONS

ECE- C

SUBJECT: VLSI DESIGN

MAX MARKS: 10 M TIMES: 1 hr
Answer any 2 out of 4 Questions, each Question carries 5 Marks.

SET-A DATE OF EXAM:

1. Implement and explain the working principles of a ripple carry adder using
transmission gates.
2. (a) Draw and explain the Read/Write operation of 4T SRAM cell.
(b) Explain the principle of DRAM cell
3. Explain the operation of FPGA and write the applications of FPGA.
4. Write short notes on
(1)DFT (2) BIST (3) boundary scan testing
MAHAVEER INSTITUTE OF SCIENCE AND TECHNOLOGY
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
IV B.TECH

I-SEM I-MID EXAMINATIONS

ECE- C

SUBJECT: VLSI DESIGN

MAX MARKS: 10 M TIME: 1 hr
Answer any 2 out of 4 Questions, each Question carries 5 Marks.

SET-B

DATE OF EXAM:

1. With the help of block diagram explain the operation of standard cells.
2. (a) Explain the terms controllability observability and fault coverage
(b) What is a fault simulation?
3. Design and explain row &column decoder for NAND ROM array
4. Design and implement a tree based zero/one detector circuit.

MAHAVEER INSTITUTE OF SCIENCE AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
IV B.TECH

I-SEM I-MID EXAMINATIONS

ECE- C

SUBJECT: VLSI DESIGN

MAX MARKS: 10 M TIME: 1 hr SET-C DATE OF EXAM:
Answer any 2 out of 4 Questions, each Question carries 5 Marks.
1(a) Draw the circuit for 6 transistor SRAM &explain its working.
(b) Write the advantage of 4T SRAM cell over 6T SRAM
2. Explain antifuse based FPGA. Mention different advantages of antifuse technology.
3. Design and explain 4bit synchronous and asynchronous counter using transmission
gates
explain its working.
4. What are the issues to be considered while implementing BIST? Explain