Professional Documents
Culture Documents
DL - Manual - 16-17
DL - Manual - 16-17
DL - Manual - 16-17
Group A
Combinational Logic Design
1. Design (truth table, K-map) and implementation of 4-bit BCD to Excess-3 and Excess-3 to BCD
Code converters.
2. Design (truth table, K-map) and implementation of 4 bit BCD & Excess 3 Adder using
IC7483.
3. Implementation of logic functions using multiplexer IC 74153 & decoder IC 74138.
(Verification, cascading & logic function implementation)
Group B
Sequential Logic Design
1. Design (State diagram, state table & K map) and implementation of 3 bit Up and Down
Asynchronous and Synchronous Counter using master slave JK flip-flop IC 7476
2. Design and implementation of Module n counter with IC7490 and IC 74191.
3. Design (State Diagram, State Table, K Map) and implementation of Sequence Generator using Shift
Register IC 74194.
Group C
VHDL Programming
Simulation of
1. 4:1 multiplexer using data flow & structural modeling.
2. Full adder using behavioral & structural modeling.
3. 3 bit controlled up / down synchronous counter with preset & clear
Reference Books
1. "Modern Digital Electronics", R.P. Jain, 3rd Edition,Tata McGraw-Hill, ISBN: 0-07-049492-4
2. "Fundamentals of Digital Logic with VHDL Design", Stephen Brown, Zvonko Vranesic
McGraw-Hill, ISBN: 978-0-07-352953-0
3. "Digital Logic applications and Design", John Yarbrough, Thomson PublicationISBN: 978-03
1. Code Converter
ii)
ICs Used:
IC 7404(Hex INV), 7432 (OR-gate), 7408 (AND-gate), 7486 (Ex-or gate)
Theory:
There is a wide variety of binary codes used in digital systems. Some of these codes are binarycoded -decimal (BCD), Excess-3, Gray, octal, hexadecimal, etc. Often it is required to convert
from one code to another. For example the input to a digital system may be in natural BCD and
output may be 7-segment LEDs. The digital system used may be capable of processing the data
in straight binary format. Therefore, the data has to be converted from one type of code to
another type for different purpose. The various code converters can be designed using gates.
1) Binary Code:
It is straight binary code. The binary number system (with base 2) represents values using two
symbols, typically 0 and 1.Computers call these bits as either off (0) or on (1). The binary code
are made up of only zeros and ones, and used in computers to stand for letters and digits. It is
used to represent numbers using natural or straight binary form.
It is a weighted code since a weight is assigned to every position. Various arithmetic operations
can be performed in this form. Binary code is weighted and sequential code.
2. Code Converter
2) Gray Code:
Digital Laboratory
NBNSSOE1
/ 88
It is a modified binary code in which a decimal number is represented in binary form in such a
way that each Gray- Code number differs from the preceding and the succeeding number by a
single bit. (E.g. for decimal number 5 the equivalent Gray code is 0111 and for 6 it is 0101.
These two codes differ by only one bit position i. e. third from the left.) Whereas by using
binary code there is a possibility of change of all bits if we move from one number to other in
sequence (e.g. binary code for 7 is 0111 and for 8 it is 1000). Therefore it is more useful to use
Gray code in some applications than binary code.
The Gray code is a nonweighted code i.e. there are no specific weights assigned to the bit
positions. Like binary numbers, the Gray code can have any no. of bits. It is also known as
reflected code.
Applications:
1. Important feature of Gray code is it exhibits only a single bit change from one code word to
the next in sequence. This property is important in many applications such as Shaft encoders
where error susceptibility increases with number of bit changes between adjacent numbers in
sequence.
2. It is sometimes convenient to use the Gray code to represent the digital data converted from
the analog data (Outputs of ADC).
3. Gray codes are used in angle-measuring devices in preference to straight forward binary
encoding.
4. Gray codes are widely used in K-map
The disadvantage of Gray code is that it is not good for arithmetic operation
2. Code Converter
Digital Laboratory
NBNSSOE2
/ 88
considerably in performing subtraction operation in digital systems, so this code is used for
certain arithmetic operations.
BCD To Excess 3 Code Conversion:
Convert BCD 2 i. e. 0010 to Excess 3 code
For converting 4 bit BCD code to Excess 3, add 0011 i. e. decimal 3 to the respective code
using rules of binary addition.
0010 + 0011 = 0101 Excess 3 code for BCD 2
Excess 3 Code To BCD Conversion:
The 4 bit Excess-3 coded digit can be converted into BCD code by subtracting decimal value 3
i.e. 0011 from 4 bit Excess-3 digit.
e.g. Convert 4-bit Excess-3 value 0101 to equivalent BCD code.
0101-0011= 0010- BCD for 2
2. Code Converter
Digital Laboratory
NBNSSOE3
/ 88
XOR
7486
2. Code Converter
B3
B2
B1
B0
E3
E2
E1
E0
2. Code Converter
Digital Laboratory
NBNSSOE4
/ 88
Fig. 8 K-Map For Reduced Boolean Expressions Of Each Output (Excess-3 Code)
Digital Laboratory
NBNSSOE5
/ 88
2. Code Converter
3) Circuit Diagram:
BCD TO EXCESS-3 CONVERTER
Digital Laboratory
NBNSSOE6
/ 88
2. Code Converter
GATE
Quantity
IC
Quantity
XOR
7486
NOT
7404
AND
7408
OR
7432
Digital Laboratory
NBNSSOE7
/ 88
2. Code Converter
E3
E2
E1
E0
B3
B2
B1
B0
Digital Laboratory
NBNSSOE8
/ 88
2. Code Converter
Fig 10 K-Map For Reduced Boolean Expressions Of Each Output (BCD Code)
Digital Laboratory
NBNSSOE9
/ 88
2. Code Converter
3) Circuit Diagram:
EXCESS-3 TO BCD CONVERTER
Digital Laboratory
NBNSSOE10
/ 88
2. Code Converter
GATE
Quantity
IC
Quantity
XOR
7486
NOT
7404
AND
7408
OR
7432
Digital Laboratory
NBNSSOE11 /
88
2. Code Converter
Digital Laboratory
NBNSSOE12
/ 88
2. Code Converter
weight to each digit position i.e. each digit position within the number is not assigned a fixed
value. Gray code, Excess-3 code are non-weighted code.
Q.6) Why is Excess-3 code called as self-complementing code?
Excess-3 code is called self-complementing code because 9s complement of a coded number
can be obtained by just complementing each bit.
Q.7) What is invalid BCD?
With four bits, sixteen numbers (0000 to 1111) can be represented, but in BCD code only 10 of
these are used as decimal numbers have only 10 digits fro 0 to 9. The six code combinations
(1010 to 1111) are not used and are invalid.
Digital Laboratory
NBNSSOE13
/ 88
AIM : To design & implement of single digit BCD & Excess adder using IC 7483.
OBJECTIVE: 1. To study the BCD arithmetic rules.
2. Comparison between binary and BCD codes.
ICs USED:
IC 7483 (4 bit Binary adder), IC 7404(Hex INV), 7432 (OR-gate), 7408 (AND-gate), 7486
(EX-OR gate)
THEORY:
BCD Adder:
BCD adder is a circuit that adds two BCD digits & produces a sum of digits also in
BCD.
Rules for BCD addition:
1. Add two numbers using rules of Binary addition.
2. If the 4 bit sum is greater than 9 or if carry is generated then the sum is invalid. To
correct the sum add 0110 i. e. (6)10 to sum. If carry is generated from this addition add it
to next higher order BCD digit.
3. If the 4 bit sum is less than 9 or equal to 9 then sum is in proper form.
CASE I : Sum <= 9 & carry = 0.
Add BCD digits 3 & 4
1.
0011
+
0100
--------0111
0110
+
0101
----------10 1 1
Digital Laboratory
NBNSSOE14
/ 88
1011
+0 1 1 0
-----------
(1
0001
1)BCD
1.
1001
+ 1001
-----------
10010
Invalid BCD ( since Carry = 1 ) so 0110 is to be added
2.
1 0010
+ 0110
-----------11000
(1
8)BCD
Valid BCD result = (18) BCD
Digital Laboratory
NBNSSOE15
/ 88
Digital Laboratory
NBNSSOE16
/ 88
i ) Truth Table for design of combinational circuit for BCD adder to check invalid
BCD :
INPUT
OUTPUT
S3
S2
S1
S0
Digital Laboratory
NBNSSOE17
/ 88
S3S2
S1S0
00
01
11
10
00
01
11
10
1
Y = S3S2 + S3S1
Digital Laboratory
NBNSSOE18
/ 88
Digital Laboratory
NBNSSOE19
/ 88
v)Hardware Requirements :
GATE
Quantity
IC
Quantity
Binary adder
7483
AND
7408
OR
7432
ii.
iii.
NBNSSOE20
/ 88
(i)Design:
1) 4 bit Binary addition of excess 3 codes of two operands can be implemented with IC 7483
2) We have to design the circuit which will either add 0011 or subtract 0011 i.e. add 1101 (2s
complement of 0011) depending upon carry bit.
Lets compare 0011 and 1101.
B3
B2
B1
B0
B2=B3=0
B2=B3=1
B1 bit follows the carry and B2 and B3 bit complements the carry.
(ii) Circuit Diagram:
Digital Laboratory
NBNSSOE21
/ 88
Sl No.
IC
Description
Quanti
ty
7404
Not Gate
01
7483
4 bit Binary
Adder
04
OBSERVATION :
BCD adder :
INPUT
OUTPUT
1st Operand
A3
(MSB)
A2
A1
2nd Operand
A0
(LSB
)
B3
(MS
B)
B2
B1
MSD
B0
(LSB
)
Cout
LSD
S3
(MS
B)
S
2
S
1
S0
(LSB
)
Excess 3 Adder :
INPUT
1st Operand
A3
(MSB)
A2
A1
OUTPUT
2nd Operand
A0
(LSB)
B3
(MSB)
Digital Laboratory
B2
B1
MSD
B0
(LS
B)
S7
(MSB)
S6
LSD
S5
S4
(LSB
)
S3
(MSB)
NBNSSOE22
/ 88
S2
S1
S0
(LSB)
CONCLUSION :
BCD adder & subtractor is designed & tested for all possible combinations.
FAQs:
1. Explain and Write the significance of. BCD number system
2. Write the applications of BCD & Excess 3 code.
3. Explain the rules of BCD & Excess 3 arithmetic.
4. What is the difference between BCD and binary codes?
5. What do you mean by unpacked and packed BCD nos.?
PRACTISE ASSIGNMENTS / EXERCISE / MODIFICATIONS:
1. Design & implement two digit BCD adder using IC 7483.
2. Design & implement single digit BCD subtractor using 10s complement method.
3. Design & implement 9s complementer.
Digital Laboratory
NBNSSOE23
/ 88
3. Study of Multiplexer
ASSSIGNMENT : 3
AIM: Part A MUX IC 74153
1) Verification of IC.
2) Implementation of 8:1 Mux by cascading 2, 4:1 mux in IC 74153
3) Boolean function implementation
Part B Decoder IC 74138
1) Verification of IC.
2) Boolean function implementation.
OBJECTIVE:
1. To study the difference between multiplexer, demultiplexer and decoder.
2. To study the applications of multiplexer.
ICs USED :
IC 74153, 74138, 7404, 7432.
THEORY :
Digital Multiplexer:
Multiplexer are combinational digital circuits equating as controlled switches
with several data inputs (I0, I1, I2 ) & one single data output (out).At any time one of the I/p
is transmitted to output. According to binary signals applied on control pairs to circuit. Usually
the number of data inputs is a power of two.
transmitting a large no. of information units over a small no. of channel / digital multiplexer is a
combinational large circuit which performs the operation of multiplexing .It selects the
operation of multiplexing. It selects the operation of binary information from one of the many
input lines & transfer to a single o/p line. Multiplexer is called a data selector or multiposition
switch because it selects one of the many input. Selection of a particular line is controlled by a
set of a selection lines or selects inputs. The number of select lines depends upon no. of input
lines.
particular code on select lines is transmitted on the output lines.Block diagram of MUX is
shown. at contains 2m input lines m select & one unable input which is used to activate or
Digital Laboratory
NBNSSOE24
/ 88
4. Study of Multiplexer
dedicate MUX .Depending upon the no. of I/P & O/P lines various types of multiplexers are
available. We have 2:1, 4:1, 8:1, 16:1 MUX. Here the first no. indicates the no. of input lines &
second no. indicates the no. of output lines.
Demultiplexer :
Demultiplexer is a logic used to perform exactly reverse function performed by
multiplexer. It accepts a single input and distributes among several outputs. The selection of a
particular output line is controlled by a set of selection line. There are n input lines & 2 m is the
number of selection line whose bit combinations determine which output to be selected.
Difference between Multiplexer, Demultiplexer & Decoder
Point
Input
Multiplexer
Many input lines
Demultiplexer
Single input line
Decoder
Many input line also Acts as
Output
select line
Many output line, Active
Select
2 =n
n=2
Encoder
&
low output
Enable inputs used
line
Decoder :
1. Encoders are used to encode given digital number into different numbering format
.like decimal to BCD Encoder, Octal to Binary.
2. Decoders are used to decode a coded binary word like BCD to seven segment
decoder.
3. Thus encoder and decoder are application specific logic develop, we can not use
any type of input for any encoder and decoder.
4. Need to select input according to encoder and decoder being selected for a
particular application as mention in examples above.
Uses of Mux. :
1) Use for Boolean function implementation.
4. Study of Multiplexer
Digital Laboratory
NBNSSOE25
/ 88
4. Study of Multiplexer
Digital Laboratory
NBNSSOE26
/ 88
Inputs (I or II)
Output
S1
S0
E (I or II)
D0
D1
D2
D3
2.CASCADING OF IC 74153:
Cascading is done to expand two or more MUX ICs to a digital multiplexer with larger no. of
inputs i.e. multiplexer stocks or tress is designed. The enable input is used for cascading. In case
of IC 74153 we have only two select lines. But for certain application 3 select lines are
required then it can be obtained by cascading using enable. Now with 3 select lines we have
8 combinations. Out of this combination the MSB is O. MSB is 1 for last four combination
so we can use these MSB to select any 1 MUX out of two by connecting it to E pin of first
4:1 MUX .
4. Study of Multiplexer
Digital Laboratory
NBNSSOE27
/ 88
Logic Diagram
Y
Output
Selec
t
Output
C (1G / 2G )
B (S1)
A (S0)
D0
D1
D2
D3
D4
D5
D6
D7
3.FUNCTION IMPLEMENTATION:
Y= m (1, 3, 5, 6)
Thisexpression is in Standard SOP form and it is three variable function. So, we need to use
mux with three select inputs i.e. 8:1 Mux. Already we have implemented 8:1 Mux using IC
74153. For Boolean function in Standard SOP form we connect data inputs
4. Study of Multiplexer
Digital Laboratory
NBNSSOE28
/ 88
corresponding to the minterms present in the given function to Vcc and remaining data inputs to
ground.
Truth table :
Inputs
C
Outpu
t
Y
0
1
LOGIC DIAGRAM :
Y
Outpu
Input
s
Digital Laboratory
NBNSSOE29
/ 88
4. Study of Multiplexer
Hardware Requirements :
GATE
Quantity
IC
Quantity
Mux.
74153
NOT
7404
OR
7432
Output
Sum
Carry
Digital Laboratory
NBNSSOE30
/ 88
D0
D1
D2
D3
i/p to MUX
D0
D1
D2
D3
i/p to MUX
4. Study of Multiplexer
Digital Laboratory
NBNSSOE31
/ 88
Hardware Requirements :
GATE
Quantity
IC
Quantity
Mux.
74153
NOT
7404
Digital Laboratory
NBNSSOE32
/ 88
A) Verification of IC 74138:
We use IC 74138 which accepts 3 binary weighted inputs (A0, A1, A2) and when enabled
provides mutually exclusive active low outputs (y0-y7). It features 3 Enable i/ps. Two active
low (G2A, G2B) and one active high (G1). Every output will be high unless G2A, G2Bare low
and G1 is high. It has demultiplexing capability and multiple enable i/ps for easy expansion.
Function Table of 3:8 decoder:
Input
Enable
Output
Data
G2A
G2B
G1
A2
A1
A0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
B) Cascading of IC 74138:
The enable i/p G1 active high of IC 74138 is used for cascading.for cascading 2 ICs ,the enable
i/p G1 of first IC is connected to G1 enable i/p of second IC through a NOT gate. This enable
i/p is used as MSB select i/p line A3. the other three select input lines of both ICs (A0,A1,A2)
are also shorted to select input lines of second IC to get single i/p select lines (A0,A1,A2).
The i/p line A3 is used to enable /disable the 2 IC 74138 decoders. When A3=0, first IC is
enabled and second is disabled. Thus the first decoder will generate minterms from 0000 to
0111 as o/p and the second decoder will generate nothing. When A3=1, the enable conditions
are reversed and thus second decoder IC will generate minterms 1000 to 1111.
Function Table of 4:16 decoder using IC 74138 (3:8 decoder):
Digital Laboratory
NBNSSOE33
/ 88
Input
Enable
G2
A
G2
B
Output
Data
A
3
A
2
A
1
A
0
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
Y1
0
Y11
Y1
2
Y1
3
Y1
4
Y15
Digital Laboratory
NBNSSOE34
/ 88
Digital Laboratory
NBNSSOE35
/ 88
Conclusion : In this way multiplexer & its applications are studied , implemented &
tested.
FAQs:
1.What is a multiplexer?
2.What is a Demultiplexer?
3. Enlist applications of multiplexer.
4. Define the terms Encoder and Decoder.
5. What is the difference between multiplexer & demultiplexer?
6. What is the difference between decoder & demultiplexer?
Digital Laboratory
NBNSSOE36
/ 88
AIM:To design and implement 3 bit UP, Down, Controlled UP / Down Ripple
Counter using MS-JK Flip-flop.
NBNSSOE37
/ 88
Flip-flop 0(Q0) is connected to clock of next flip-flop (i.e Flip-flop 1) and so on. As soon as
clock pulse changes output is going to change (at the negative edge of clock pulse) as a Up
count sequence. For 4 bit Up counter state table is as shown below.
State Table :
Counter States
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Q3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Count
Q2 Q1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Q0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Logic diagram :
Digital Laboratory
NBNSSOE38
/ 88
Quantity
MS JK
IC
Quantity
7476
2) Down Counter:
Fig. 2 shows 4 bit Asynchronous Down Counter. Here Flip-flop 3 act as a MSB Flip-flop and
Flip-flop 0 act as a LSB Flip-flop. Clock pulse is connected to the Clock of Flip-flop 0. Output
of Flip-flop 0 (Q0) is connected to clock of next flip-flop (i.e Flip-flop 1) and so on. As soon as
clock pulse changes output is going to change (at the negative edge of clock pulse) as a down
count sequence. For 3 bit down counter sate table is as shown below.
In both the counters Inputs J and K are connected to Vcc, hence J-K Flip flop work in toggle
mode. Preset and Clear both are connected to logic 1.
Digital Laboratory
NBNSSOE39
/ 88
Counter States
State Table :
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Q3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Count
Q2 Q1
1
1
1
1
1
0
1
0
0
1
0
1
0
0
0
0
1
1
1
1
1
0
1
0
0
1
0
1
0
0
0
0
Q0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Logic diagram :
NBNSSOE40
/ 88
5. Ripple Counter
Hardware requirements :
Gate /
Flip flop
Quantity
MS JK
IC
Quantity
7476
To design and implement 3 bit UP, Down Synchronous Counter using MS-JK Flip-flop.
ICs USED: Digital Trainer Kit, IC 7476 (MS-JK Flip-flop), IC 7408 (Quad 2 i/p AND
Gate), IC 7432 (Quad 2 i/p OR Gate) and IC 7404 (Hex Inverter).
THEORY:
Counters : counters are logical device or registers capable of counting the no. of states or no.
of clock pulses arriving at its clock input where clock is a timing parameter arriving at
regular intervals of time, so counters can be also used to measure time & frequencies. They are
made up of flip flops. Where the pulse are counted to be made of it goes up step by step & the
o/p of counter in the flip flop is decoded to read the count to its starting step after counting n
pulse incase of module counters.
Types of Counters:
Counter are of two types:
1) Synchronous counter.
2) Asynchronous counter.
1) Synchronous Counter :
Digital Laboratory
NBNSSOE41
/ 88
When counter is clocked such that each flip flop in the counter is
triggered
at
the
same
time,
the
counter
is
called
as
synchronous
counter.
The gates propagation delay at reset time will not be present or we may say will not occur.
Types of synchronous counter:
1) Up counter.
2) Down counter.
3) Controlled up down counter.
6. Synchronous counter
Present state
Q2
Next state
Flip flop 3
K2
J1
K1
flip flop 1
Q1
Q0
Q2
Q2
Q0
Digital Laboratory
J2
Flip flop 2
NBNSSOE42
J0
/ 88
K0
K-Map :
Q1Q0
0
0
01
11
10
Q2
J2= Q1Q0
6. Synchronous counter
Q1Q0
0
0
01
11
10
0
0
01
11
10
0
0
01
11
10
Q2
K2= Q1Q0
Q1Q0
Q2
J1= Q0
Q1Q0
Q2
K1= Q0
Digital Laboratory
NBNSSOE43
/ 88
Q1Q0
0
0
01
11
10
Q2
J0= 1
6. Synchronous counter
Q1Q0
0
0
01
11
10
Q2
K0= 1
Logic Diagram:
Digital Laboratory
NBNSSOE44
/ 88
6. Synchronous counter
Present state
Q2
Q1
Q0
Next state
Q2
Q1
Digital Laboratory
Q0
Flip flop 3
Flip flop 2
Flip flop 1
J2
J1
J0
K2
K1
NBNSSOE45
/ 88
K0
K-Map :
Q1Q0
0
0
01
11
10
Q2
J2= Q1Q0
6. Synchronous counter
Q1Q0
0
0
01
11
10
01
11
10
Q2
K2= Q1Q0
Q1Q0
Q2
Digital Laboratory
0
0
NBNSSOE46
/ 88
0
0
01
11
10
J1= Q0
Q1Q0
Q2
K1= Q0
Q1Q0
0
0
01
11
10
Q2
J0= 1
6. Synchronous counter
Q1Q0
0
0
01
11
10
Q2
K0= 1
Logic Diagram :
Digital Laboratory
NBNSSOE47
/ 88
Quantity
IC
Quantity
MS JK
7476
NOT
7404
OR
7432
AND
7408
Flip flop
Uses:
1. Specially used as the counting devices.
2. Used in frequency divider circuit.
Digital Laboratory
NBNSSOE48
/ 88
AIM:To design and implement mod - 10, mod 7, mod - 99 asynchronous BCD counter using
IC 7490 and to design and implement up, down, mod - n Binary counter using IC 74191.
OBJECTIVE:To know difference between regular & truncated counter as well as binary
&BCD Counter
ICs USED:
THEORY:
Part A IC 7490
IC 7490 is a TTL MSI (medium scale integration) decade counter. It contains 4 master
slave flip flops internally connected to provide MOD-2 i.e. divide by 2 and MOD-5 i.e. divide
by 5 counters. MOD-2 and Mod-5 counters can be used independently or in cascading.
It is a 4-bit ripple type decade counter. The device consists of 4-master slave flip flops
internally connected to provide a divide by two and divide by 5 sections. Each section has a
separate clock i/p to initiate state changes of the counter on the high to low clock transition.
Pin out of IC 7490:
U1
14 INA
1 INB
2 R01
3 R02
6 R91
7 R92
QA
QB
QC
QD
12
9
8
11
7490N
Basic internal Structure of IC 7490:
Digital Laboratory
NBNSSOE49
/ 88
uncti
on Table of MOD-2 counter:
Input A clock
of MOD-5 counter:
InputB clock
Design of MOD-10
Output
Count
Output
QD QC QB Count
counter.
Mod-5
Digital Laboratory
first
flip
flop
is
NBNSSOE50
/ 88
Due
counters,
to
the
overall configuration the decade counters count from 0000 to 1001. After 1001 mod-5 resets to
0000 and next count after 1001 is 0000.
When QA o/p is connected to B i/p, we have the Mod-2 counter followed by Mod-5
counter. The count sequence obtained is shown in the table. It may be noted that QA changes
from 0 to 1 the state of Mod-5 counter doesnt change, whereas when QA changes from 1 to 0
the Mod-5 counter goes to the next state.
Logic DiagramMOD-10 counter using IC 7490:
Function table:
Digital Laboratory
NBNSSOE51
/ 88
I/p clock
Output
Count
QD
QC QB Q
A
CLK
QA
QB
QC
QD
Digital Laboratory
NBNSSOE52
/ 88
QC
QB
QA
Digital Laboratory
NBNSSOE53
/ 88
Function
table:
I/p clock
Output
Count
Digital Laboratory
QD
Q
C
QB QA
NBNSSOE54
/ 88
CLK
QA
A
QB
A
QC
A
7. Modulus n Counter
Pin details
D0 to D3 input lines, PL parallel load
Digital Laboratory
NBNSSOE55
/ 88
7. Modulus n Counter
Digital Laboratory
NBNSSOE56
/ 88
Clk
Pulse
s
QA QB
QC QD
10
11
12
13
14
15
7. Modulus n Counter
Logic Diagram
Digital Laboratory
NBNSSOE57
/ 88
no connection
NC
Clock
14
D3
D2 D1 D0
PL
10 1 15
11
IC 74191
G
U/D
RC
MAX / MIN
UP/Down 5
G 47
NC
13 RC
12Q3 Q2 Q1 Q0
TC
Outputs
Steps
Down
Q3 Q2
Q1
Q0
Digital Laboratory
NBNSSOE58
/ 88
NC
10
11
12
13
14
15
0
no connection
vcc
vcc
U/D
Clk
D3 D2 D1 D0
Clock
G
RC
MAX / MIN
GQ3 Q2 Q1 Q0 TC
PL
IC 74191
NC
NC
Outputs
7. Modulus n Counter
Digital Laboratory
NBNSSOE59
/ 88
Preset Count
CLOCK
D3
U / D74191
D2
D1
D0
TC
RC
GPL
Up/downQ3
Q3
Q2
Q2
Q1
Q1
Q0
Combinational Circuit
Mod 11 counter
Implementation of presetttable mod up/down counter using IC- 74LS191
Counter
Q3 Q2 Q1 Q0
1. Load
Data on data lines D0 to D3 (0101).
state / Clock
2.
Counter will go through the states
from
0101 ,0110,1111 in up counter and
pulse
0101
to 0000 in down counter.
3. The
logic circuit should be designed in
1
0
1
0
1
such
a way that only when all the outputs
2
0
1
1
0
are
high, output of the reset circuit
should be low and the counter
3
0
1
1
1
should jump to state 5. It should
again
start counting from 0101 to 0000,
4
1
0
0
0
State Table
UP Counter
Digital Laboratory 1
10
11
Down
NBNSSOE60
Counter
/ 88
Counter state /
F/F outputs
Q3
Q2
Q1
Q0
Clock pulse
vcc
GND
vcc
NC
High or Low
13
12
11
32
32
32
GND
GND
Digital Laboratory
NBNSSOE61
/ 88
Operation
S1
S0
Clock Inhibit
Shift right
Shift Left
Parallel loading
Function
Table of IC
74194
Design:
The minimum number of flip-flops, N, required to generate a sequence of length S is given by
S 2N 1.
In this case S=7, therefore the minimum value of N, which may generate in this sequence is 3.
However, it is not guaranteed to lead to a solution. If the given sequence leads to seven distinct
states, then only three flip flops are sufficient otherwise we have to increase the number of flip
flops. We write the states of circuit as given in table 1. Table 1. State Assignment Table of
Sequence Generator (N=3)
Number of Clock
Pulses
QA
QB
QC
Digital Laboratory
NBNSSOE62
States
7*
/ 88
7*
5*
5*
Present State Qn
Flip-Flop Input D
Number of Clock
Pulses
States
Serial i/p
QA
QB
QC
QD
14
15
11
10
13
Digital Laboratory
NBNSSOE63
/ 88
8. Sequence Generator
K-Map Simplification:
00
01
11
10
00
01
11
10
Y= QA + QB + QC = QA.QB.QC
LOGIC DIAGRAM:
Sl No.
ICs
Digital Laboratory
Description
Quantity
NBNSSOE64
/ 88
74194
7410
1
1
AIM
OBJECTIVE: - To learn data flow modeling style. Its uses and different types of declarations
with some different types of circuits. Structure of VHDL program is well
discussed with this modeling style.
THEORY :Data flow style:In this type of design, the view of data as flowing from input to output through a design.
An operation is defined in terms of a collection of data transformation expressed as
concurrent statement. Each of the statement can be activated when any of its input signal
changes its value. While these statements describe the behavior of the circuit, a lot of
information about its structure can be extracted from the description as well.
Data flow modeling has a set of concurrent assignment statements. In the data flow level
of abstraction we describe how information is passed in the circuit. The built in operators in
VHDL are used in expression such as AND, OR, XOR, NOT, etc
Digital Laboratory
NBNSSOE65
/ 88
S1
S0
Design steps:
Click on Xilinx ISE 9.2i.
Create New project from file menu. Ensure top level source is HDL.
Select family of devices (usually spartan2E or 3)
Ensure preferred language is VHDL.
Click new source which shows you project details, device details
and Synthesis and simulator tools.
After finishing project create new source by right clicking in project name with
VHDL module.
Complete ports name, directions and bus. Ensure architecture name is behavioral.
After that we will get design summary and detailed reports.
Close design summary.
Create your code with given modeling style.
Go to process window and synthesis to check if any error is there in code. Check
syntax and view RTL schematic.
Create new source to simulate the code.
Right click on source name and create test bench waveform with proper name.
Ensure the project is same.
Click on combinational circuit in initial timing wizard.
Select test bench wave in source window. Apply inputs to wave diagram. Ensure
you are in behavioral simulation.
Go to process box. Click on Xilinx ISE simulator and simulate the model. See
results.
Digital Laboratory
NBNSSOE66
/ 88
RTL Schematic:
Timing Diagram:
Digital Laboratory
NBNSSOE67
/ 88
INPUT:
OUTPUT:
AIM
OBJECTIVE: To learn structural modeling style. Its uses and different types of declarations
with some different types of circuits. Structure of VHDL program is well
modeling style
THEORY :- Structural style:A digital electronic system can be described as a module with inputs and/or outputs. The
electrical values on the outputs are same functions of the values of inputs. The example of it is
as shown. The NAND gate has 2i/ps, A&B, & an output y. Using VHDL terminology, we call
the NAND2 design entity & the inputs & outputs are called ports. 1 way of describing the
function of NAND2 is to describe how it is composed of sub modules AND & INVERTER
Each of the Sub modules is an instance of some entity & ports of the instances are connected
using signals. Structural modeling has a set of interconnected component. Structure can be used
to create a very low level description of a circuit or a very high level description.
Digital Laboratory
NBNSSOE68
/ 88
In a gate level description of a circuit, for example components such as basic logic gates
& F/Fs might be connected in some logical stricture to create the circuit. This is what is often
called a net list.
NBNSSOE69
/ 88
Cin
SUM
CARRY
Sum = m(1, 2, 4, 7)
Carry= m(3, 5, 6, 7)
Digital Laboratory
NBNSSOE70
/ 88
Design steps:
Click on Xilinx ISE 9.2i.
Create New project from file menu. Ensure top level source is HDL.
Select family of devices (usually spartan2E or 3)
Ensure preferred language is VHDL.
Click new source which shows you project details, device details
and Synthesis and simulator tools.
After finishing project create new source(full adder) by right clicking in project
name with VHDL module.
Complete ports name, directions and bus. Ensure architecture name is behavioral.
After that we will get design summary and detailed reports.
Close design summary.
Click new source which shows you project details, device details
and Synthesis and simulator tools.
After finishing project create new source(half adder) by right clicking in project
name with VHDL module.
Complete ports name, directions and bus. Ensure architecture name is behavioral.
Names should be same as previous inputs.
After that we will get design summary and detailed reports.
Close design summary
Create your code for half adder with given modeling style.
After that go to process window. Click on design utilities.
View HDL instantiation code of half adder.
Copy component part of half adder in architecture block of full adder. Copy
instantiation template twice after begin as we require two half adders to construct
full adder (structural modeling). Name them differently (e.g. ha1 or ha2).
Create signals as per the logic. Complete code of full adder.
Go to process window and synthesis to check if any error is there in code. Check
syntax and view RTL schematic.
Create new source to simulate the code.
Right click on source name and create test bench waveform with proper name.
Ensure the project is same.
Click on combinational circuit in initial timing wizard.
Select test bench wave in source window. Apply inputs to wave diagram. Ensure
you are in behavioral simulation.
Go to process box. Click on Xilinx ISE simulator and simulate the model. See
results.
Digital Laboratory
NBNSSOE71
/ 88
RTL Schematic:
Timing Diagram:
Digital Laboratory
NBNSSOE72
/ 88
INPUT:
OUTPUT:
FAQs:
1. What do you mean by structural style?
Ans : in this type of code a circuit is described in hierarchical fashion, by connecting
together sub circuits.
2. Explain IF statement with example.
Ans: The general form of an IF statement is as follws:
IF Sel=0 THEN
F<=x1;
ELSE
Digital Laboratory
NBNSSOE73
/ 88
F<=x2;
END IF;
3. Explain declaration and instantiation process in VHDL.
Ans: first declare a small vhdl code in formal way. E.g. half adder. Define project name is
full adder. And simply copy instantiation template in main source code. Define how many
times you want to declare this template. Give separate names for those.
4. What is STD_LOGIC_VECTOR?
Ans: It is standard data object added to VHDL standard in IEEE 1164. It provides more
flexibility than the Bit type.
5. Explain difference between concurrent and sequential statements?
Ans: Concurrent statements define interconnected processes and blocks that together describe a
designs overall behavior or structure. They can be grouped using block s13.
tatement. Groups of blocks can also be partitioned into other blocks. At this same
level, a VHDL component can be connected to define signals within the blocks.
It is a reference to an entity. A process can be a single signal assignment statement or a
series of sequential statements (SS). Within a process, procedures and functions can
partition the sequential statements
PRACTICE ASSIGNMENTS:
1. Implement half adder using data flow modeling.
2. Implement Full Adder using behavioral modeling.
3. Implement 3 bit magnitude comparator using a 3 bit adder.
4. Implement half sub tractor using data flow modeling.
5. Write VHDL code for Full Subtractor.
Digital Laboratory
NBNSSOE74
/ 88
11. 3bit Controlled up / down synchronous counter with preset & clear.
AIM
OBJECTIVE: To learn behavioral modeling style. Its uses and different types of declarations
with some different types of circuits. Structure of VHDL program is well discussed with this
modeling style
THEORY :tructure of Behavioral modeling:
Digital Laboratory
NBNSSOE75
/ 88
11. 3bit Controlled up / down synchronous counter with preset & clear.
Functional block diagram of 3 bit controlled up / down synchronous counter with preset &
clear:
Function table of 3 bit controlled up / down synchronous counter with preset & clear:
Design steps:
11. 3bit Controlled up / down synchronous counter with preset & clear.
INPUT:
Digital Laboratory
NBNSSOE76
/ 88
OUTPUT:
FAQs:
1. Explain the structure of behavioral modeling?
Digital Laboratory
NBNSSOE77
/ 88
Ans: BEGIN
Process( sensitivity list)
;
;
END process;
PRACTICE ASSIGNMENTS:
1. Implement 3 bit asynchronous up counter using behavioral modeling.
2. Implement 3 bit asynchronous down counter using behavioral modeling.
AIM
Digital Laboratory
NBNSSOE78
/ 88
Behavioral design is a technology independent, text based design that incorporates high
level functionality & high level information flow.
Structure of Behavioral modeling:
Inputs
Digital Laboratory
Outputs
NBNSSOE79
/ 88
rst
clk
dir
Data in
Q0
Q1
Q2
Data Out
1
0
0
0
0
0
0
x
1
1
1
1
1
1
x
0
0
0
1
1
1
X
D
0
D
D
D
0
0
D
0
0
D
D
0
D
D
0
0
0
D
D
D
D
0
0
0
D
0
0
D
Design steps:
Digital Laboratory
NBNSSOE80
/ 88
RTL Schematic:
Timing Diagram:
Digital Laboratory
NBNSSOE81
/ 88
INPUT:
OUTPUT:
FAQs:
1. Shared variables introduce the problem of non-determinism into VHDL. Explain this
with an example
Ans: u cannot put a shaed variable in a process sensitivity list...shared variables cause
non-determistic behaviour
architecture behaviour of SHARED is
shared variable S : integer;
begin
one : process (A, B)
begin
S := A + B;
end process;
Digital Laboratory
NBNSSOE82
/ 88
ELSE
Statement;
{statement ;}
END IF;
3. What is TEST bench ?
Ans: Test bench is part of a VHDL model that generates a set of test vectors and
sends them to the Module being tested. It collects the responses made by the Module
under Test and compares them against a specification of correct results.
4. Explain need of Test bench.
To ensure that design is correct .Model is operating as required.
5. Explain generate statement.
There are two types of generate statements.
Digital Laboratory
NBNSSOE83
/ 88
forgenerate
ifgenerate
Number of copies is
determined
conditionally
by a discrete range
Syntax:
Syntax:
{ concurrent_statement }
{ concurrent_statement }
PRACTICE ASSIGNMENTS:
1. Implement T flip-flop using behavioral modeling.
2. Implement JK flip-flop using behavioral modeling
3. Implement T and d using JK flip-flop.
4. Implement asynchronous clocked JK flip-flop.
5. Implement synchronous clocked JK flip-flop.
Digital Laboratory
NBNSSOE84
/ 88
APPENDIX
A. University Syllabus
214443: DIGITAL LABORATORY
Teaching Scheme
Practical: 4 hrs / week
A.
Examination scheme
Practical: 50 Marks
Oral: 50 Marks
1. Design (State diagram, state table & K map) and implementation of 4 bit Up, Down,
Controlled Up/Down asynchronous counter using master slave JK flip-flop IC 7476.
2. Design (State diagram, state table &K map) and implementation of 4 bit Up, Down,
Digital Laboratory
NBNSSOE85
/ 88
Instructor will frame assignments based on the suggested assignments as given above. Students
will submit the term work in the form of journal consisting of 12 assignments listed above.
Practical examination will be based on practical assignments and questions will be asked to
judge the understanding of assignments performed at the time of examination.
Note - Instructor should take care that datasheets of all the required ICs are available in
the laboratory & students are verifying the functionality of ICs being used.
C. Assignment separator for the students Journal.
Digital Laboratory
NBNSSOE86
/ 88
Assignment No.:
Date:
Title :
Digital Laboratory
NBNSSOE87
/ 88