TITLE: DESIGN OF A LOW-POWER AND AREA-EFFICIENT

CARRY SELECT ADDER

GROUP MEMBERS:
M.AMULYA
K.KEDAR
N.D.S.K.SEKHAR

BLENU4ECE08508
BLENU4ECE08507
BLENU4ECE08503

VII SEM/ ECE A

AMRITA SCHOOL OF ENGINEERING, BANGALORE

NAME OF THE GUIDE: Ms. KIRTI S PANDE

SIGN OF THE GUIDE:

ABSTRACT:
Carry Select Adder (CSLA) is one of the fastest adders used in many
data-processing processors to perform fast arithmetic functions. From the
structure of the CSLA, it is clear that there is scope for reducing the area and
power consumption in the CSLA.
This work uses a simple and efficient gate-level modification to
significantly reduce the area and power of the CSLA. Based on this
modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA)
architecture have been developed and compared with the regular SQRT CSLA
architecture.
The proposed design has reduced area and power as compared with the
regular SQRT CSLA with only a slight increase in the delay. This work
evaluates the performance of the proposed designs in terms of delay, area,
power, and their products by hand with logical effort and through custom
design and layout in 0.18m CMOS process technology. The results analysis
shows that the proposed CSLA structure is better than the regular SQRT
CSLA.
Power dissipation is one of the most important design objectives in
integrated circuits, after speed. As adders are the most widely used components
in such circuits, design of efficient adder is of much concern for researchers.
This project presents performance analysis of different Fast Adders. The
comparison is done on the basis of three performance parameters i.e. Area,
Speed and Power consumption. We present a modified carry select adder
designed in different stages. Results obtained from modified carry select
adders will be better in area and power consumption.

PLAN OF WORK AND TIME CHART:

DEADLINE

WORK TO BE DONE

End of December

Ground work to understand all the basic

designs to be used in the project.
Understanding the working of the
various adders used in the project.
Understanding the working of VHDL
and exploring the usage of various
commands needed for implementing
the various adders.
Implementation of the adders using the
designs found.
Comparing the various results obtained
and finding the best design that has the
lowest power consumption.

End of January
End of February

End of March
End of April

REFERENCES:

1. Padma Devi, Ashima Girdher, Balwinder Singh, CDAC, Mohali,

International Journal of Computer Applications (0975 8887) Volume 3
No.4, June 2010
2. G.A. Ruiz, M. Granda, Depto. de Electronica y Computadores, Facultad de
Ciencias, Universidad de Cantabria, Avda. de Los Castros s/n, 39005
Santander, Spain, Received 13 January 2004; received in revised form 23
August 2004; accepted 2 September 2004