Lecture 4: MIPS Instructions I

EEE 105: Computer Organization

MIPS
Used by NEC, Nintendo, Silicon Graphics, Sony, etc
Typical of instruction sets designed since the early 1980's
(RISC)

Arithmetic and Logical Operations

Design Principle 1: Simplicity favors regularity
Fixed number of operands
Examples

Instruction

Operation

add a,b,c

a=b+c

sub a,b,c

a=b-c

addi a,b,100

a = b + 100

and a,b,c

a=b&c

or a,b,c

a=b|c

sll a,b,10

a = b << 10

srl a,b,10

a = b >> 10

C-code
f=(g+h)-(i+j)
MIPS Assembly
add t0,g,h
add t1,i,j
sub f,t0,t1

MIPS Registers
Design Principle 2: Smaller is faster
MIPS has 32 32-bit registers, with the following usage convention:
Name

Reg #

Usage

$zero

Constant 0

$at

Reserved for assembler

Preserved
on call?

$v0-$v1

2-3

Values for results and expression evaluation

no

$a0-$a3

4-7

Arguments

yes

$t0-$t7

8 - 15

Temporaries

no

$s0-$s7

16 - 23 Saved

yes

$t8-$t9

24 - 25 Temporaries

no

$gp

28

Global pointer

yes

$sp

29

Stack pointer

yes

$fp

30

Frame pointer

yes

$ra

31

Return address

yes
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Encoding MIPS Instructions

Design Principle 1: Simplicity favors regularity
Fixed instruction length and format

R-type encoding
op

rs

rt

rd

shamt

funct

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

op: Opcode. Specifies the operation

rs: First register source operand
rt: Second register source operand
rd: Register destination operand
shamt: Shift amount
funct: Selects a specific variant of the operation specified in the opcode

R-type arithmetic/logic instructions

Instruction

op

rs

rt

rd

shamt

func

add

src reg

src reg

dest reg

32

sub

src reg

src reg

dest reg

34

and

src reg

src reg

dest reg

36

or

src reg

src reg

dest reg

37

sll

src reg

dest reg

shamt

srl

src reg

dest reg

shamt

Example: add $s1, $s2, $s3

0

18

19

17

32

000000

10010

10011

10001

00000

100000

Data Transfer Instructions

In most RISC ISA's, memory access is limited to data

transfer instructions only
C-code
Examples
Instruction

Operation

lw $s1,100($s2)

$s1=Mem[$s2+100]

sw $s1,100($s2)

Mem[$s2+100]=$s1

Note: Memory is byte-addressable

g=h+A[i];
MIPS Assembly
add $t1,$s4,$s4
add $t1,$t1,$t1
add $t1,$t1,$s3
lw $t0,0($t1)
add $s1,$s2,$t0

Note:
$s4 is offset
$s3 is base
$s2 is h
$s1 is g

I-type Instructions
Design Principle 3: Good design demands good compromises
Fixed instruction length and format, thus limited memory addressing

I-type encoding
op

rs

rt

address

6 bits

5 bits

5 bits

16 bits

op: Opcode. Specifies the operation

rs: Base (address) register for load word and store word
rt: Destination register for load word and store word
address: Address offset for load word and store word

I-type Instructions
Instruction

op

rs

rt

address

lw

35

base reg

dest reg

offset

sw

43

base reg

src reg

offset

Example: lw $t0, 1200($t1)

35

1200

100011

01001

01000

0000010010110000

Example: sw $t0, 1200($t1)

43

1200

101011

01001

01000

0000010010110000

Instructions for Making Decisions

Used for varying program flow

C-code

Examples
Instruction

Operation

beq $s1,$s2,L

if ($s1==$s2) go to L

bne $s1,$s2,L

if ($s1!=$s2) go to L

slt $s1,$s2,$s3
j 2500

if ($s2<$s3) then
$s1=1
else $s1=0
PC=(2500)*4

jr $t1

PC=$t1

if (i==j) f=g+h;
else f=g-h;

MIPS Assembly
bne $s3,$s4,Else
add $s0,$s1,$s2
j Exit
Else: sub $s0,$s1,$s2
Exit:

10

Branch Encoding
I-type encoding
Instruction

op

rs

rt

address

beq

src reg

src reg

(addr offset)/4

bne

src reg

src reg

(addr offset)/4

note: branch target address is (PC + 4) + (addr offset)

Example: bne $s1, $s2, 100

5

17

18

25

000101

10001

10010

0000000000011001

11

Set on Less Than encoding

R-type encoding
Instructions

op

rs

rt

rd

shamt

func

slt

src reg

src reg

dest reg

42

Example: slt $s1, $s2, $s3

0

18

19

17

42

000000

10010

10011

10001

00000

101010

12

Jump encoding
R-type encoding
Instructions

op

rs

rt

rd

shamt

func

jr

src reg

note: branch target address is contents of rs

J-type encoding
op

address
26 bits

6 bits
Instructions

op

address
(addr target)/4
note: branch target address:
lower 28 bits: addr target
upper 4 bits: upper 4 bits of PC
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Reference

Computer Organization and Design: The Hardware /

Software Interface, 2nd ed. Patterson and Hennessy

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