HIGH QUALITY TEST OF ARM CORTEX-A15

PROCESSOR USING TESSENT

TESTKOMPRESS

DAVE MACEMON, MENTOR GRAPHICS

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W H I T E

P A P E R

SEPTEMBER 2011

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High-Quality Test of ARM Cortex-A15 Processor using Tessent TestKompress

CONTENTS
Abstract.................................................................................................................................................................................. 2
ARM Cortex-A15 Processor Overview .......................................................................................................................... 2
Mentor reference flow for ARM architecture ............................................................................................................. 2
Conclusion ............................................................................................................................................................................ 3

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High-Quality Test of ARM Cortex-A15 Processor using Tessent TestKompress

ABSTRACT
Customers are integrating single or multiple ARM Cortex-A15 processors into their SoC
designs in order to take advantage of this industry-leading IP. In order to perform
manufacturing test for the SoC, a test strategy needs to be adopted and the
corresponding DFT implemented to achieve that test strategy. Traditionally, it has been up
to the design-for-test (DFT) engineer to understand the test strategy and implement the
DFT associated with it.
With the introduction of this jointly developed Mentor reference flow for ARM
architecture, DFT engineers now have a guide so they can effectively and efficiently test
designs that include the ARM Cortex-A15 processor. This white paper provides a high
level overview of the Mentor reference flow for ARM architecture.

ARM CORTEX-A15 PROCESSOR OVERVIEW

As shown in Figure 1, the ARM Cortex-A15 processor is composed of a non-CPU block and
1, 2, or 4 CPU blocks. The blocks are stitched together at the top level.
Test logic is inserted into the non-CPU block and into each CPU block. Tessent
TestKompress is set up to test the non-CPU block and the CPU blocks. When testing the
cores, the test stimulus is broadcast to each of the CPU blocks, and each CPU block has
dedicated output channels for test results.

Figure 1: Block-level view of the ARM Cortex-A15 Processor

MENTOR REFERENCE FLOW FOR ARM ARCHITECTURE

Unlike other IP that may be used in an SoC, the Mentor reference flow for ARM
architecture provides documented steps, and dofiles (command scripts) that control the
test insertion, synthesis and automatic test pattern generation (ATPG).
The jointly developed flow utilizes Cadence RTL Compiler for synthesis. DFTAdvisor and
Tessent TestKompress from Mentor Graphics are used for scan insertion and to generate
the compression hardware that is used for test.
After the design is synthesized using RTL Compiler, DFTAdvisor is used to insert scan
chains into the non-CPU block and into the CPU block.

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High-Quality Test of ARM Cortex-A15 Processor using Tessent TestKompress

Figure 2: Test synthesis and pattern generation flow diagram

Tessent TestKompress logic is generated and inserted into the CPU blocks, as well as the
non-CPU block. After the Tessent TestKompress logic has been synthesized into the
design, the non-CPU block and the CPU blocks are instantiated into a complete ARM
Cortex-A15 processor. Test patterns are generated for the ARM Cortex-A15 processor.
The ARM Cortex-A15 processor is now setup to be tested with Tessent TestKompress in
modular or hierarchical mode. The DFT engineer now has the flexibility to implement the
tests to meet the various test budgets including test time, pattern volume and power.

CONCLUSION
The Mentor reference flow for ARM architecture provides a repeatable process for
inserting test logic and generating manufacturing tests for the ARM Cortex-A15 processor
designs. This saves time and ensures a high quality test while meeting low power targets
and limiting switching activity to 25%.
For more information, and access to the Mentor reference flow for ARM architecture, go to
http://supportnet.mentor.com/

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