Comparative Analysis of Cascade H-Bridge Multilevel

Voltage Source Inverter

Hiral V Sabhaya

Vishal S Sheth

Under Graduate Student

Department of Electrical Engineering
A D Patel Institute of Technology,
New V. V. Nagar-388121, India
sabhaya.hiral@gmail.com

Assistant Professor
Department of Electrical Engineering
A D Patel Institute of Technology,
New V. V. Nagar-388121, India
vshalsheth@gmail.com

Abstract In real time industrial applications, there are many

limitations in extracting power from renewable energy sources.
To meet the increasing power demand, multilevel inverter is
widely used to extract power from solar cells. It synthesizes the
desired ac output from several dc sources. This paper presents
comparative analysis of different cascaded H-Bridge multilevel
inverter topologies employing low switching frequency devices to
reduce thermal stress and improve conversion efficiency. The
inverter is operated on fundamental frequency switching strategy.
The present topology provides high quality output power due to
its more output levels, low thermal stress and high conversion
efficiency. This multilevel topology enables to achieve highquality output voltages and output currents and also immense
availability because of their intrinsic switches redundancy. This
paper presents comparative analysis in terms of THD and FFT of
different level topologies. The different Multi level Inverter
Topologies are simulated in PSIM.
Index Terms Cascade multilevel H Bridge inverter, Total
Harmonic Distortion, Fast Fourier Transformation analysis,
Comparative analysis between various level topologies, PSIM
software.

I. INTRODUCTION
The multilevel inverter has obtained much attention in
recent years due to its advantages in high power
transformation with low harmonics applications. The main
objective of the multilevel inverter is to extract a desired high
voltage from several levels of dc voltages that can be batteries,
fuel cells, photovoltaic etc. Nowadays, there are exists three
topologies of multilevel voltage source inverters named as:
neutral point clamped (NPC) or Diode Clamped (DC), flying
capacitors (FCs) and cascaded H-bridge (CHB) [2]. Amongst
these inverter topologies, cascaded multilevel inverter has
many advantages like it reaches up to the higher output
voltage and higher power levels (13 kV, 30 MVA) and also
has higher flexibility due to its modular topology [3].
In CHB inverters, there are several single-phase H-Bridge
inverters connected in series fashion. This structure is capable
of fulfil requirement of medium output voltage levels by using
only standard low-voltage component. Typically, it is
necessary to connect four to eleven inverters in series to obtain
the required output voltage.

Cascade H-Bridge Multi level inverters also have a

feature of high modularity index because each inverter module
will be seems like a module with similar circuit topology,
modulation and, control structure [1]. So, in the case of fault
in any one of these modules, it is possible to replace it with
another one quickly and easily. Moreover, with a particular
control strategy, it is possible to bypass and disconnect the
faulty module without interrupting the entire load, bringing an
almost continuous overall availability.
This paper presents basics of cascaded H-Bridge
multilevel inverters, its working principle, circuit topologies,
control techniques, simulation & comparative analysis in
terms of THD and FFT of different level H Bridge topologies.
II. BASICS OF H BRIDGE INVERTER
Fig.1 shows H-bridge Voltage Source Inverter. Each Hbridge inverter circuit consists of four main switches and four
freewheeling diodes which can give either of positive or
negative polarity output voltage; or it can also be zero volts,
that depends on the switching condition of the switches. Three
level CHB is the smallest no. of voltage level for a multilevel
inverter using cascaded-inverter. To achieve a three-level
waveform, a single unit of full-bridge inverter is required.
Generally, a full-bridge inverter is known as an H-bridge cell,
which is given in Figure 1. According to four-switching
combinations pattern, three output voltage levels, +V, -V, & 0
can be extracted for the voltages across A and B. During
inverter operation shown in Fig. 1, switches S and S are
1

closed at the same time to provide V a positive voltage and a

AB

current path for Io. Switch S and S are turned on to provide

V

AB

a negative voltage with a path for Io shown in fig 2.

When all switches are turned off, the current will be pass
through the freewheeling-diodes. In case of zero level, there
are two possible switching patterns to obtain zero level, for
example: (1) S S on, S S off (2) S S off, S S on. We can use
1 2

3 4

any of them for obtain zero level.

1 2

3 4

TABLE 1
Switching table for H-Bridge

S1
1
1

0
Vdc
0
0
-Vdc
0

S2
1

S3

1
1
1

1
1
1

1
1

S4

Because zero voltage level is common for all inverter outputs,

hence the total number of output voltage level becomes 2S+1.
For example, a 9 level output phase voltage waveform can be
obtained with four H-bridge modules and four separated dc
sources. Here 9 Level H-bridge inverter circuit diagram are
shown in Fig. 3 and phase voltage waveform for a nine-level
cascaded inverter are shown in Fig. 4. In this case, all dc
voltage sources are assumed to be equal,
i.e.,

1=

2=

3= .

( 1)=

(3)

The main advantage of cascaded multilevel inverter is

modularized layout and packaging. This makes the
manufacturing process to be done more quickly and at a low
cost. The drawback of this topology is that it needs a separate
DC source for each H-bridge and it involves high number of
semiconductor switches.

Fig.1 Diagram for basic H-Bridge structure

Fig.2 Output voltage wave form of an H-bridge inverter.

III. CASCADED MULTILEVEL H BRIDGE INVERTER

The conventional two or three levels inverter does not
completely eliminate the unwanted harmonic components in
the output. Therefore, using the multilevel inverter as an
alternative to conventional PWM inverters is investigated. To
synthesize a multilevel waveform by H bridge circuit, the ac
output of each of the different levels of H-bridge cells are
connected in series. And at the end, final obtained output
voltage waveform is the sum of all individual inverter outputs.
The S number of sources or stages and the according to that,
number of output voltage level can be written as below:

Fig.3 Circuit diagram of 9 Level H-bridge inverter.

Mlevel =2S+1 (1)

Where S is the number of dc sources. Here the output
voltage is the sum of each individual H-bridge output and it is
given as:
=

1+

2+

3+

( 1)+

(2)
Fig.4 Phase voltage waveform of 9 Level H-bridge inverter.

The magnitude and THD content of the output voltage

depends on the switching angles at which switches will be
fired and voltage level of output voltage. Therefore, these
angles need to be selected properly to minimize total harmonic
distortion. To eliminate selective harmonics, we have to select
the switching sequence carefully.
IV. SELECTIVE HARMONICS ELIMINATION

From equation (4), the expressions for fundamental

voltage in terms of m, and lower order harmonic components,
when they are eliminated, can be written as for 7-level CHB:

(6)
For 11-level CHB, corresponding equations are as follows:

By taking, the Fourier series expansion equation of the

staircase output voltage waveform as shown in Fig. 4
(7)
Similarly for 13-level CHB, equations are given below:
. (4)
Where S is the number of H-bridges module connected in
cascade per phase and k is order of harmonic components. For
a given desired fundamental peak voltage V1, it is required to
determine the switching angles such that 0 1 < 2 < s
/2 and some predominant lower order harmonics of phase
voltage are zero. Among s number of switching angles,
basically one switching angle is used for fundamental voltage
selection and the remaining (s-1) switching angles are used to
eliminate certain predominating lower order harmonics. In
three-phase power system, triplen harmonic components are
absent in line-to-line voltage, as a result, only non-triplen odd
harmonic components are present in line-to-line voltages [1]
From equation (4), the expression for the fundamental
voltage in terms of switching angles is given by

(8)
The equations (6,7,8) are transcendental equations, known
as selective harmonic elimination (SHE) equations, where
unknown parameters are switching angles. The first equation
of the set of equations given by (6,7,8) determines the
magnitude of fundamental voltage for a given value of m, and
the remaining equations eliminate selective harmonic
components [1]. The equations (6,7,8) are to be solved by
employing N-R method in such a way that all possible
solutions for a given value of m are obtained without much
computational effort. The algorithm for the solution of
equations (6,7,8) is given in [1].
V. SIMULATION & ANALYTICAL RESULTS

Moreover, the relation between the fundamental voltage

and the maximum obtainable voltage is given by modulation
index.
The modulation index, m, is defined as the ratio of the
fundamental output voltage (V1) to the maximum obtainable
fundamental voltage. The maximum fundamental voltage is
obtained when all the switching angles are zero i.e. V1max =
4sVdc/, therefore,
m = V1/4sVdc [1].
For 7, 11 and 13-level cascade multilevel inverters, s = 3,
s = 5 and s = 7 respectively. Number of degrees of freedom
available is equal to s; one degree of freedom is used to
choose the value of V1 and remaining degrees of freedom are
used to eliminate the lower order harmonics. For example, in
case of 7-level CHB, only two harmonic components (in
general, 5th and 7th ) can be eliminated, similarly for 11-level
CHB, four harmonic components (i.e. 5th , 7th , 11th and 13th )
and in 13-level CHB, six harmonic components (i.e. 5th , 7th ,
11th , 13th , and 17th ) can be eliminated.

By using PSIM software, all possible solution sets for a 5,

7, 9, 11 and 13-level CHBs are calculated and a complete
analysis is presented.
For different Level CHB, We can obtain different level
voltage output by various switching sequences. Here
Presented switching sequence are set for low switching
stresses and less heating effect for particular switch which is
mentioned in below.
For each of the multiple solution sets as calculated above,
total harmonic distortion (THD) in percentage is computed
according to equation 6. The set of switching angles among
multiple solutions which produce least THD is selected for
switching of semiconductor devices, and these are termed as
combined solutions.

But here, we calculated THD by PSIM software from output

voltage of each topology. The FFT performance of each
topology are also given below in the form of graph which is
obtain by PSIM software. The simulation results, output
voltage waveforms and comparison between all of them are
given below.

SWITCHING TABLE FOR 11 LEVEL CHB

TABLE 2
SWITCHING TABLE FOR 9 LEVEL CHB

Vout

S
1

S
2

S
3

S
4

S
5

Vdc

2 Vdc

3 Vdc

4 Vdc

S
6

S
7

S
8

S
1
3

S
1
4

S
1
5

S
1
6

2 Vdc

Vdc

-2 Vdc

1
1

1
1
1

-3 Vdc

1
1
1

1
1

1
1

1
1
1

1
1

1
1

-2 Vdc

-Vdc

S
9

S
1
0

S
2

S
3

S
4

S
5

S
6

S
7

S
8

S
1
2

S
1
3

S
1
4

S
1
5

S
1
6

S
4

S
5

S
6

S
7

S
8

S
9

S
1
0

1
1
1

1 1 1
1 1

1 1
1 1 1

1 1

1
1

-5
Vdc
-4
Vdc
-3
Vdc
-2
Vdc
Vdc
0

S
1
1

S
1
2

S
1
3

S
1
4

S
1
5

S
1
6

S
1
7

S
2
0

1 1

1 1 1

1 1

1 1

1 1

1 1

1 1 1

1 1

1 1

1 1

1 1

1 1 1

1 1

1 1

1 1

1 1

1 1 1

1 1

1 1

1 1

1 1

1 1 1

1 1

1 1
1

1 1

1 1

1 1 1

1
1
1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1 1

1
S
2

S
3

S
4

S
5

S
6

S
7

S
8

S
9

S
1
0

S
1
1

S
1
2

S
1
3

S
1
4

S
1
5

S
1
6

S
1
7

FIGURE 5 OUTPUT VOLTAGE WAVEFORM OF 9 LEVEL CHB

FIGURE 7 OUTPUT VOLTAGE WAVEFORM OF 11 LEVEL CHB

FIGURE 6 FFT ANALYSIS OF 9 LEVEL CHB

TABLE 3

S
1
9

1 1
1 1

1 1

S
1

S
1
8

1 1
1 1

1
1 1

Vdc
-2
Vdc
-3
Vdc
-4
Vdc

1
S
1
1

S
3

Vdc
2
Vdc
3
Vdc
4
Vdc
5
Vdc
4
Vdc
3
Vdc
2
Vdc
Vdc
0

S
2

-3 Vdc

S
1

S
1
2

-4 Vdc

S
1
1

3 Vdc

-Vdc

S
9

S
1
0

S
1

S
1
8

S
1
9

S
2
0

VI. COMPARATIVE ANALYSIS OF DIFFERENT LEVEL

CHB TOPOLOGIES:
TABLE 4
COMPARATIVE ANALYSIS OF 3, 5, 7, 9, 11 & 13 LEVEL CHB

FIGURE 8 FFT ANALYSIS OF 11 LEVEL CHB

FFT

LEVEL

THD
(in %)

80.42%

63.30V

42.97%

140.02V

31.14%

222.58V

25.67%

302.74V

11

22.29%

383.92V

13

20.23%

464.78V

Fundamental

RD

41.81V
(66.05%)
46.74V
(33.38%)
54.28V
(24.38%)
63.18V
(20.83%)
70.96V
(18.43%)
79.54V
(17.11%)

5TH

7TH

12.54V
(19.81%)

8.92V
(14.09%)
20.00V
(14.28%)
17.83V
(8.01%)
18.80V
(6.20%)
19.57V
(5.09%)
20.87V
(3.22%)

0V (0%)
1.41V
(0.63%)
3.76V
(1.24%)
6.71V
(1.74%)
9.35V
(2.01%)

The analytical result shown in table 5, In which we

can see the THD is more than 5% for all values of modulation
indices, hence not satisfying IEEE-519 standard. This type of
output voltage cannot be used directly for power system and
industrial drive applications due to high THD. Here the THD
of 13 level CHB is around 20% that can be minimize up to 2%
by simply putting filter inductor-capacitor. In our analysis, the
value of series inductor is 0.010H and the value of shunt
capacitor is 2200F, which can minimize the THD up to 2%
in 13 level CHB.
VII. CONCLUSION
FIGURE 9 OUTPUT VOLTAGE WAVEFORM OF 13 LEVEL CHB

FIGURE 10 FFT ANALYSIS OF 13 LEVEL CHB

The switching sequence for cascade multilevel

inverters of 5, 7, 9, 11 and 13-level has been calculated for
analysis of total harmonic distortions produced in the output
voltage and complexity in computation of these sequence. It
has been found that complexity in computation of switching
sequence increases with increase in number of levels as more
sets of solution are produced but the operating range of
modulation index goes down. On the other part, the THD in
output voltage decrease and output voltage increase with
increase in number of levels. Analytical results are validated
with simulation results for all level of CHBs. This paper has
reviewed the comparative analysis in terms of THD and FFT
performance of different level CHBs done by PSIM 9.0
software. By comparison table 5, we can conclude that as the
no. level increases, the 3rd, 5th, and 7th Harmonic components
are reduced when compared with fundamental component.

REFERENCES
[1] Dr. Jagdish Kumar ,THD Analysis for Different Levels
of Cascade Multilevel Inverters for Industrial Applications
International Journal of Emerging Technology and Advanced
Engineering
[2] Surin Khomfoi, Chatrchai Aimsaard A 5-Level Cascaded
Hybrid Multilevel Inverter for Interfacing with Renewable
Energy Resources IEEE Trans 2009
[3] S. Ali Khajehoddin, Praveen Jain, and Alireza Bakhshai
Cascaded Multilevel Converters and Their Applications in
Photovoltaic Systems 2nd Canadian Solar Buildings
Conference Calgary, June 10 - 14, 2007
[4] *M.Murugesan, R.Sakthivel, E. Muthukumaran and
R.Sivakumar Sinusoidal PWM Based Modified Cascaded
Multilevel Inverter /International Journal Of Computational
Engineering Research / ISSN: 22503005
[5] Gobinath.K, Mahendran.S, Gnanambal. I NEW
CASCADED H-BRIDGE MULTILEVEL INVERTER WITH
IMPROVED EFFICIENCY International Journal of
Advanced Research in Electrical, Electronics and
Instrumentation Engineering Vol. 2, Issue 4, April 2013
[6] PSIM software version 9.0.0