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Experiment 4
Experiment 4
Experiment 4
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Group No: 01
Lab Number: 04
Prepared By:
Student Name: Anupam Golder
Student ID: 0906004
Name of Group Member: Anik Saha
Student ID of Group Member: 0906001
Date of Experiment: 23/08/2014
Date of Report: 30/08/2014
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ABSTRACT
In this experiment, Cadence Virtuoso Layout Suite L has been used to build the layout view of a
CMOS Inverter with the constraint that it should be of minimum possible size. Then using
Cadence ASSURA the DRC rules have been checked for design errors and using ASSURA LVS
check, layout has been matched with the schematic. The process technology adopted for this
experiment is gpdk090 which is a 90nm technology. The purpose of this experiment was to get
acquainted with the design rules that come into action when minimum size devices are to be
designed.
KEYWORDS
Virtuoso
ASSURA
Inverter
Layout
DRC
LVS
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TABLE OF CONTENTS
Page
Abstract...2
Keywords.2
Table of Contents....3
List of Figures.....4
List of Tables...4
1. Introduction.....5
2. Theory.5
3. Lab Handout Question ...8
4. Tools Used...8
5. Procedure 8
6. Results ....8
6.1 Layout of the inverter......8
6.2 Errors Received...................9
6.3 List of rules....10
6.4 List of some good practices.......10
6.5 Fabrication Sequence of the CMOS Inverter.11
6.6 LVS Check ...13
7.Conclusion13
8.References. 13
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LIST OF FIGURES
Page
5
6
6
7
8
9
9
10
11-13
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LIST OF TABLES
9-10
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INTRODUCTION
In this experiment, a layout of a CMOS inverter has been designed in Cadence Virtuoso Layout Suite L.
The design rules have specifications for minimum width, area, separations, enclosure, butting and overlapping.
To ensure the minimum possible area for the inverter layout all the rules have been carefully checked and
followed. The rules were specified for gpdk090 technology.
After the DRC check has been performed, several DRC errors have been found which have been corrected.
Then LVS check has been performed which ensured that the layout and the schematic of the inverter
matched. Several issues have been encountered like mismatched pins and nets which have been corrected.
This experiment can help demonstrate how design rules come into play when minimum sized devices are to
be designed and the reason behind following the rules which is related to the accuracy of the fabrication process
for the specified technology.
THEORY
VLSI Design Process
The VLSI design process goes through the following steps:
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CMOS Inverter:
The CMOS inverter consists of a PMOS and an NMOS transistor. They must be properly shaped to account for the
fact that holes have lower mobility than electrons. So the PMOS transistor generally has a larger size and to reduce
the undesirable effects due to larger size, twice the no. of contacts in NMOS are placed in the PMOS.
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0.14m
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TOOLS USED
1. Cadence Virtuoso Layout Suite L
2. Cadence ASSURA DRC
3. Cadence ASSURA LVS
PROCEDURE
RESULTS
1. Layout of the CMOS inverter as designed:
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This might be due to the error in drawing which led to the p-sub or nwell being not connected to proper
connections (GND or VDD).
6
7
8
9
10
11
12
13
Poly gates cannot have bends. We have to use path to connect poly gates to input or output pin.
Minimum contact to gate spacing must be 0.1 um. This occurred due to error 8.
Minimum poly to contact enclosure must be 0.04um.
Poly to contact enclosure on at least two opposite sides must be greater than 0.06 um.
Contact on gate is not allowed. It occurred due to error 8.
Metal area smaller than .07
are not allowed.
Table No. 1 Meanings of the errors
After all the errors have been corrected, DRC check yielded the following window:
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5. Fabrication sequence of the CMOS inverter with masks and cross-section: (From Q & A section)
Start: For an n-well process, the starting point is p-type silicon wafer.
Epitaxial growth: A single p-type single crystal film is grown on the surface of the wafer by oxidation.
D ia m e te r = 7 5 to 2 3 0 m m
p -e p ita xia l la ye r
< 1m m
P + -typ e w a fe r
La tera l
diffu sio n
n -w ell
p-typ e ep ita xial la ye r
Active area definition: A thin layer of SiO2 is grown over the active region and covered with silicon nitride.
A c tive m ask
S ilico n N itrid e
n-w e ll
p -typ e
Isolation: i)Channel-stop implant:The silicon nitride (over n-active) and the photoresist (over n-well) act as masks
for the channel-stop implant
c h a n n e l s to p m a s k = ~ ( n - w e ll m a s k )
Im p la n t (B o ro n )
r e s it
n -w e ll
p -ty p e
p + c h a n n e l- s to p im p la n t
ii) Local oxidation of silicon(LOCOS): growing thick oxide field after removing photresists.
p a tte rn e d
a c t iv e
a re a
F ie ld
o x id e
(F O X )
n - w e ll
a c tiv e
a re a
a fte r L O C O S
p -ty p e
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Gate oxide growth: After removing stress-relief oxide and nitride gate oxide (thin) is grown.
n - w e ll
p -ty p e
G a t e o x id e
to x
tox
n - w e ll
p -ty p e
Polysilicon deposition and patterning: A layer of polysilicon is deposited on entire wafer and then photolithography
is used to pattern it.
P o lysilico n m a sk
P o lysilico n g ate
n -w ell
p -typ e
p+ implant (boron)
p+ mask
n-well
Photoresist
p-type
NMOS formation: n+ is implanted.
n + im pla n t (arse nic o r p ho sp h orou s)
n + m as k
n -w ell
P h o toresist
p -typ e
n - w e ll
n+
p+
p -ty p e
12
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Contact cuts: The surface of the IC is covered by a layer of CVD oxide. Contact cuts are defined by etching SiO2
down to the surface to be contacted.
C o n ta ct m a sk
n -w e ll
n+
p+
p -ty pe
Metal1: A first level of metallization is applied to the wafer surface and selectively etched to produce the
interconnects.
m e ta l 1 m a s k
m e ta l 1
n -w e ll
n+
p+
p -ty pe
The LVS check lead to no error. The output window is shown below:
CONCLUSION
In this experiment three basic steps of CMOS process flow Layout Design, DRC and LVS checking have been
studied in Cadence. The layout of a basic inverter has been drawn in the Cadence Virtuoso Layout Suite L for
gpdk90nm process parameters. The design rules of the layout have been checked by the Cadence ASSURA and all
the errors have been resolved. And finally, the LVS check has been performed. Another objective was to obtain
minimum possible dimension for the inverter, which, as we have calculated, has been obtained as instructed. This
experiment helped understand the layout design process rules.
REFERENCES
1. http://en.wikipedia.org/wiki/Integrated_circuit_layout
2. http://en.wikipedia.org/wiki/Design_rule_checking
3. Neil H. E. Weste, David Harris and Ayan Banerjee, CMOS VLSI Design: A Circuits and Systems
Perspective, Third Edition, Chapter 4, Section 6,Pearson Education, 2005
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