Static and Dynamic Translinear Circuits

Static and Dynamic Translinear Circuits
Bradley A. Minch
Mixed Analog-Digital VLSI Circuits and Systems Lab
Franklin W. Olin College of Engineering
Needham, MA 024921200
bradley.minch@olin.edu
May 20, 2010
Translinear Circuits: Whats in a Name?

In 1975, Barrie Gilbert coined the term translinear to describe a class of circuits whose
large-signal behavior hinges both on the precise exponential I/V relationship of the bipolar
transistor and on the intimate thermal contact and close matching of monolithically integrated
devices.
The word translinear refers to the exponential I/V characteristic of the bipolar transistorits
transconductance is linear in its collector current:
VBE /UT
IC = Is e
IC
IC
VBE /UT 1
gm =
= Is e
=
.
VB UT UT
IC
Gilbert also meant the word translinear to refer to circuit analysis and design principles that
bridge the gap between the familiar territory of linear circuits and the uncharted domain of
nonlinear circuits.

devices.
VBE /UT
IC = Is e
IC
IC
VBE /UT 1
gm =
= Is e
=
.
VB UT UT
IC
nonlinear circuits.

devices.
VBE /UT
IC = Is e
IC
IC
VBE /UT 1
gm =
= Is e
=
.
VB UT UT
IC
nonlinear circuits.
Gummel Plot of a Forward-Active Bipolar Transistor

10m
1m
IB, IC (A)
100m
IC
IC = IseVB/UT
10m
IB
1m
100n
IB =
10n
IC
bF
Is = 105 fA
UT = 25.6 mV
bF = 679
1n
100p
0.25
VB
0.3
0.35
0.4
0.45
0.5
VB (V)
0.55
0.6
0.65
+5 V
Translinearity of the Forward-Active Bipolar Transistor

1
IC + dIC
100m
IB + dIB
gm (S)
10m
gm =
1m
IC
UT
VB
+ dVB
100m
10m
gm =
1m
100n
1n
UT = 25.6 mV
10n
100n
1m
10m
IC (A)
100m
1m
10m
IC
IC
=
VB UT
IC gmVB
+5 V
The Translinear Principle

Consider a closed loop of base-emitter junctions of four closely matched npn bipolar transistors
biased in the forward-active region and operating at the same temperature. Kirchhos voltage
law (KVL) implies that
V1 + V2
I1
I2
UT log + UT log
Is
Is
I1 I2
log 2
Is
I1 I2

CCW
= V3 + V4
I3
I4
= UT log + UT log
Is
Is
I3 I4
= log 2
Is
=
I3 I4 .
counterclockwise
element
I2
I1
clockwise
element
I3
I4
V2 V3
V1
V4
CW
This result is a particular case of Gilberts translinear principle (TLP): The product of the
clockwise currents is equal to the product of the counterclockwise currents.
Why Translinear Circuits?

Translinear circuits are universal. Conjecture: In principle, we can realize any system
whose description we can write down as a nonlinear ODE with time as its independent
variable as a dynamic translinear circuit.
Translinear circuits are synthesizable via highly structured methods. They should be very
amenable to the development both of CAD tools and of recongurable FPAA architectures
for rapid prototyping and deployment of translinear analog signal processing systems.
Translinear circuits are fundamentally large-signal circuits. Linear dynamic translinear
circuits are linear because of device nonlinearities rather than in spite of them.
Translinear circuits are tunable electronically over a wide dynamic range of parameters
(e.g., gains, corner frequencies, quality factors).
Translinear circuits are robust. Carefully designed translinear circuits are temperature
insensitive and do not depend on device or technology parameters.




Simple EKV Model of the Saturated nMOS Transistor

We model the saturation current of an nMOS transistor by

Isat = SIs log 1 + e((VGVT0)VS)/2UT
((VG VT0 )VS )/UT

, (VG VT0 ) VS < 0
SIse
SIs
2
(
(V
V
)
V
)
, (VG VT0) VS > 0,
G
T0
S
2
4UT
2
where
W
Cox
kT
2CoxUT2
, S = , Is =
, and =
.
UT =
q
L
Cox + Cdep
Weak inversion operation corresponds to Isat SIs, moderate inversion operation corresponds to Isat SIs, and strong inversion operation to Isat SIs. Note that SIs is
approximately twice the saturation current at threshold.
Saturation Current of an nMOS Transistor

10m
Isat = SIs ek(VG VT0)/UT
1m
100m
10m
Isat (A)
Isat
SIs = 3.93 mA
Isat = SIs log2(1+ ek(VG VT0)/2UT)
1m
100n
Isat =
+5 V
SIs
2
2 (k(VG VT0))
4UT
VG
10n
1n
100p
k = 0.715
UT = 25.8 mV
VT0 = 0.647 V
0
0.5
1.5
VG (V)
2.5
Translinearity of the Saturated nMOS Transistor

10m
1m
gm (S)
100m
10m
gm =
k
SIsIsat (1 e
UT
k
SIsIsat
gm =
UT
gm =
k
I
UT sat
Isat + dIsat
Isat/SIs
+5 V
VG
+ dVG
1m
100n
gm =
10n
1n
100p
SIs = 3.93 mA
1n
10n
100n
1m
10m
Isat (A)
k = 0.715
UT = 25.8 mV
100m
1m
10m
Isat Isat
=
, Isat SIs
VG
UT
Isat gmVG
Weak-Inversion MOS Translinear Principle

When designing weak-inversion MOS translinear circuits, if we restrict ourselves to using
translinear loops that alternate between clockwise and counterclockwise elements, we obtain
Gilberts original TLP, with no dependence on the body eect (i.e., ).
stacked loop
I2
alternating loop
I3
I1
I4
TLP: I1I2 = I3I4
I1
I2
I3
I4
TLP: I1I3 = I2I4
This restriction does not limit the class of systems that we can implement. However, designs
based on alternating loops generally consume more current but operate on a lower power
supply voltage than do designs based on stacked loops.
10
Static Translinear Circuits: Squaring/Reciprocal
Ix
Iy
Ix
TLP = Ix2 = Iy Iz
Ix2
= Iz =
Iy
V0
Iy
Ix
Ix
Iz
V0
10

10m
Ix
Iy
Ix
1m
Iz
mA
=1
A
10
0n
V0
Iy
A
100n
10
n
Iz (A)
V0
10n
1n
1n
Ix2
Iz =
Iy
10n
100n
Ix (A)
1m
10m
10

10m
Ix
1m
Ix
1m
Iy
Ix
Iz
Iz (A)
V0
10
0n
100n
10n
1n
1n
10
n
10n
V0
Ix2
Iz =
Iy
100n
Iy (A)
1m
10m
11
Static Translinear Circuit Synthesis: Pythagorator

Synthesize a two-dimensional vector-magnitude circuit implementing

r = x2 + y 2,
where x > 0 and y > 0.
We represent each signal as a ratio of a signal current to the unit current:

x
Ix
,
I1
Iy
,
I1
and r
Ir
.
I1
We substitute these into the original equation and rearrange to obtain

Ir
=
I1
Ix
I1
2

+
Iy
I1
2
=
Ir2 = Ix2 + Iy2
Iy2
Ix2
Ir =
+
Ir
Ir

Ir1
Ir2
11


r = x2 + y 2,

x
Ix
,
I1
Iy
,
I1
and r
Ir
.
I1

Ir
=
I1
Ix
I1
2

+
Iy
I1
2
=
Ir2 = Ix2 + Iy2
Iy2
Ix2
Ir =
+
Ir
Ir

Ir1
Ir2
11


r = x2 + y 2,

x
Ix
,
I1
Iy
,
I1
and r
Ir
.
I1

Ir
=
I1
Ix
I1
2

+
Iy
I1
2
=
Ir2 = Ix2 + Iy2
Iy2
Ix2
Ir =
+
Ir
Ir

Ir1
Ir2
11


r = x2 + y 2,

x
Ix
,
I1
Iy
,
I1
and r
Ir
.
I1

Ir
=
I1
Ix
I1
2

+
Iy
I1
2
=
Ir2 = Ix2 + Iy2
Iy2
Ix2
Ir =
+
Ir
Ir

Ir1
Ir2
11


r = x2 + y 2,

x
Ix
,
I1
Iy
,
I1
and r
Ir
.
I1

Ir
=
I1
Ix
I1
2

+
Iy
I1
2
=
Ir2 = Ix2 + Iy2
Iy2
Ix2
Ir =
+
Ir
Ir

Ir1
Ir2
11


r = x2 + y 2,

x
Ix
,
I1
Iy
,
I1
and r
Ir
.
I1

Ir
=
I1
Ix
I1
2

+
Iy
I1
2
=
Ir2 = Ix2 + Iy2
Iy2
Ix2
Ir =
+
Ir
Ir

Ir1
Ir2
12

TLP: Ir1Ir = Ix2
Ir2Ir = Iy2
KCL: Ir = Ir1 +Ir2
12

TLP: Ir1Ir = Ix2
Ir2Ir = Iy2
Ix
V0
Ir1
Ix
KCL: Ir = Ir1 +Ir2
Ir
V0
12

TLP: Ir1Ir = Ix2
Ir2Ir = Iy2
Ix
Ir1
Ix
KCL: Ir = Ir1 +Ir2
Ir
V0
V0
Iy
V0
Ir2
Iy
Ir
V0
12

TLP: Ir1Ir = Ix2
Ir2Ir = Iy2
Ix
Ir1
Ix
V0
Ir
V0
Iy
V0
KCL: Ir = Ir1 +Ir2
Ir2
Iy
12

TLP: Ir1Ir = Ix2
Ir2Ir = Iy2
Ix
V0
Ir1
Ix
KCL: Ir = Ir1 +Ir2
Ir
V0
Iy
Ir2
Iy
V0
12

TLP: Ir1Ir = Ix2
Ir2Ir = Iy2
Ix
Ix
Ix
V0
Ix + Ir1
KCL: Ir = Ir1 +Ir2
Ir1
Iy
Ix
Ir
Iy
V0
Ix + Ir1
Iy
Ir2
Iy
V0
Iy + Ir2
Iy + Ir2
13
Dynamic Translinear Circuit Synthesis: Output Structures

noninverting
inverting
It
It
It
In
Vn
Icn
C
V0
It
Vn
In
Icn
C
It
In = I e(VnV0)/UT
In
In
=
Vn UT
In = I e(V0Vn)/UT
In
In
=
Vn
UT
V0
14
Dynamic Translinear Circuit Synthesis: First-Order LPF

Synthesize a rst-order low-pass lter described by
dy
+ y = x,
dt
where x > 0.

Iy
Ix
and y .
x
I1
I1
Substituting these into the ODE, we obtain
d
dt
Iy
I1
Iy
Ix
+
=
I1
I1
dIy
+ Iy = Ix .
dt
14

dy
+ y = x,
dt
where x > 0.

Iy
Ix
and y .
x
I1
I1
d
dt
Iy
I1
Iy
Ix
+
=
I1
I1
dIy
+ Iy = Ix .
dt
14

dy
+ y = x,
dt
where x > 0.

Iy
Ix
and y .
x
I1
I1
d
dt
Iy
I1
Iy
Ix
+
=
I1
I1
dIy
+ Iy = Ix .
dt
14

dy
+ y = x,
dt
where x > 0.

Iy
Ix
and y .
x
I1
I1
d
dt
Iy
I1
Iy
Ix
+
=
I1
I1
dIy
+ Iy = Ix .
dt
14

To implement the time derivative, we introduce a log-compressed voltage state variable, Vy .
Using the chain rule, we can express the preceding equation as
Iy dVy
+ Iy = Ix
Vy dt
Ix
dVy
+1=
=
UT dt
Iy
Ic
Ix
= + 1 =
I
Iy

dVy
+ Iy = Ix
Iy
UT
dt
dVy
Ix
=
C
+1 =
CU
dt
Iy
T
Ic
1/I
I Ix
= I Ic =
.
Iy

Ip
14

Iy dVy
+ Iy = Ix
Vy dt
Ix
dVy
+1=
=
UT dt
Iy
Ic
Ix
= + 1 =
I
Iy

dVy
+ Iy = Ix
Iy
UT
dt
dVy
Ix
=
C
+1 =
CU
dt
Iy
T
Ic
1/I
I Ix
= I Ic =
.
Iy

Ip
14

Iy dVy
+ Iy = Ix
Vy dt
Ix
dVy
+1=
=
UT dt
Iy
Ic
Ix
= + 1 =
I
Iy

dVy
+ Iy = Ix
Iy
UT
dt
dVy
Ix
=
C
+1 =
CU
dt
Iy
T
Ic
1/I
I Ix
= I Ic =
.
Iy

Ip
14

Iy dVy
+ Iy = Ix
Vy dt
Ix
dVy
+1=
=
UT dt
Iy
Ic
Ix
= + 1 =
I
Iy

dVy
+ Iy = Ix
Iy
UT
dt
dVy
Ix
=
C
+1 =
CU
dt
Iy
T
Ic
1/I
I Ix
= I Ic =
.
Iy

Ip
14

Iy dVy
+ Iy = Ix
Vy dt
Ix
dVy
+1=
=
UT dt
Iy
Ic
Ix
= + 1 =
I
Iy

dVy
+ Iy = Ix
Iy
UT
dt
dVy
Ix
=
C
+1 =
CU
dt
Iy
T
Ic
1/I
I Ix
= I Ic =
.
Iy

Ip
14

Iy dVy
+ Iy = Ix
Vy dt
Ix
dVy
+1=
=
UT dt
Iy
Ic
Ix
= + 1 =
I
Iy

dVy
+ Iy = Ix
Iy
UT
dt
dVy
Ix
=
C
+1 =
CU
dt
Iy
T
Ic
1/I
I Ix
= I Ic =
.
Iy

Ip
14

Iy dVy
+ Iy = Ix
Vy dt
Ix
dVy
+1=
=
UT dt
Iy
Ic
Ix
= + 1 =
I
Iy

dVy
+ Iy = Ix
Iy
UT
dt
dVy
Ix
=
C
+1 =
CU
dt
Iy
T
Ic
1/I
I Ix
= I Ic =
.
Iy

Ip
14

Iy dVy
+ Iy = Ix
Vy dt
Ix
dVy
+1=
=
UT dt
Iy
Ic
Ix
= + 1 =
I
Iy

dVy
+ Iy = Ix
Iy
UT
dt
dVy
Ix
=
C
+1 =
CU
dt
Iy
T
Ic
1/I
I Ix
= I Ic =
.
Iy

Ip
14

TLP: IpIy = IxI
KCL: Ic + Ip = I
14

TLP: IpIy = IxI
Ix
V0
Ip
KCL: Ic + Ip = I
It
Iy
V0
14

TLP: IpIy = IxI
Ix
It
It
Ix
V0
KCL: Ic + Ip = I
Ip
Vy
Ic
C
It
Iy
V0
15
Dynamic Translinear Circuit Synthesis: RMS-DC Converter

Synthesize an RMS-to-DC converter described by
x = w2,
dy
+ y = x,
dt
and z =
y.
We can eliminate x and y from the system description by substituting

x=w ,
2
y=z ,
2
dz
dy
= 2z
and
dt
dt
into the linear ODE describing the low-pass lter, obtaining a rst-order nonlinear ODE
describing the system given by
dz
2 z + z 2 = w2.
dt
15

Synthesize an RMS-to-DC converter described by
x = w2,
dy
+ y = x,
dt
and z =
y.
We can eliminate x and y from the system description by substituting

x=w ,
2
y=z ,
2
dz
dy
= 2z
and
dt
dt
into the linear ODE describing the low-pass lter, obtaining a rst-order nonlinear ODE
describing the system given by
dz
2 z + z 2 = w2.
dt
15

Iw+ 1
(Vw V0 )/UT
w+
= 2 1+e
I1

Iw 1
(Vw V0 )/UT
w
= 2 1+e
I1
Iw
= w+ w
I1
(Vw V0)
w = sinh
UT
Iw
= w+ +w 1
I1
(Vw V0)
w = cosh
UT
w
w2 = (w) 1
2
I
Iw
Iw
Vw
Iw
I1
Iw
Iw
V0
Iw+
Iw+
15

The input signal, w, can be positive or negative. To remedy this situation, we adopt a sinh
representation for w and and dene an associated signal, w, as just described. Substituting
w2 = (w)2 1 into the nonlinear ODE, we obtain
dz
2
2 z + z 2 = (w) 1.
dt
Iw
w
I1
Iz
and z .
I1
Substituting these into the nonlinear ODE, we obtain

2 2
Iz d Iz
dIz
Iz
Iw
2
+
+ Iz2 = Iw2 I12.
=
1 = 2 Iz
I1 dt I1
I1
I1
dt
15

dz
2
2 z + z 2 = (w) 1.
dt
Iw
w
I1
Iz
and z .
I1

2 2
Iz d Iz
dIz
Iz
Iw
2
+
+ Iz2 = Iw2 I12.
=
1 = 2 Iz
I1 dt I1
I1
I1
dt
15

dz
2
2 z + z 2 = (w) 1.
dt
Iw
w
I1
Iz
and z .
I1

2 2
Iz d Iz
dIz
Iz
Iw
2
+
+ Iz2 = Iw2 I12.
=
1 = 2 Iz
I1 dt I1
I1
I1
dt
15

dz
2
2 z + z 2 = (w) 1.
dt
Iw
w
I1
Iz
and z .
I1

2 2
Iz d Iz
dIz
Iz
Iw
2
+
+ Iz2 = Iw2 I12.
=
1 = 2 Iz
I1 dt I1
I1
I1
dt
15

To implement the time derivative, we introduce a log-compressed voltage state variable, Vz .
Iz dVz
+ Iz2 = Iw2 I12
2 Iz
Vz dt

=
Iw2 I12
2w dVz
+1= 2 2
=
UT dt
Iz
Iz
Iw2 I12
Ic
= + 1 = 2 2
I
Iz
Iz
2 Iz
Iz
UT
dVz
+ Iz2 = Iw2 I12
dt
Iw2 I12
2
dVz
C
+1 = 2 2
Iz
Iz
CU
T dt
Ic
1/I
I Iw2 I I12
I Ic = 2 2 .
I
Iz
z
Ip
Iq
15

Iz dVz
+ Iz2 = Iw2 I12
2 Iz
Vz dt

=
Iw2 I12
2w dVz
+1= 2 2
=
UT dt
Iz
Iz
Iw2 I12
Ic
= + 1 = 2 2
I
Iz
Iz
2 Iz
Iz
UT
dVz
+ Iz2 = Iw2 I12
dt
Iw2 I12
2
dVz
C
+1 = 2 2
Iz
Iz
CU
T dt
Ic
1/I
I Iw2 I I12
I Ic = 2 2 .
I
Iz
z
Ip
Iq
15

Iz dVz
+ Iz2 = Iw2 I12
2 Iz
Vz dt

=
Iw2 I12
2w dVz
+1= 2 2
=
UT dt
Iz
Iz
Iw2 I12
Ic
= + 1 = 2 2
I
Iz
Iz
2 Iz
Iz
UT
dVz
+ Iz2 = Iw2 I12
dt
Iw2 I12
2
dVz
C
+1 = 2 2
Iz
Iz
CU
T dt
Ic
1/I
I Iw2 I I12
I Ic = 2 2 .
I
Iz
z
Ip
Iq
15

Iz dVz
+ Iz2 = Iw2 I12
2 Iz
Vz dt

=
Iw2 I12
2w dVz
+1= 2 2
=
UT dt
Iz
Iz
Iw2 I12
Ic
= + 1 = 2 2
I
Iz
Iz
2 Iz
Iz
UT
dVz
+ Iz2 = Iw2 I12
dt
Iw2 I12
2
dVz
C
+1 = 2 2
Iz
Iz
CU
T dt
Ic
1/I
I Iw2 I I12
I Ic = 2 2 .
I
Iz
z
Ip
Iq
15

Iz dVz
+ Iz2 = Iw2 I12
2 Iz
Vz dt

=
Iw2 I12
2w dVz
+1= 2 2
=
UT dt
Iz
Iz
Iw2 I12
Ic
= + 1 = 2 2
I
Iz
Iz
2 Iz
Iz
UT
dVz
+ Iz2 = Iw2 I12
dt
Iw2 I12
2
dVz
C
+1 = 2 2
Iz
Iz
CU
T dt
Ic
1/I
I Iw2 I I12
I Ic = 2 2 .
I
Iz
z
Ip
Iq
15

Iz dVz
+ Iz2 = Iw2 I12
2 Iz
Vz dt

=
Iw2 I12
2w dVz
+1= 2 2
=
UT dt
Iz
Iz
Iw2 I12
Ic
= + 1 = 2 2
I
Iz
Iz
2 Iz
Iz
UT
dVz
+ Iz2 = Iw2 I12
dt
Iw2 I12
2
dVz
C
+1 = 2 2
Iz
Iz
CU
T dt
Ic
1/I
I Iw2 I I12
I Ic = 2 2 .
I
Iz
z
Ip
Iq
15

Iz dVz
+ Iz2 = Iw2 I12
2 Iz
Vz dt

=
Iw2 I12
2w dVz
+1= 2 2
=
UT dt
Iz
Iz
Iw2 I12
Ic
= + 1 = 2 2
I
Iz
Iz
2 Iz
Iz
UT
dVz
+ Iz2 = Iw2 I12
dt
Iw2 I12
2
dVz
C
+1 = 2 2
Iz
Iz
CU
T dt
Ic
1/I
I Iw2 I I12
I Ic = 2 2 .
I
Iz
z
Ip
Iq
15

Iz dVz
+ Iz2 = Iw2 I12
2 Iz
Vz dt

=
Iw2 I12
2w dVz
+1= 2 2
=
UT dt
Iz
Iz
Iw2 I12
Ic
= + 1 = 2 2
I
Iz
Iz
2 Iz
Iz
UT
dVz
+ Iz2 = Iw2 I12
dt
Iw2 I12
2
dVz
C
+1 = 2 2
Iz
Iz
CU
T dt
Ic
1/I
I Iw2 I I12
I Ic = 2 2 .
I
Iz
z
Ip
Iq
15

TLP: IpIz2 = I Iw2
Iq Iz2 = I I12
KCL: Ic +Ip = I +Iq
15

TLP: IpIz2 = I Iw2
Iq Iz2 = I I12
Iw
V0
Ip
KCL: Ic +Ip = I +Iq

Iw
Iz
It
Iz
V0
15

TLP: IpIz2 = I Iw2
Iq Iz2 = I I12
Iw
Ip
KCL: Ic +Ip = I +Iq

Iw
Iz
It
Iz
V0
V0
I1
V0
Iq
I1
Iz
It
Iz
V0
15

TLP: IpIz2 = I Iw2
Iq Iz2 = I I12
Iw
Ip
KCL: Ic +Ip = I +Iq

Iw
V0
It
Iz
V0
I1
V0
Iz
Iq
I1
15

TLP: IpIz2 = I Iw2
Iq Iz2 = I I12
I1
Iw
Ip
KCL: Ic +Ip = I +Iq
Iw
V0
Iz
It
Iz
V0
Iq
I1
15

TLP: IpIz2 = I Iw2
Iq Iz2 = I I12
KCL: Ic +Ip = I +Iq
Iz
Iw
I1
I1
Iw
Iq
Iw
Iz
It
Iq
It
Ip
Iw
V0
Iz
It
Vz
Ic
C
Iq
I1
I1
Iz
V0
15

TLP: IpIz2 = I Iw2
Iq Iz2 = I I12
KCL: Ic +Ip = I +Iq
Iz
Iw
I1
I1
Iw
Iq
Iw
Iz
It
Iq
It
Ip
Iw
V0
Iz
It
Vz
Ic
C
Iq
I1
I1
Iz
Iz
V0

Static and Dynamic Translinear Circuits

Uploaded by

Copyright:

Available Formats

You might also like

Static and Dynamic Translinear Circuits

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Static and Dynamic Translinear Circuits

Uploaded by

Copyright:

Available Formats

Static and Dynamic Translinear Circuits

Translinear Circuits: Whats in a Name?

Translinear Circuits: Whats in a Name?

Translinear Circuits: Whats in a Name?

Gummel Plot of a Forward-Active Bipolar Transistor

Translinearity of the Forward-Active Bipolar Transistor

The Translinear Principle

Why Translinear Circuits?

Why Translinear Circuits?

Why Translinear Circuits?

Why Translinear Circuits?

Why Translinear Circuits?

Why Translinear Circuits?

Simple EKV Model of the Saturated nMOS Transistor

Isat = SIs log 1 + e((VGVT0)VS)/2UT

((VG VT0 )VS )/UT

Saturation Current of an nMOS Transistor

Isat = SIs ek(VG VT0)/UT

Translinearity of the Saturated nMOS Transistor

Weak-Inversion MOS Translinear Principle

TLP: I1I2 = I3I4

TLP: I1I3 = I2I4

Static Translinear Circuits: Squaring/Reciprocal

Static Translinear Circuits: Squaring/Reciprocal

Static Translinear Circuits: Squaring/Reciprocal

Static Translinear Circuit Synthesis: Pythagorator

where x > 0 and y > 0.

We represent each signal as a ratio of a signal current to the unit current:

We substitute these into the original equation and rearrange to obtain

Ir2 = Ix2 + Iy2

Static Translinear Circuit Synthesis: Pythagorator

where x > 0 and y > 0.

We represent each signal as a ratio of a signal current to the unit current:

We substitute these into the original equation and rearrange to obtain

Ir2 = Ix2 + Iy2

Static Translinear Circuit Synthesis: Pythagorator

where x > 0 and y > 0.

We represent each signal as a ratio of a signal current to the unit current:

We substitute these into the original equation and rearrange to obtain

Ir2 = Ix2 + Iy2

Static Translinear Circuit Synthesis: Pythagorator

where x > 0 and y > 0.

We represent each signal as a ratio of a signal current to the unit current:

We substitute these into the original equation and rearrange to obtain

Ir2 = Ix2 + Iy2

Static Translinear Circuit Synthesis: Pythagorator

where x > 0 and y > 0.

We represent each signal as a ratio of a signal current to the unit current:

We substitute these into the original equation and rearrange to obtain

Ir2 = Ix2 + Iy2

Static Translinear Circuit Synthesis: Pythagorator

where x > 0 and y > 0.

We represent each signal as a ratio of a signal current to the unit current:

We substitute these into the original equation and rearrange to obtain

Ir2 = Ix2 + Iy2

Static Translinear Circuit Synthesis: Pythagorator

KCL: Ir = Ir1 +Ir2

Static Translinear Circuit Synthesis: Pythagorator