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UChip PIC16F72 Based Relay TIMER Board Circuit
UChip PIC16F72 Based Relay TIMER Board Circuit
UChip PIC16F72 Based Relay TIMER Board Circuit
1
2
3
JP6
JST3
VDD
R14
RA5
1K
MCLR
JP3
JP1
Vin
3
2
1
VDD
1
Q2
2
4.7K
BUZ 3
+ C5
RS (LCD) 4
47uF/63V
En (LCD) 5
6
RA5
7
GND 8
OSC1 9
OSC2 10
Q8
11
X1
Q9
12
XTAL
Q7
13
14
P3
CPU3/3.96
C
JP2
C8
RB7
RB6
GND
VDD
MCLR
5
4
3
2
1
33pF
Vin
RELAY8
RELAY9
RELAY1
RELAY2
U?
R4
C9
MCLR/VPP
RB7/PGD
RA0
RB6/PGC
RA1
RB5
RA2
RB4
RA3
RB3
RA4
RB2
RA5
RB1
PIC16F72
GND
RB0
OSC1
VDD
OSC2
GND
RC0
RC7
RC1
RC6
RC2
RC5
RC3
RC4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7
RB6
Q4
Q5
D7 (LCD)
D6 (LCD)
D5 (LCD)
D4 (LCD)
VDD
GND
Q1
Q6
P1
P2
1
2
3
4
5
CPU5/5.96
C
C7
100nF
+ C6
10uF/63V
JP7
Vin
RELAY4
RELAY5
RELAY6
RELAY7
JST5
33pF
1
2
3
4
5
CPU5/5.96
J?
GND
P1
P2
P3
VDD
220K
2.2K
2.2K
R13
R9
R7
R6
CON4
D1,2,3,4,4,5,6,7,8
1N4007
VDD
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BUZ
Vin
2.7K
- (LCD)
+ (LCD)
D7 (LCD)
D6 (LCD)
D5 (LCD)
D4 (LCD)
D3 (LCD)
D2 (LCD)
D1 (LCD)
D0 (LCD)
En (LCD)
R/W
RS (LCD)
CONTRAST
VDD
GND
4
3
2
1
Q1
JP5 REL16
Q1,2,4,5,6,7,8,9
BD139
R3,2,5,10,11,12,15,16
2.2K
5V
Q3
R8
BUZ
470E
NPN
A
Title
Size
Number
Revision
B
Date:
File:
1
8-Oct-2016
Sheet of
D:\Water Level Complete\Circuits\FINAL CIRCUIT\WATER
Drawn By:
LEVEL CIRCUIT.ddb
6