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2016 ch3-CMOS Technology PDF
2016 ch3-CMOS Technology PDF
2016 ch3-CMOS Technology PDF
CMOS
Technology
1. CMOS Fabrication
2. Layout Design Rules
3. CMOS gate design
3: CMOS Technology
1. CMOS Fabrication
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process
3: CMOS Technology
4th Ed.
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
3: CMOS Technology
4th Ed.
3: CMOS Technology
4th Ed.
GND
VDD
nMOS transistor
pMOS transistor
well tap
substrate tap
3: CMOS Technology
4th Ed.
3: CMOS Technology
4th Ed.
Fabrication
Chips are built in huge factories called fabs
Contain clean rooms as large as football fields
Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
3: CMOS Technology
4th Ed.
Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
p substrate
3: CMOS Technology
4th Ed.
Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
3: CMOS Technology
4th Ed.
Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
Photoresist
SiO2
p substrate
3: CMOS Technology
4th Ed.
Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
Photoresist
SiO2
p substrate
3: CMOS Technology
4th Ed.
Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
3: CMOS Technology
4th Ed.
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesnt melt in next step
SiO2
p substrate
3: CMOS Technology
4th Ed.
n-well
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2
n well
3: CMOS Technology
4th Ed.
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
n well
p substrate
3: CMOS Technology
4th Ed.
Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
3: CMOS Technology
4th Ed.
Polysilicon Patterning
Use same lithography process to pattern polysilicon
3: CMOS Technology
4th Ed.
Self-Aligned Process
Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contact
3: CMOS Technology
4th Ed.
N-diffusion
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesnt melt during later processing
3: CMOS Technology
4th Ed.
N-diffusion cont.
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
3: CMOS Technology
4th Ed.
10
N-diffusion cont.
Strip off oxide to complete patterning step
3: CMOS Technology
4th Ed.
P-Diffusion
Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
3: CMOS Technology
4th Ed.
11
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contact
3: CMOS Technology
4th Ed.
Metalization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
M e ta l
3: CMOS Technology
4th Ed.
12
4th Ed.
3: CMOS Technology
4th Ed.
13
Inverter Layout
Transistor dimensions specified as Width / Length
Minimum size is 4 / 2, sometimes called 1 unit
In f = 0.6 m process, this is 1.2 m wide, 0.6 m
long
3: CMOS Technology
4th Ed.
Review
1.
2.
3.
4.
5.
6.
7.
8.
3: CMOS Technology
4th Ed.
14
A
B
C
D
3: CMOS Technology
4th Ed.
Complementary CMOS
Complementary CMOS logic gates
nMOS pull-down network
pMOS pull-up network
inputs
a.k.a. static CMOS
Pull-up OFF
Pull-up ON
Pull-down ON
X (crowbar)
3: CMOS Technology
pMOS
pull-up
network
output
nMOS
pull-down
network
4th Ed.
15
nMOS: 1 = ON
pMOS: 0 = ON
Series: both must be ON
Parallel: either can be ON
g2
(a)
OFF
OFF
ON
(c)
a
g1
(d)
ON
OFF
OFF
OFF
a
0
a
1
a
0
OFF
ON
ON
ON
a
0
a
g2
OFF
a
g2
0
b
g1
(b)
g2
a
g1
0
b
3: CMOS Technology
g1
a
1
a
0
ON
ON
ON
OFF
4th Ed.
Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
Series nMOS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Y
Requires parallel pMOS
A
3: CMOS Technology
4th Ed.
16
Compound Gates
Compound gates can do any inverting function
Ex: Y = A B + C D (AND-AND-OR-INVERT, AOI22)
A
(a)
(b)
B C
(c)
(d)
A
B
C
D
(f)
(e)
3: CMOS Technology
4th Ed.
Example: O3AI
Y = (A+ B +C) D
A
B
C
D
A
3: CMOS Technology
4th Ed.
17
Signal Strength
Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
But degraded or weak 1
pMOS pass strong 1
But degraded or weak 0
Thus nMOS are best for pull-down network
3: CMOS Technology
4th Ed.
Pass Transistors
Transistors can be used as switches
3: CMOS Technology
4th Ed.
18
Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
Input
g
a
b
gb
g = 1, gb = 0
0
strong 0
g = 1, gb = 0
a
b
g = 1, gb = 0
strong 1
1
g
a
gb
b
gb
3: CMOS Technology
Output
g = 0, gb = 1
a
b
b
gb
4th Ed.
Tristates
Tristate buffer produces Z when not enabled
EN
EN
Y
A
EN
A
EN
3: CMOS Technology
4th Ed.
19
Nonrestoring Tristate
Transmission gate acts as tristate buffer
Only two transistors
But nonrestoring
Noise on A is passed on to Y
EN
A
Y
EN
3: CMOS Technology
4th Ed.
Tristate Inverter
Tristate inverter produces restored output
Violates conduction complement rule
Because we want a Z output
A
A
EN
EN = 0
Y = 'Z'
EN = 1
Y=A
EN
3: CMOS Technology
4th Ed.
20
Multiplexers
2:1 multiplexer chooses between two inputs
D1
D0
3: CMOS Technology
D0
D1
4th Ed.
D1
S
D0
D1
S
D0
4
2
3: CMOS Technology
4th Ed.
21
S
D0
Y
S
D1
S
3: CMOS Technology
4th Ed.
Inverting Mux
Inverting multiplexer
Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
Noninverting multiplexer adds an inverter
D0
D1
3: CMOS Technology
D0
D1
S
Y
D0
D1
4th Ed.
22
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects
Two levels of 2:1 muxes
Or four tristates
3: CMOS Technology
4th Ed.
D Latch
When CLK = 1, latch is transparent
D flows through to Q like a buffer
When CLK = 0, the latch is opaque
Q holds its old value independent of D
a.k.a. transparent latch or level-sensitive latch
Latch
CLK
3: CMOS Technology
CLK
D
Q
Q
4th Ed.
23
D Latch Design
Multiplexer chooses D or old Q
CLK
D
CLK
1
0
Q
CLK
CLK
CLK
3: CMOS Technology
4th Ed.
D Latch Operation
Q
D
CLK = 1
Q
D
CLK = 0
CLK
D
Q
3: CMOS Technology
4th Ed.
24
D Flip-flop
When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop
CLK
CLK
Flop
Q
Q
3: CMOS Technology
4th Ed.
D Flip-flop Design
Built from master and slave D latches
CLK
CLK
CLK
D
CLK
QM
Latch
Latch
CLK
D
QM
3: CMOS Technology
CLK
Q
CLK
CLK
Q
CLK
CLK
4th Ed.
25
D Flip-flop Operation
QM
CLK = 0
QM
CLK = 1
CLK
D
Q
3: CMOS Technology
4th Ed.
Race Condition
Back-to-back flops can malfunction from clock skew
Second flip-flop fires late
Sees first flip-flop change and captures its result
Called hold-time failure or race condition
CLK1
CLK2
Q1
3: CMOS Technology
Flop
Flop
CLK1
CLK2
Q2
Q1
Q2
4th Ed.
26
Nonoverlapping Clocks
Nonoverlapping clocks can prevent races
As long as nonoverlap exceeds clock skew
We will use them in this class for safe design
Industry manages skew more carefully instead
2
1
QM
D
2
Q
1
1
2
3: CMOS Technology
4th Ed.
Gate Layout
Layout can be very time consuming
Design gates to fit together nicely
Build a library of standard cells
Standard cell design methodology
VDD and GND should abut (standard height)
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts
3: CMOS Technology
4th Ed.
27
Example: Inverter
3: CMOS Technology
4th Ed.
Example: NAND3
3: CMOS Technology
4th Ed.
28
Stick Diagrams
Stick diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers
3: CMOS Technology
4th Ed.
Wiring Tracks
A wiring track is the space required for a wire
4 width, 4 spacing from neighbor = 8 pitch
Transistors also consume one wiring track
3: CMOS Technology
4th Ed.
29
Well spacing
Wells must surround transistors by 6
Implies 12 between opposite transistor flavors
Leaves room for one wire track
3: CMOS Technology
4th Ed.
Area Estimation
Estimate area by counting wiring tracks
Multiply by 8 to express in
40
32
3: CMOS Technology
4th Ed.
30
Example: O3AI
Sketch a stick diagram for O3AI and estimate area
Y = (A+ B +C) D
3: CMOS Technology
4th Ed.
Review
3: CMOS Technology
4th Ed.
31