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Palmisano - 16 - AICSP - Design Procedure For Two-Stage CMOS Transconductance Operational
Palmisano - 16 - AICSP - Design Procedure For Two-Stage CMOS Transconductance Operational
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3 authors, including:
Gaetano Palumbo
Salvatore Pennisi
University of Catania
University of Catania
SEE PROFILE
SEE PROFILE
Received April 1, 1999; Revised July 24, 2000; Accepted September 12, 2000
Abstract. This paper deals with well-defined design criteria for two-stage CMOS transconductance operational
amplifiers. A novel and simple design procedure is presented, which allows electrical parameters to be univocally
related to the value of each circuit element and biasing value. Unlike previous methods, the proposed one is
suited for a pencil-and-paper design and yields accurate performance optimization without introducing unnecessary
circuit constraints. Bandwidth optimization strategies are also discussed. SPICE simulations based on the proposed
procedures are given which closely agree the expected results.
Key Words: CMOS, amplifiers, OTAs, analog design, frequency compensation
I.
Introduction
tios, bias current and compensation capacitor) to be univocally related to the required amplifier performance.
In such a way, OTA parameters are optimized with a
straightforward pencil-and-paper analysis using accurate design equations.
The design procedure is based on the following main
parameters: noise, phase margin (M ), gain-bandwidth
product ( f GBW ), load capacitance (C L ), slew rate (SR),
input common mode range (CMR), output swing (OS),
and input offset voltage (due to systematic errors).
When M is not given it is set to minimize settling
time [10].
Important parameters such as dc gain, CMRR and
PSRR, will not be used during the design steps since
they depend on the output resistance of MOS transistors that is not easily modeled for a hand analysis. Such
parameters greatly depend on the amplifier topology
(typical dc gain and CMRR in a two-stage OTA are in
the ranges of 6080 dB and 7090 dB, respectively)
and can only be predicted by simulation using accurate
transistor models. Of course, there are electrical pameters which can be improved with appropriate circuit
arrangements. For instance, a high drive capability can
be achieved by employing class AB instead of class A
topologies [1113].
The proposed procedure in its general form is described in Section II. We will use the Miller
180
DD
M3
IB
M4
M5
A
IN
M1
M2
RC
IN +
CC
OUT
CL
M8
M6
M7
V
SS
CC =
II.
A.
Description
16 kT
3 Sn ( f )
(2)
(3)
2I D1,2
CC
(4a)
SREXT =
I D8 2I D1,2
CL
(4b)
The procedure starts from the noise requirement. Neglecting flicker noise which contributes at low frequencies, the input noise voltage spectral density of the OTA
in Fig. 1 is given by
gm3,4
2 1
Sn ( f ) = 2 4kT
1+
(1)
3 gm1,2
gm1,2
1 gm1,2
2 f GBW
SR
CC
2
(5a)
CL
I D8 = SR(CC + C L ) = 2 1 +
I D1,2
CC
(5b)
Remembering that gm = 2 K n,p (W/L)I D where
(K n,p = n,p Cox /2), from equation (5a) the aspect ratio
of transistors M1 and M2 is
2
gm1,2
W
=
(6)
L 1,2
4K N I D1,2
For a two-stage amplifier in which the frequency behavior can well be assumed with a single non-dominant
pole (i.e., a single second pole), the phase margin is expressed by
M = 90 arctan
f GBW
f SP
(7)
(9)
(10)
(11)
f SP
f GBW
(12)
(14)
(15)
181
(17a)
(17b)
VGS1,2 =
|VDSsat3,4,5 |
2
2
|VTP | + VTN
(18a)
CMR = VDS7 VDSsat7 =
VDD
VGS1,2 VDSsat7,8
2
VDD
(18b)
VDSsat1,2 VTN VDSsat7
2
Hence, in order to satisfy both the two set of conditions
we have to chose
=
(19a)
(19b)
182
Are Set
by
Design
Parameters
Noise
gm1,2
fGBW
CC
(W/L)1,2
SRINT
ID1,2
ID7
SREXT
ID8
ID5
M
gm5
(W/L)5
Systematic offset
(W/L)3,4
OS
VDSsat7
(W/L)7
CMR
VDSsat8
(W/L)8
IB
(W/L)6
(W/L)6
I D7
(W/L)7
(20)
B.
Simulations
Parameters
Target
Simulated
DC Gain
f GBW
M
Slew rate
Input white noise
Systematic offset
OS
CMR
CMRR
>60 dB
10 MHz
60
10 V/s
10 nV/ Hz
0V
2 V
1.2 V
>70 dB
67 dB
12 MHz
59
11.5 V/s
13 nV/ Hz
0.1 mV
2V
1.2 V
78 dB
In order to evaluate the accuracy of proposed procedure, the two-stage OTA in Fig. 1 has been designed
by using a standard 1.2-m CMOS technology which
has the main following process parameters:
K N = 30 A/V2 ,
K P = 10 A/V2 ,
VT N = VT P = 0.75 V.
The target specification is reported in the first column of Table 2. The requirement in terms of dc gain
and CMRR are set on the base of the topology rather
than on the design approach, as mentioned before. Furthermore, a load capacitor, C L , equal to 4 pF has been
assumed.
Using the design procedure outlined in Section II,
we have determined the values of transistor aspect ra-
Parameters
Value
Unit
IB
M1 M2
M3 M4
M5
M6
M7
M8
CC
RC
18
28/1.2
17/1.2
75/1.2
7/1.2
14/1.2
33/1.2
3.5
2.3
m/m
pF
k
183
III.
a better frequency response. The original of these techniques was applied to NMOS opamps [15] and then to
CMOS opamps [16]. It breaks the forward path through
the compensation capacitor by introducing a voltage
buffer in the compensation branch. Another solution
uses a current buffer to break this forward path [17].
Optimized versions of these techniques, as well as of
that employing the nulling resistor, were discussed in
[1820].
In this section we will give procedures which optimize the gain-bandwidth product while keeping unchanged as much as possible all the remaining electrical
parameters previously set.
A.
gm5
1
,
2 (gm5 RC 1) CC
184
1
2 RC R Co1
K =
(21)
where CC R and RC R are the new compensation capacitor and resistor, respectively.
Once this compensation is achieved, the new second
pole is [18]
f SP =
(22)
CC R
gm1,2 RC R Co1
(23)
gm1,2
Co1 C L
(24a)
=K
gm5
RC R
1
gm5 C L
1+ 1+4
=
2gm5
K g m1,2 Co1
CL
=
K g m1,2 gm5 Co1
(24b)
Equation (24a) shows that the compensation capacitor is now approximately proportional to the geometric media of Co1 and C L and hence is lower than that
in equation (13). Therefore, the optimized approach
with nulling resistor provides a higher gain-bandwidth
product.
B.
gm9V CC V
gm1,2 Co1
(27)
Since the actual value of Co1
is unknown (it depends
on the aspect ratio of transistor M9V that has to be still
computed), evaluation of the exact solution for gm9V
and CC V needs an iterative method. However, to provide a high second pole a small geometrical dimension
for M9V has to be set. Hence, we can neglect Cgs9V
with respect to Co1 and solve equations (25) and (27)
for CC V and gm9V . It results
gm1,2
CC V = K
Co1 C L
(28a)
gm5
Co1
gm9V
(28b)
= K gm5 gm1,2
CL
C.
DD
DD
and
I BC
CCC
A
M9V
OUT
M9C
bias
OUT
C CV
C
I BC CC
I BV
V
SS
(a)
SS
(b)
Fig. 4. Voltage buffer (a) and current buffer (b) compensation blocks.
185
gm12
gm5
2K 1 1
+
2+K
2
(29a)
C L Co1
(29b)
Assuming similar electrical parameters, phase margin and load capacitance, capacitance CCC is slightly
lower than capacitance CC V and hence the gainbandwidth product in this last case is the highest among
the optimized approaches.
Moreover, the optimization using current buffer
preserves the original output swing. Finally, a better
implementation of this approach can be achieved by
186
D.
Final Remarks
2 f sp f d2
K f d (2 f d + f sp )
(30)
E.
f GBW
CC
f NGBW
(31)
Simulations
Value
Unit
IBV
M9V
IBC
M9C
18
7/1.2
36
50/1.2
A
m/m
A
m/m
Expected
Simulateda
Simulatedb
f GBW
M
(MHz) (deg.)
f GBW
M
(MHz) (deg.)
f GBW
M
(MHz) (deg.)
Resistance
Voltage buffer
Current buffer
32
39
41
41
38
47.5
38
36.5
44
63
63
63
51
48
42
57.5
54
56
a Without
b Taking
187
Fig. 5. Frequency responses of the loop-gain for the optimized compensation techniques: ( ) nulling resistor, () voltage buffer and () current
buffer.
IV.
Conclusions
188
189
papers on referred international journals and conferences. He is serving as an Associated Editor of the
IEEE Transaction on Circuits and Systems part I. Prof.
Palumbo is an IEEE Senior Member.