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College of Engineering: Submitted by
College of Engineering: Submitted by
College of Engineering: Submitted by
College of Engineering
Tibanga, 9200 Iligan City, P.O. Box No.5644 Tel. Nos. (063) 221-4050 Loc.130
Direct line (063) 2351E-mail:fbalagao@yahoo.com
Homepage: http://www.msuiit.edu.ph/coe
Submitted by:
TOLEDO, John Xavier P.
Submitted to:
Prof. Jefrey C. Pasco
March 2016
ABSTRACT
d. To be able to pass the test analyses for lay-out inverter using DRC and
LVS.
RESULTS and DISCUSSIONS
a. Pre-Simulation
waveform of the input pulse with 4.71ns rise time, 3.73ns fall time, 44ns
pulse width and 99ns pulse width repetition.
b. Post-Simulation
connected to source voltage, vdd!. The guard ring for the PMOS is a N-active
via covering the whole PMOS and the PIMP layer is covering the diffusion
layer. The polysilicon gate layer is bonded together using Metal2 pins and
layer including the polysilicon layer of the NMOS and also, the connected
drain is bonded with the drain of the NMOS using Metal 2 pins and layer. For
the finalization of PMOS, the whole device is covered with minimum amount
of NWELL layer.
pins and layer are used to be connected to the drain of PMOS. The two
polysilicon gate layers are connected together using Metal 1, and another
Metal2 pins and layer are used to be routed in the poly gate of PMOS. To
cover up the device, a NIMP layer is used following the minimum distances to
other layers, and a P-active via is used as a guard ring while the source via is
connected to the guard ring using Metal1 layer and Metal1 pin as a ground,
gnd!. Using Metal 3 pin and layer, the routed poly gate is to be directed as
input voltage while the routed drain is to be directed as output voltage.
Figure 7. Waveform for Input and Output voltages for post-simulation in TT.
According to the graph above, the rise time from 0v to 1.8v is 4.4ns
and the fall time from 1.8v to 0v is 3.51ns using Typical-Typical (TT) setting
for both NMOS and PMOS transistors.
Figure 8. Waveform for Input and Output voltages for post-simulation in SS.
According to the graph above, the rise time from 0v to 1.8v is 5.14ns
and the fall time from 1.8v to 0v is 3.72ns using Slow-Slow (SS) setting for
both NMOS and PMOS transistors.
Figure 9. Waveform for Input and Output voltages for post-simulation in FF.
According to the graph above, the rise time from 0v to 1.8v is 4.28ns
and the fall time from 1.8v to 0v is 3.61ns using Fast-Fast (FF) setting for
both NMOS and PMOS transistors.
CONCLUSION
Two post-simulation processes have a lesser rise and fall times, namely
the TT and FF corner processes. The TT corner process has a 4.4ns and
3.51ns rise time and fall time, respectively and the FF corner process has a
4.28ns and 3.61ns rise time and fall time, simultaneously while the presimulation TT corner process, as a basis, has a 4.71ns and 3.73ns rise/fall
time so it can be concluded that the layout gives a better output voltage as
expected. As for the SS corner process, the 3.72ns fall time is better while
5.14ns is not a good rise time but taking it with considerations for the SS
process, it can be said that the layout process, as an overall, has a good
performance and can be concluded that, it has meet the desired output for
this laboratory activity.