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UVM Register
Use Models
Mark Glasser
Methodology Architect
DVT
October 2010
UVM Register
SystemVerilog/UVM facility for modeling

registers
Variety of use models

Single bus
Multiple bus
Hierarchy
Driven by Sequences
Your Initials, Presentation Title, Month Year
2010 Mentor Graphics Corp. Company Confidential
www.mentor.com
UVM RAL: Basic Flow
RAL
test
Maps:
APB:
A:
F[7:0]
X:
F[7:0]
addr
CVT
data
blk_APB_seq
ral.A.write
A
env
RAL
RAL
CVT
RTL BLK
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Infrastructure: The RAL Block

Usually Auto-generated
test
Human-Readable
RAL
Maps:
APB:
A:
F[7:0]
X:
F[7:0]
CVT
blk_APB_seq
class ral_block_B extends uvm_ral_block;
ral.A.write
rand ral_reg_R A;
RAL
rand ral_reg_R X;
uvm_ral_map APB;
env
RAL function void build();

virtual
this.A
= ral_reg_R::type_id::create("A");
CVT
this.X = ral_reg_R::type_id::create("X");
APB = add_map("APB", 1, uvm_ral::LITTLE_ENDIAN);
default_map = APB;
APB.add_reg(A, h0, uvm_ral::RW);
APB.add_reg(X, 'h10, uvm_ral::RW);
endfunction : build
endclass : ral_block_B
RTL BLK
Set default map

Set map for registers
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Step 1: The Converter
RAL
test
Maps:
APB:
class ral2apb_adapter extends uvm_ral_convert;

ùvm_object_utils(ral2apb_adapter)
A:
F[7:0]
CVT
F[7:0]
X:
virtual function uvm_sequence_item
ral2bus(uvm_ral_item
ral_item);
apb_item apb = apb_item::type_id::create("apb_item");
blk_APB_seq
apb.read = (ral_item.oper == uvm_ral::READ) ? 1 : 0;
ral.A.write
apb.addr = ral_item.addr;
RAL
apb.data = ral_item.data;
return apb;
endfunction
env
virtual
function void bus2ral(uvm_sequence_item bus_item,
RAL
uvm_ral_item ral_item);
apb_item apb;
CVT
if (!$cast(apb,bus_item)) begin
ùvm_fatal("NOT_APB_TYPE","Provided bus_item is the wrong type")
return;
end
ral_item.oper = apb.read ? uvm_ral::READ : uvm_ral::WRITE;
ral_item.addr = apb.addr;
ral_item.data = apb.data;
endfunction
RTL BLK
endclass
Not called directly

by user
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Step 2: The RAL Sequence
RAL
APB:
class blk_APB_test_seq extends uvm_ral_sequence;
ùvm_object_utils(blk_AXW_test_seq)
F[7:0]
A:
addr
ral_block_B ral;
CVT
data
F[7:0]
X:
test
function new(string name = "blk_AXW_test_seq");

super.new(name);
endfunction: new
blk_APB_seq
ral.A.write
RAL
env
Maps:
RAL
CVT
virtual task body();

uvm_ral::status_e status;
uvm_ral_data_t
data;
int n;
data[7:0] = $urandom();
ral.A.write(status, data, .parent(this));
write(ral.X, status, data);
ral.A.mirror(status, uvm_ral::VERB, .parent(this));
endtask
endclass
RTL BLK
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Step 3: The Environment
RAL
class blk_env extends uvm_env;
ùvm_component_utils(blk_env)
F[7:0]
A:
ral_block_B ral;
F[7:0]
X:
apb_agent
apb;
wsh_agent
wsh;
test
blk_APB_seq
ral.A.write
APB:
CVT
RAL
env
Maps:
RAL
CVT
virtual function void build();

any_driver#(apb_item)::type_id::set_type_override(
my_apb_driver::get_type());
apb =
apb_agent::type_id::create("apb_agent",this);
wsh =
wsh_agent::type_id::create("wsh_agent",this);
ral = ral_block_B::type_id::create("ral_blk_B");
ral.build();
endfunction: build
RTL
BLK
endclass
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Step 4: Pass Sequencer to RAL Block

class blk_env extends uvm_env;
ùvm_component_utils(blk_env)
ral_block_B
apb_agent
wsh_agent
ral;
apb;
wsh;
env
RAL
CVT

any_driver#(apb_item)::type_id::set_type_override(
my_apb_driver::get_type());
apb =
apb_agent::type_id::create("apb_agent",this);
wsh =
wsh_agent::type_id::create("wsh_agent",this);
ral = ral_block_B::type_id::create("ral_blk_B");
ral.build();
endfunction: build
virtual function void connect();
ral2apb_adapter ral2apb = new;
ral.APB.set_sequence(apb.sqr, ral2apb);
endfunction
endclass
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Step 5: The Test
RAL
APB:
class blk_test extends uvm_test;

ùvm_component_utils(blk_test)
test
F[7:0]
A:
blk_env env;
CVT
F[7:0]
X:
function void build();

env = blk_env::type_id::create("blk_env",this);
endfunction
blk_APB_seq
ral.A.write
RAL
env
Maps:
task run();
blk_APB_seq seq = blk_APB_seq::type_id::create("blk_APB_seq",this);
seq.ral = env.ral;
RAL
CVT
seq.start(null);
seq.wait_for_sequence_state(FINISHED);
global_stop_request();
endtask
endclass
RTL BLK
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Example: Vertical Reuse
RAL_SYS
RAL0
sys_test
sys_test_seq
blk_test_seq
ral.A.write
blk_test_seq
ral.A.write
RAL
Maps:
Maps:
APB:
APB:
CVT
A:
F[7:0]
X:
F[7:0]
CVT
RAL
RAL1
sys_env
Maps:
APB:
RAL
CVT
A:
F[7:0]
X:
F[7:0]
CVT
Different Base
Addresses
RTL BLK
RTL BLK
10
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Vertical Reuse: The RAL Block
RAL_SYS
RAL0
sys_test
sys_test_seq
blk_test_seq
ral.A.write
blk_test_seq
ral.A.write
Maps:
Maps:
APB:
CVT
RAL
A:
F[7:0]
X:
F[7:0]
CVT
RAL
class ral_sys_S extends uvm_ral_block;

ùvm_object_utils(ral_sys_S)
rand ral_block_B B[2];
RAL
sys_env
RAL1
Maps:
APB:

F[7:0]
A:
foreach (this.B[i])
begin
CVT
CVT
F[7:0]
X:
this.B[i] = ral_block_B::type_id::create($psprintf("B[%0d]",
i));
this.B[i].build();
Set up sub-blocks
this.register_child(this.B[i].default_map,
default_map, 'h100 + i*'h100);
end
endfunction : build
Set base address
endclass : ral_sys_S
RTL BLK
RTL BLK
Register as child blocks

11
APB:
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Vertical Reuse: The Environment
RAL_SYS
RAL0
sys_test
sys_test_seq
blk_test_seq
ral.A.write
blk_test_seq
ral.A.write
RAL
APB:
APB:
CVT
A:
F[7:0]
X:
F[7:0]
CVT
RAL
class sys_env extends uvm_env;
ùvm_component_utils(sys_env)
sys_env
RAL
CVT
RAL1
Maps:
APB:
ral_sys_S ral;
apb_agent apb;
F[7:0]
A:
CVT
F[7:0]
X:
super.build();
apb = apb_agent::type_id::create("apb_agent",this);
ral = ral_sys_S::type_id::create("ral_sys_S");
ral.build();
Set sequencer
endfunction: build
virtual function void connect();
RTL BLK
ral2apb_adapter ral2apb = new;
ral.set_sequence(apb.sqr,ral2apb);
RTL BLK endfunction
endclass: sys_env
12
Maps:
Maps:
for ral_block_S
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Vertical Reuse: The Test Sequence
RAL_SYS
RAL0
sys_test
sys_test_seq
blk_test_seq
ral.A.write
blk_test_seq
ral.A.write
RAL
Maps:
Maps:
APB:
APB:
CVT
A:
F[7:0]
X:
F[7:0]
CVT
RAL
sys_env
class sys_R_test_seq extends uvm_ral_sequence;

ùvm_object_utils(sys_R_test_seq)
ral_sys_S ral;
RAL1
Maps:
APB:
RAL

F[7:0]
A:
for (int i=0; i < 2; i++) begin
CVT
CVT
F[7:0]
fork begin
X:
blk_R_test_seq seq;
seq = blk_R_test_seq::type_id::create($sformatf("blk_seq%0d",i),
,get_full_name());
seq.ral = ral.B[i];
seq.start(null,this);
end join_none
RTL fork;
BLK
wait
Set sequencer pointers
end
endtask
RTL BLK
endclass
Start subsequences
13
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Vertical Reuse: The Test
RAL_SYS
RAL0
sys_test
sys_test_seq
blk_test_seq
ral.A.write
blk_test_seq
ral.A.write
RAL
RAL
sys_env
RAL
CVT
APB:
APB:
CVT
A:
F[7:0]
X:
class sys_R_test extends uvm_test;
ùvm_component_utils(sys_R_test)
sys_env env;
Maps:
Maps:
F[7:0]
RAL1
CVT
Maps:

APB:
apb_config apb_cfg = new;
apb_cfg.vif = $root.sys_top.apb0;
F[7:0]
A:
env = sys_env::type_id::create("sys_env",this);
CVT
set_config_object("sys_env.apb_agent.*","config",apb_cfg,0);
F[7:0]
X:
endfunction
task run();
sys_R_test_seq seq;
seq = sys_R_test_seq::type_id::create("sys_R_test_seq",this);
seq.ral = env.ral;
seq.start(null);
RTL BLK
Set RAL Block
global_stop_request();
endtask
RTL BLK
Start System-level sequence
endclass
14
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Example 3: Multiple Maps
sys_test
RAL0
blk_test_seq
ral.A.write
ral.W.write
A:
F[7:0]
X:
F[7:0]
Maps:
APB:
CVT
RAL
WSH:
sys_env
RAL
W
:
X:
CVT
F[7:0]
F[7:0]
CVT
RTL BLK
15
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Multiple Maps: The RAL Block
sys_test
class ral_block_B extends uvm_ral_block;

rand ral_reg_R A;
rand ral_reg_R X;
rand ral_reg_R W;
blk_test_seq
RAL0

this.A = ral_reg_R::type_id::create("A");
this.X = ral_reg_R::type_id::create("X");
this.W = ral_reg_R::type_id::create("W");
APB = RAL
add_map("APB", 1, uvm_ral::LITTLE_ENDIAN);
WSH = add_map("WSH", 1, uvm_ral::LITTLE_ENDIAN);
default_map
= APB;
CVT
APB.add_reg(A,
APB.add_reg(X,
WSH.add_reg(X,
WSH.add_reg(W,
endfunction
endclass
h0,
'h10,
'h0,
'h10,
uvm_ral::RW);
uvm_ral::RW);
uvm_ral::RW);
uvm_ral::RW);
APB:
Declare Maps
ral.A.write
uvm_ral_map APB;
ral.W.write
uvm_ral_map
RAL WSH;
sys_env
Maps:
A:
F[7:0]
X:
F[7:0]
CVT
WSH:
Add Maps
W
:
X:
F[7:0]
F[7:0]
CVT
Register shared in 2 maps
RTL BLK
16
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Multiple Maps: The Sequence
sys_test
class blk_test_seq extends uvm_ral_sequence;

ùvm_object_utils(blk_AXW_test_seq)
ral_block_B ral;
blk_test_seq
ral.A.write
ral.W.write
uvm_ral::status_e
status;
RAL
RAL0
A:
F[7:0]
X:
F[7:0]
uvm_ral_data_t
data;
fork
ral.A.write(status, 'h33, .parent(this));
ral.X.write(status, 'h44, .parent(this));
ral.W.write(status, 'hcc, .parent(this));
join RAL
Maps:
APB:
Parallel accesses via

default
maps
CVT
WSH:
sys_env
Explicit Map
W
F[7:0]
:
ral.X.write(status,
~ral.A.get(), .map(ral.APB), .parent(this));
CVT
CVT
F[7:0]
ral.X.mirror(status, uvm_ral::VERB, .map(ral.WSH), X:.parent(this));
endtask
endclass
One register accessed

via multiple maps
RTL BLK
17
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UVM RAL: Translation Sequence

test
RAL
env
blk_APB_seq
ral.A.write
A
Maps:
APB:
A:
F[7:0]
X:
F[7:0]
CVT
RAL
Start_item()
RAL item
Passthru Converter
get_next_item()
addr
CVT
data
Translation Sequence
RTL BLK
18
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UVM Register

SystemVerilog/UVM facility for modeling

Variety of use models

Your Initials, Presentation Title, Month Year

2010 Mentor Graphics Corp. Company Confidential

UVM RAL: Basic Flow

2010 Mentor Graphics Corp. Company Confidential

Infrastructure: The RAL Block

RAL function void build();

Set default map

2010 Mentor Graphics Corp. Company Confidential

Step 1: The Converter

class ral2apb_adapter extends uvm_ral_convert;

Not called directly

Step 2: The RAL Sequence

function new(string name = "blk_AXW_test_seq");

virtual task body();

2010 Mentor Graphics Corp. Company Confidential

Step 3: The Environment

virtual function void build();

2010 Mentor Graphics Corp. Company Confidential

Step 4: Pass Sequencer to RAL Block

virtual function void build();

2010 Mentor Graphics Corp. Company Confidential

Step 5: The Test

class blk_test extends uvm_test;

function void build();

2010 Mentor Graphics Corp. Company Confidential

Example: Vertical Reuse

2010 Mentor Graphics Corp. Company Confidential

Vertical Reuse: The RAL Block

class ral_sys_S extends uvm_ral_block;

function void build();

Register as child blocks

2010 Mentor Graphics Corp. Company Confidential

Vertical Reuse: The Environment

2010 Mentor Graphics Corp. Company Confidential

Vertical Reuse: The Test Sequence

class sys_R_test_seq extends uvm_ral_sequence;

virtual task body();

2010 Mentor Graphics Corp. Company Confidential

Vertical Reuse: The Test

function void build();

2010 Mentor Graphics Corp. Company Confidential

Example 3: Multiple Maps

2010 Mentor Graphics Corp. Company Confidential

Multiple Maps: The RAL Block

class ral_block_B extends uvm_ral_block;

virtual function void build();

Register shared in 2 maps

2010 Mentor Graphics Corp. Company Confidential

Multiple Maps: The Sequence

class blk_test_seq extends uvm_ral_sequence;

Parallel accesses via

One register accessed

2010 Mentor Graphics Corp. Company Confidential

UVM RAL: Translation Sequence

2010 Mentor Graphics Corp. Company Confidential

Your Initials, Presentation Title, Month Year