The R-S flip flop

Lecture 7:

S 1

Flip-Flops

R0

September 2001

Computer Hardware Lecture 7 Slide1

September 2001

Non determinism

R
0
1
0
1

P
1
1
0
?

Q
1
0
1
?

Computer Hardware Lecture 7 Slide2

The nature of the non-determinism

For input 1,1 we can only compute the output if we

know what is was at the previous time interval
S

S
0
0
1
1

S
1
1
1
1

R
1
1
1
1

Pp
0
0
1
1

Qp
0
1
0
1

P
1
0
1
0

Q
1
1
0
0

Unstable
Stable
Stable
Unstable

Theoretically the circuit could flip between the two

unstable states, oscillating indefinitely.
In practice the two gates will not have identical time
delays, so one will change before the other and the
circuit will fall into a stable state.
We do not know what that stable state is.

September 2001

Computer Hardware Lecture 7 Slide3

September 2001

Non determinism when the circuit is switched on

The flip flop and memory

The R-S flip flop can be looked upon as a very simple
memory.

Logic Level
S

It has two states which can be thought of as Q=1 and

Q=0, or to put it another way it is a one bit memory.

R
Q

Computer Hardware Lecture 7 Slide4

The inputs are labelled S for set and R for reset.

?
Time

September 2001

Computer Hardware Lecture 7 Slide5

September 2001

Computer Hardware Lecture 7 Slide6

Sequential Circuits

The D-Type latch

Notice that we can only describe the behaviour of the

R-S if we know the time sequence of the inputs. For
this reason it is referred to as a sequential circuit.
In all practical cases we shall avoid using S=R=0, and
thus it will always be the case that P=Q

The set-reset mechanism of the R-S flip flop is not

very convenient.
It would be much better if a memory circuit could be
set to one or zero depending on its input.
This is the purpose of the D-type latch.

The input S=R=1 ensures that the output cannot

change
September 2001

Computer Hardware Lecture 7 Slide7

September 2001

The D type latch, open

Computer Hardware Lecture 7 Slide8

The D type latch, closed

Latch
D

Latch
D

D S

Q'

1
D

0
D

Q'

Computer Hardware Lecture 7 Slide9

The value that is held on the Q output of a D-Type

latch is the value of D at the instant at which the latch
goes from 1 to 0.
Q
Q'

Computer Hardware Lecture 7 Slide11

Computer Hardware Lecture 7 Slide10

Limitations of a D-Type latch

Latch

If the latch is 0, then S=R=1 Q and Q cannot change

September 2001

Symbol for a D-Type latch

September 2001

If the latch is 1 then S=D=Q and R=D=(Q)

September 2001

When the latch is at 1, any chnge on D causes a

change of Q, and this is undesirable.

September 2001

Computer Hardware Lecture 7 Slide13

Edge triggering

Undesirable output on Q when latching

In order to avoid the undesirable "spike", we adapt the

circuit so that the value of D is transferred to Q only
when the control input goes from 1 to 0.

Latch
D

This is called an edge triggered circuit

September 2001

Computer Hardware Lecture 7 Slide14

September 2001

The Master-Slave D-Type flip flop

D

Computer Hardware Lecture 7 Slide15

Making a D-Type flip flop from two latches

Q1'
Q2'

Clock
11100011

00011100

L
D

Q2
Q1

10110110
D

00010111

Q
00000011

Q'

Q
Q'
C

September 2001

Computer Hardware Lecture 7 Slide16

Clocks

September 2001

Computer Hardware Lecture 7 Slide17

Flip flops as finite state machines

Notice that in the master slave design of the D type

flip flop we have started to refer to the control input
as a clock.

Flip flops can be thought of as circuits that have only

two states:

Computers have clocks to drive their sequences of

actions. Essentially they control the storage of bits on
D-Type flip flops. They produce simply square
waves.

They can change state only when falling edge is

applied to the clock input.

September 2001

Computer Hardware Lecture 7 Slide18

Q=0
Q=1

They can be thought of as finite state machines

September 2001

Computer Hardware Lecture 7 Slide19

The D-Type flip flop and its finite state machine

Q
0

The T-Type flip flop (toggle)

September 2001

Computer Hardware Lecture 7 Slide20

September 2001

The J-K flip flop

Computer Hardware Lecture 7 Slide21

The (rising) edge triggered flip flop

100011
111110

11, 10

**0001

00
01

00
10

Q'
CLOCK

001101

11, 01

110011
011100

100111
September 2001

Computer Hardware Lecture 7 Slide22

September 2001

Computer Hardware Lecture 7 Slide23

PRESET
CLEAR

Q'

CLOCK

September 2001

Computer Hardware Lecture 7 Slide24