EE320 Electronic Notes

EE 320 Electronics I
Lecture Notes
Keith W. Whites
Fall 2009
Laboratory for Applied Electromagnetics and Communications

Department of Electrical and Computer Engineering
South Dakota School of Mines and Technology
2009 Keith W. Whites
Course Notes:
EE 320 Electronics I
Table of Contents
Lecture
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Title
Ideal Diode.
Physical Operation of Diodes.
DC Analysis of Diode Circuits.
Small-Signal Diode Model and Its Application.
Introduction to B2 Spice from Beige Bag Software.
Zener Diodes.
Diode Rectifier Circuits (Half Cycle, Full Cycle, and Bridge).
Peak Rectifiers.
Limiting and Clamping Diode Circuits. Voltage Doubler. Special Diode Types.
Bipolar Junction Transistor Construction. NPN Physical Operation.
PNP Bipolar Junction Transistor Physical Operation. BJT Examples.
DC Analysis of BJT Circuits.
The BJT as a Signal Amplifier.
BJT Small-Signal Equivalent Circuit Models.
BJT Small-Signal Amplifier Examples.
Graphical Analysis of a BJT Small-Signal Amplifier.
BJT Biasing. Current Mirror.
Common Emitter Amplifier.
Common Emitter Amplifier with Emitter Degeneration.
Common Base Amplifier.
Common Collector (Emitter Follower) Amplifier.
BJT Internal Capacitances. High Frequency Circuit Model.
Common Emitter Amplifier Frequency Response. Millers Theorem.
BJT as an Electronic Switch.
Enhancement Type MOSFET Operation, P-Channel, and CMOS.
MOSFET Circuit Symbols, iD-vDS Characteristics.
MOSFET Circuits at DC.
MOSFET as an Amplifier. Small-Signal Equivalent Circuit Models.
MOSFET Small-Signal Amplifier Examples.
Biasing MOSFET Amplifiers. MOSFET Current Mirrors.
Common Source Amplifier.
Common Source Amplifier with Source Degeneration.
CMOS Common Source Amplifier.
MOSFET Common Gate Amplifier.
CMOS Common Gate Amplifier.
MOSFET Common Drain (Source Follower) Amplifier.
CMOS Digital Logic Inverter.
Whites, EE 320
Lecture 1
Page 1 of 7
Lecture 1: Ideal Diode

Up to this point in your career as an ECE student, youve been
studying linear electrical components. For example, resistors
(R), inductors (L), and capacitors (C) are ideally linear elements
(and passive, of course).
Linear Circuit Elements

What do we mean that a component is linear? To answer this
question, recall there are just two independent qualities of
electricity in electrical circuits. These are voltage and current.
A linear circuit element is one that linearly relates the voltage
across that element to the current through the element.
Linearity has a precise mathematical statement. If a quantity y is
a function of another quantity x, as
y = f ( x)
(1)
Then y is linearly dependent on x if
my = f ( mx )
(2)
where m is a constant. In other words, f is a linear function if

when quantity x is multiplied by some constant m results in the
function simply being multiplied by m.
Whites, EE 320
Lecture 1
Page 2 of 7
Here are a couple of examples of linear components in electrical

circuits:
Resistors: v = Ri .
i
i
R
+
v
-
Capacitors: i = C
v
R
dv
.
dt
i
C
+
v
-
This is perhaps a bit tricker, but notice that differentiation

is a linear operator: if v increases by a factor m then i does
as well.
Ideal Diodes
You will now learn about a new electrical circuit element, the
diode. Diodes are made from two different types of
semiconducting materials that come together to form a
junction:
Whites, EE 320
Lecture 1
Page 3 of 7
The circuit symbol is
which is related to the physical markings on a typical diode as
In stark contrast to resistors, inductors, and capacitors, the diode

is a nonlinear element. For an ideal diode, the i-v characteristic
curve is
i
It is apparent from this i-v characteristic curve that there are two
distinct regions of operation of the ideal diode:
v < 0 i = 0 . In this region, the diode is off.
i > 0 v = 0 . In this region, the diode is on.
The ideal diode acts as an electronic valve allowing current in
only one direction through the diode: in the direction of the
arrow in the circuit symbol.
Whites, EE 320
Lecture 1
Page 4 of 7
We will find this valve behavior very useful in some

situations. For example, this is useful to prevent damage to an
electronic device when the battery is inserted backwards, for
example.
Applications of Diodes
Now we will briefly consider a couple of applications for
diodes. Well cover these in much more detail later.
Signal rectifier.
Think of this R as the Thevenin
resistance of additional circuitry
attached to the rectifier circuit.
+ vD +
vI
D
R
+
vO
-
If a ground is not shown, one is assumed

at the negative terminal of the source.
When vI > 0 , current will flow into the anode of D and

forward bias this device. With the ideal diode now on, vD is
very small and vO vI :
Whites, EE 320
Lecture 1
Page 5 of 7
vI
A
t
vO
A
t
Conversely, when vI < 0 , the ideal diode is off and there is

no current through R. Therefore, vO = 0 .
We have rectified the input voltage with this circuit.
This process of rectification will work for any type of input
signal, whether it is periodic (as shown above) or not.
Digital logic gate. Diodes and resistors together can be used
to make rudimentary logic gates. For example:
vA
vB
D1
D2
vY
R
Whites, EE 320
Lecture 1
Page 6 of 7
Assuming the voltages are 0 V for low signals and 5 V for

the high signals, then the circuit shown above is a two-input
OR gate:
o If vA = 5 V and vB = 0 or 5 V, then vY = 5 V.
o If vB = 5 V and vA = 0 or 5 V, then vY = 5 V.
for ideal diodes. This is an OR function Y=A+B.
Why do we have the resistor in this circuit? Its a clamp
down resistor and forces the voltage vY = 0 when vA = vB = 0.
(What if there was no R? Wouldnt the voltage be zero in this
case as well?)
One huge complication of diodes (or any nonlinear circuit
element) in an electrical circuit is the use of superposition in the
analysis is disallowed! (The exception to this is if the analysis
has been linearized for only small amplitude signals. Well see
this linearization throughout the course.)
Consequently, nonlinear circuit analysis is usually much more
complicated than linear circuit analysis. One often needs
numerical analysis for solution, such as that provided by circuit
simulation software.
Example N1.1 Determine the voltage V and current I in the

circuit below.
Whites, EE 320
Lecture 1
Page 7 of 7
D1
1V
D2
3V
V
I
1k
-5 V
This is a nonlinear circuit, so a completely different analysis

procedure is required than what youve used in the past for
linear circuits.
One process you can use to solve this problem is to try (i.e.
guess) different on/off combinations for the diodes D1 and D2
until you achieve a physically plausible and self consistent
solution.
For example, if D1 is on and D2 is on, then V = 1 V and 3 V.
It is simply impossible to have two different voltages
simultaneously at a node. Voltages must be single valued at all
nodes. We conclude that D1 and D2 cannot both be on
simultaneously.
Next, we try D1 off and D2 on. This leads to
V = 3 V and I = 8 mA.
This result is physically realistic and self consistent since with V
= 3 V then the voltage drop across D1 requires that it be off,
which is what we have assumed.
Whites, EE 320
Lecture 2
Page 1 of 10
Lecture 2: Physical Operation of Diodes.

Real diodes have a more complicated i-v characteristic curve
than ideal diodes. As shown in the text for a silicon diode:
(Fig. 3.8)
The diode has three distinct regions of operation:
1. Forward bias note that when the diode is on, the voltage
drop is approximately 0.6 V to 0.7 V for a silicon diode.
2. Reverse bias in this region i = I S , where IS is called the
saturation current. For small signal diodes, IS is often on
the order of fA (10-15 A).
3. Breakdown in this region v VZK for all I, where VZK is
called the breakdown knee voltage. This region of operation
is useful in certain applications.
In the forward bias region of operation, it can be shown from
first principals that
Whites, EE 320
Lecture 2
nVv
T
i = I S e 1
Page 2 of 10
(3.1),(1)
where
n = emission constant. Typically between 1 and 2.
VT = kT q 25 mV at room temperature (20C). Called
the thermal voltage.
Notice the highly non-linear relationship between i and v in this
equation. (Youll learn where this mathematical expression
comes from in EE 362.)
When v << 0 in (1), then
nVv
i = I S e T 1 I S
which is true for operation in the reverse bias region.
(2)
Well now take a quick look at the basic semiconductor physics

behind the pn junction, and then follow this up with examples
and applications.
PN Junction
Semiconductor junction diodes are made by joining two
semiconductors together. A pn junction diode is formed by
joining a p-type semiconductor to an n-type semiconductor:
Whites, EE 320
Lecture 2
p type
silicon
lattice
Page 3 of 10
n type
silicon
lattice
For a silicon diode, both the p and n regions are silicon, but in
each of these regions, small amounts of impurities have been
added through a process called doping.
To make p and n regions, we begin with a silicon crystal as
shown in Fig. 3.40. These atoms are held together by covalent
bonds (sharing pairs of electrons).
(Fig. 3.40)
At T = 0, the outermost electron (e-) of each atom is held in
covalent bonds. No current is possible since no electrons are
available to contribute to conduction.
Whites, EE 320
Lecture 2
Page 4 of 10
For T > 0, random thermal vibration provides enough energy for

some of the e- to break their covalent bonds (see Fig. 3.41).
These e- can contribute to conduction current.
(Fig. 3.41)
Holes
When electrons are thermally excited out of covalent bonds,
they leave a vacancy at the bond site, as illustrated above in
Fig. 3.41. This is called a hole.
Interestingly, holes can also contribute to conduction current in a
semiconductor material (see the figure below). This movement
is usually much slower than e- so the mobility of holes is
smaller.
Whites, EE 320
Lecture 2
Page 5 of 10
Donors and Acceptors

The concentration of holes and free electrons can be changed in
a silicon crystal by adding small amounts of impurities called
dopants. This is what makes electronic devices possible!
(1) To create holes, add acceptor dopants to the silicon (see
Fig. 3.44). For such p-type semiconductors, the silicon is
doped with trivalent impurity elements such as boron.
These impurity atoms displace silicon atoms (having four
electrons) with boron atoms (having three electrons).
Consequently, the regular silicon lattice has holes, or
locations in the lattice that can accept a free electron. This
hole can also move through the lattice.
Whites, EE 320
Lecture 2
Page 6 of 10
(Fig. 3.44)
(2) To create free electrons, add donor dopants (see Fig. 3.43).
For such n-type semiconductors, the silicon is doped with
pentavalent impurity elements such as phosphorus. These
impurities displace silicon atoms with phosphorous atoms
(having five electrons). Consequently, one extra electron is
available to move through the silicon lattice.
(Fig. 3.43)
Be aware that the entire p-type and n-type regions remain charge
neutral at all times! The dopant atoms are also charge neutral.
Whites, EE 320
Lecture 2
Page 7 of 10
At room temperature, thermal ionization breaks some covalent

bonds. In n-type materials we then have free electrons while in
p-type materials we have free holes.
p type means positive charge carriers predominate while n
type means negative charge carriers predominate.
Depletion Region
Something very special occurs when we place p-type material in
contact with n-type material. There now appears to be an
excess of holes in the p-type material and an excess of free
electrons in the n type.
p type
silicon
lattice
n type
silicon
lattice
Through the mechanism of diffusion (random motion due to

thermal agitation), excess holes will migrate to the n-type region
while excess free electrons will migrate to the p-type region.
More specifically, when the p- and n-type materials are placed
in contact (forming a junction), two things happen near the
contact region:
Whites, EE 320
Lecture 2
Page 8 of 10
(1) Holes diffuse across the junction (diffuse because the hole
concentration is higher in p type) into the n-type region and
recombine with majority electrons.
Diffusion of
majority carrier.
Recombination
+
+ -
p type
n type
With this electron now gone, we have uncovered a

positive charge from the dopant atom in the n-type region.
This forms a positively charged region.
++
++
++
++
++
+ + n type
++
p type
(2) Similarly, the majority carriers in the n-type region

(electrons) diffuse across the junction and recombine with
majority holes in the p-type region. This uncovers negative
bound charge.
p type --
++
++
++
++
++
+ + n type
++
This contact region between the p and n regions now has a

bound volume electric charge density. It is called the depletion
region. This may seem an unexpected name since only in this
region is there a net volume charge density (aka space charge)!
Whites, EE 320
Lecture 2
Page 9 of 10
Reverse and Forward Biased Junction

There are two important states for a pn junction, the reversed
biased and forward biased states:
(1) Reversed biased state:
An electric field E is created in the depletion region
because of the uncovered charges near the junction:
Ebattery
E-
+++
+++
+++
+++
+++
+++
+++
width of depletion
region increases
V
For the reversed biased state of the pn junction, the electric

field produced by the battery Ebattery adds to this electric
field of the space charge E in the depletion region. This
increases the width of the depletion region.
Consequently, the majority carriers cannot flow through
the region: holes in the p material are opposed by E in the
depletion region, as are electrons in the n material. Hence,
little current flows (only the drift current IS) unless the
junction breaks down. This occurs when Ebattery is strong
Whites, EE 320
Lecture 2
Page 10 of 10
enough to strip electrons from the covalent bonds of the

atoms, which are then swept across the junction.
(2) Forward biased state:
Ebattery
minority carrier
minority carrier
+
p
-
E -
+
+
+
+
+
+
+
+
n
-
width of depletion
region decreases
V
When V is large enough so that Ebattery > E, then (i) holes

are swept from the p to n regions, and (ii) electrons are
swept from the n to p regions. We now have current!
Whites, EE 320
Lecture 3
Page 1 of 10
Lecture 3: DC Analysis of Diode Circuits.

Well now move on to the DC analysis of diode circuits.
Applications will be covered in following lectures.
Lets consider this very simple diode circuit:
We will assume that the diode is forward biased. Using KVL

VDD = IR + VD
(3.7),(1)
From the characteristic equation for the diode
VD
nV
T
I = I S e 1
(3.1),(2)
Assuming n, IS, and VT are known, we have two equations for

the two unknown quantities VD and I. Substituting (2) into (1):
VD
nV
T
VD = VDD I S R e 1
(3)
which is a transcendental equation for VD. There is no simple

analytical solution to this equation.
So how do we solve such a circuit problem? Over the next
couple of pages well mention five methods.
Whites, EE 320
Lecture 3
Page 2 of 10
1. Graphical Analysis. Begin with the diode i-v characteristic

curve:
i
(3.1)
From (1), we can rearrange the equation in terms of I to also

plot above. That is, from (1)
V
V
I = DD D
(4)
R
R
which is an equation for a straight line ( y = b + mx ):
i
VDD/R
Slope = -1/R
v
VDD
We call this straight line the load line.

Now, plot both of these curves on the same graph:
Whites, EE 320
Lecture 3
Page 3 of 10
(Fig. 3.11)
The point where these two curves intersect is the
simultaneous solution to the two equations (1) and (2).
This graphical method is an impractical solution method for
all but the simplest circuits. However, it is useful for a
qualitative understanding of these circuits. For example, what
happens when:
(a) VDD increases?
VDD
(b) R increases?
Whites, EE 320
Lecture 3
Page 4 of 10
2. Simulation packages. SPICE, Agilents Advanced Design

System (ADS), etc. Here is a simple example using ADS:
DC
DC
DC1
565 mV
VD
1.43 mA
2V
-1.43 mA
V_DC
SRC1
Vdc=2.0 V
R
R1
R=1 kOhm
1.43 mA
ap_dio_1N4148_1_19930601
D1
3. Numerical methods. Use Mathematica, Matlab, Mathcad, etc.

Here is a simple example from Mathcad:
Whites, EE 320
Lecture 3
Page 5 of 10
4. Iterative analysis. See example 3.4 in the text.

5. Approximate analysis. This is by far the most widely used
approach for hand calculations.
Approximate Diode Circuit Solutions

There is often a need for us to perform design with pencil and
paper. Remember: simulation packages dont design for you,
they only analyze circuits. Theres a big difference between
design and analysis!
There are two very important approximate diode models that
allow easier paper designs:
1. Constant-Voltage-Drop (CVD) Model.
2. Piecewise Linear (PWL) Model.
Constant-Voltage-Drop (CVD) Model

In this model, the characteristic curve is approximated as:
Whites, EE 320
Lecture 3
Page 6 of 10
(Fig. 3.15)
In words, this model says that if the diode is forward biased,
then the voltage drop across the diode is VD. If not forward
biased, the diode is then reversed biased and the current is zero
and VD can be any value < VD.
VD is often set to 0.7 V for silicon diodes, as shown above, while
set to 0.2 V for Schottky diodes, for example.
The CVD circuit model for diodes is
(Fig. 3.16b)
This is probably the most commonly used diode model for hand
calculations.
Whites, EE 320
Lecture 3
Page 7 of 10
Example N3.1. Determine the current I in the circuit below

using the CVD model and assuming a silicon diode.
Using the CVD model, the equivalent approximate circuit is:
Assuming the diode is forward conducting (i.e., on) with VD =

0.7 V and using KVL in this circuit:
2 = IR + VD
2 VD 2 0.7
I=
=
= 1.3 mA
or
R
1000
The positive value of this current indicates our original
assumption that the diode is on is correct.
What if VDD = 0.5 V? By KVL again,
0.5 VD 0.5 0.7
I=
=
= 0.2 mA.
R
1000
Since I is negative, then D must be reversed biased. This means
our initial forward conducting assumption was incorrect. Rather,
in this situation I = 0 and VD = 0.5 V.
Whites, EE 320
Lecture 3
Page 8 of 10
Piecewise Linear (PWL) Diode Model

This is a battery plus internal diode resistance model. It is one
step better than the CVD model by incorporating a slope to the
interpolative line:
(Fig. 3.12)
The finite slope to this curve means that the diode has a nonzero internal resistance, which we will label as rD. The
equivalent circuit for the PWL diode model is then
(Fig. 3.13b)
Whites, EE 320
Lecture 3
Page 9 of 10
Example N3.2. Determine the current I in the circuit below

using the PWL diode model shown in text Figure 3.12.
From Fig. 3.12, we can determine VD0 and rD for the particular
diode whose characteristic equation is shown:
VD0 = 0.65 V
run 0.9 0.65
rD =
=
= 20.8 .
rise 12 103
The equivalent circuit using the PWL model of the diode is then
I
R=1 k
+
VDD=
2V
VD
-
+
Ideal VIdeal
VD0=0.65 V
rD=20.8
Assuming the diode is on,, then by KVL:

2 = I 1000 + 0.65 + 20.8 I
or
I = 1.32 mA.
This is close to the 1.3 mA we computed in the last example

using the cruder CVD model. Again, the positive value of this
Whites, EE 320
Lecture 3
Page 10 of 10
current indicates that we made the correct choice that the diode
is on.
Whats the forward voltage drop across the diode?
VD = 2 1000 1.32 103 = 0.68 V
Is this enough to turn the diode on? Yes, referring to the
equivalent circuit above
VIdeal = VD 0.65 20.8 1.32 103 0+ V
Whites, EE 320
Lecture 4
Page 1 of 9
Lecture 4: Small-Signal Diode Model

and Its Application.
The diode analysis so far has focused only on DC signals. We
must also consider the application of diodes in circuits with time
varying signals. This analysis is also complicated by the
nonlinear nature of the diode.
Large signal analysis of diode circuits is often best left for
circuit simulation packages. Conversely, small signal analysis
of nonlinear diode circuits can sometimes be done by hand.
The concept behind small-signal operation is that a time varying
signal with small amplitude rides on a DC value that may or
may not be large.
The analysis of the circuit is then divided into two parts:

1. DC bias
2. AC signal of small amplitude.
and the solutions are added together using superposition.
Whites, EE 320
Lecture 4
Page 2 of 9
For example:
(Fig. 3.17a)
where vd(t) is some time varying waveform, perhaps periodic
such as a sinusoid or triangle signal.
The purpose of VD in this circuit is to set the operation of the
diode about a point on the forward bias i-v characteristic curve
of the diode. This is called the quiescent point, or Q point, and
the process of setting these DC values is called biasing the
diode.
(Fig. 3.17b)
Whites, EE 320
Lecture 4
Page 3 of 9
The total voltage at any time t is the sum of the DC and AC

components
vD ( t ) = VD + vd ( t )
(3.10),(1)
provided the AC signal is small enough that the diode operates
approximately in a linear fashion. (See Section 1.4.9 for a
discussion on the symbol convention used in your text.)
The diode current is (3.1) with iD ( t ) >> I S such that
vD ( t )
VD
nVT
vd ( t )
iD ( t ) I S e nVT = I S e e nVT
N
=ID
vd ( t )
or
iD ( t ) = I D e nVT
(3.12),(2)
where ID is the DC diode current.

We can series expand the exponential term using
x2
x
e = 1 + x + +"
2!
and if vd(t) is small enough so that vd ( t ) ( nVT ) << 2 , truncate
the series to two terms:
vd ( t )
v (t )
(3)
e nVT 1 + d
nVT
Substituting (3) in (2) gives
I
iD ( t ) I D + D vd ( t )
(3.14),(4)
nVT
Whites, EE 320
Lecture 4
Page 4 of 9
So, if vd(t) is small enough we can see from this last equation
that iD is the sum (or superposition) of two components: DC and
AC signals. What weve done is to linearize the problem by
limiting the AC portion of vD to small values.
The term nVT I D has units of ohms. It is called the diode smallsignal resistance:
nV
rd T []
(3.18),(5)
ID
From a physical viewpoint, rd is the inverse slope of the tangent
line at a particular bias point along the characteristic curve of the
diode. Note that rd changes depending on the (DC) bias:
(Note that this rd is a fundamentally different quantity than rD

used in the PWL model of the diode discussed in the previous
lecture.)
The equivalent circuit for the small-signal operation of diodes is:
Whites, EE 320
Lecture 4
Page 5 of 9
Because we have linearized the operation of the diode (by

restricting the analysis to small AC signals), we can use
superposition to analyze the composite DC and AC signals.
That is, signal analysis is performed by eliminating all DC
sources (short out DC voltage sources/open circuit DC current
sources) and replacing the diode with its small-signal resistance
rd.
This process is illustrated below:
iD=ID+id R
+
AC (signal)
vs
-
DC (bias)
ID
VDD
id
+
VDD
+
vD=VD+vd
-
VD
-
Ideal
VD0
R
+
+
rd
vs
-
vd =
-
rd
vs
rd + R
rD
AC only: rides on VD.
Whites, EE 320
Lecture 4
Page 6 of 9
Example N4.1 (Text example 3.6). For the circuit shown below,
determine vD when V + = 10 + 1 cos ( 2 60t ) V.
V+
2V
10 V
Called ripple if one
desires purely DC.
t
T=1/f=1/60 s
The diode specifications are

0.7-V drop at 1 mAdc
n = 2.
As we discussed, for small AC signals we can separate the DC
analysis from the AC (i.e., linearized). We need to start with the
DC bias. Assuming VD 0.7 V for a silicon diode the DC
current is
10 0.7
ID =
= 0.93 mA
10,000
Since I D 1 mA, then VD will be very close to the assumed
value.
At this DC bias, then the small-signal resistance at the Q point is
nVT 2 25 103
rd =
=
= 53.8
3
ID
0.93 10
Whites, EE 320
Lecture 4
Page 7 of 9
We use this rd as the equivalent resistance in the small-signal

model of the diode
The AC voltage across the diode is found from voltage division

as
rd
53.8
vd ( t ) =
vs =
cos (t )
rd + 10,000
53.8 + 10,000
= 5.35cos (t ) mV
The corresponding phasor diode voltage is then

vd = 5.35 mVp = 10.70 mVpp
where the subscript p indicates a peak value and the pp
subscript means a peak-to-peak value.
Were we justified in using a small-signal assumption for this
problem? From page 3, lets check if vd ( t ) ( nVT ) << 2 :
vd
5.35 103
=
= 0.107
3
nVT 2 25 10
which is much less than 2. So, yes, the small-signal assumption
is valid here.
As an aside, note that in this circuit the ripple in the voltage has
been reduced at the output. At the input, the ripple is 2/10=20%
Whites, EE 320
Lecture 4
Page 8 of 9
of the DC component while at the output the ripple is

0.0107/0.7=1.5% of the DC component.
See text example 3.7 for another example of this ripple
reduction.
Diode High Frequency Model

This purely resistive AC model for the diode works well when
the frequency of the AC signals is sufficiently low.
At high frequencies, we need to include the effects that arise due
to these time varying signals and the charge separation that
exists in the depletion region and in the bulk p and n regions of
the diode under forward bias conditions.
Cd
+
p
-
+
+
+
+
+
+
+
n
-
Cj
VS
vs
Within the device and the depletion region there exists an

electric field, as discussed in Lecture 2. For AC signals, this
electric field is varying with time.
Whites, EE 320
Lecture 4
Page 9 of 9
As youve learned in electromagnetics, a time varying electric

field is a displacement current. The effects of a displacement
current are modeled by equivalent circuit capacitances:
rd
Cj
Cd
We wont do anything with this effect now. This is presented

primarily as an FYI. (However, later in the course we will
investigate this capacitive junction effect in transistors and how
it affects the gain of transistor amplifier circuits at high
frequencies.)
Whites, EE 320
Lecture 5
Page 1 of 10
Lecture 5: Introduction to B2 Spice from

Beige Bag Software.
There are many, many circuit simulation packages available
today. SPICE and PSPICE are two common examples. In this
course, we will be using B2 Spice from Beige Bag Software. A
free version, B2 Spice A/D V4 Lite, is available from Beige Bag
(www.beigebag.com) and has been installed on the campus PCs.
B2 Spice Simulation of a Simple DC Diode Circuit

To illustrate the use of B2 Spice, we will analyze the simple
series resistor and diode circuit considered earlier in Lecture 3:
B2 Spice startup window:
Whites, EE 320
Lecture 5
Page 2 of 10
The circuit is assembled in the schematic editor shown above.

You graphically add electrical parts to your circuit by choosing
them from the menus, then draw wires to interconnect these
devices. You can adjust the properties of these devices by
double clicking the component once its placed in the schematic.
Well first place a resistor. Select Devices | Resistor (simple)
(R) then click on the schematic to place the resistor:
Whites, EE 320
Lecture 5
Page 3 of 10
You can double click the component to change its values, such
as the resistance of the resistor in this case. However, the default
value of 1 k is the value we need here.
To add the DC voltage source, we select Devices | Voltage
Source (V) then click once to place the voltage source on the
schematic. Selecting Ctrl + r once rotates the source vertically
giving:
Whites, EE 320
Lecture 5
Page 4 of 10
Next, well add the diode. In this case, well add the generic
diode available in B2 Spice in Devices | Diode (D):
In the full version of B2 Spice there is a huge library of

component libraries available, but in the Lite version there is
Whites, EE 320
Lecture 5
Page 5 of 10
only two: the generic diode and the 1N4007 diode, which can be
found in Categories | Diode .
The next steps are to connect the circuit components together
using the wire tool and then add a circuit ground from Devices |
Ground (0). The wire tool is accessed from the toolbar as
illustrated below:
The final step in setting up this simulation in B2 Spice is to add a

voltmeter to measure the diode voltage. Select Devices |
Voltmeter Vertical (2), place the component, then wire it into
the circuit as shown using the wiring tool:
Whites, EE 320
Lecture 5
Page 6 of 10
Before running the simulation we will change the voltage source

to 2 V:
Whites, EE 320
Lecture 5
Page 7 of 10
The final step is to tell B2 Spice what type of simulation you

would like to perform. Select Simulation | Set Up Simulations
and select .OP (Operating Point) for a DC simulation:
At this point the circuit is ready to be analyzed by B2 Spice. To

run the simulation, simply select Simulation | Run
Simulations (or press F5):
Whites, EE 320
Lecture 5
Page 8 of 10
Notice that a voltage of 598.3 mV now appears in the voltmeter

device, indicating the DC voltage across the diode. A table of
data also pops up when the simulation has finished. In this
particular case it indicates the current into the voltage source V1
is -1.402 mA, or equivalently, the current out of the source is
+1.402 mA.
Plot VD Versus Variable Source Voltage

For the next simulation, we will plot the diode voltage VD1 as
the source voltage changes from 0 V to 4 V. Well then make a
plot of this diode voltage.
To begin, we select Simulation | Set Up Simulations and
Enable the Single or Dual Parameter DC Sweep as indicated:
Whites, EE 320
Lecture 5
Page 9 of 10
Then we select the Single or Dual Parameter DC Sweep button,

which brings up the Dual Stepped DC Sweep window. The
source we wish to vary is the voltage V1 with a Start Value of 0
V and a Stop Value of 4 V. Well choose a step voltage of 0.1 V
for this sweep:
After simulating by selecting Simulation | Set Up

Simulations, the following plot will appear showing the
variation of the diode voltage as the source voltage varies from 0
to 4 V, as desired.
Whites, EE 320
Lecture 5
Page 10 of 10
Whites, EE 320
Lecture 6
Page 1 of 11
Lecture 6: Zener Diodes.

The very steep portion in the reverse biased i-v characteristic
curve is called the breakdown region.
In this region the voltage across the diode remains nearly

constant while the current varies (i.e., small internal resistance).
There are two physical mechanisms that can produce this
behavior in the breakdown region. One is the Zener effect in
which the large electric field in the depletion region causes
electrons to be removed from the covalent bonds in the silicon.
The second mechanism is the avalanche effect in which charges
that are accelerated to high speeds due to the large electric field
in the depletion region collide with atoms in the silicon lattice
causing charges to be dislodged. In turn, these dislodged charges
have sufficient energy to liberate additional electrons. In other
words, this avalanche effect is a cascading, ionization process.
Whites, EE 320
Lecture 6
Page 2 of 11
Provided that the power dissipated in the diode is less than the
maximum rated, the diode is not damaged when operating in the
breakdown region. In fact, Zener diodes are designed to operate
in this region.
The circuit symbol for the Zener diode is
(Fig. 3.20)
These diodes are usually operated in the reverse bias regime
(i.e., breakdown region) so that IZ > 0 and VZ > 0.
An enlargement of this breakdown region is shown in text
Figure 3.21:
(Fig. 3.21)
Whites, EE 320
Lecture 6
Page 3 of 11
The manufacturer specifies the VZ0 and test current IZT. One can
design Zeners with a wide range of voltages.
The page below is from a Digikey catalog (www.digikey.com)

and shows voltages from ranging from 3.6 V to 200 V, for
example.
The rated VZ at the specified IZT is listed for these Zener diodes.
The circled component, for example, has VZ = 8.2 V at IZT = 31
mA. The maximum rated power is 1 W for this device.
Whites, EE 320
Lecture 6
Page 4 of 11
As the current deviates from the specified value IZT, the voltage
VZ also changes, though perhaps only by a small amount. The
change in voltage VZ is related to the change in the current IZ
as
VZ = rz I Z
(1)
where rz is the incremental or dynamic resistance at the Q point
and is usually a few Ohms to tens of Ohms. See the datasheet for
the particular device you are working with.
Because of the nearly linear relationships in the breakdown
region, the reverse bias model of the Zener diode is
(Fig. 3.22)
VZ = VZ 0 + rz I Z
where
as is apparent from Fig. 3.21.
Applications of Zener Diodes

What are Zener diodes used for? Applications include:
(3.20),(2)
Whites, EE 320
Lecture 6
Page 5 of 11
1. Voltage overload protection. This circuit is from the NorCal

40A radio that is built in EE 322 Electronics II Wireless
Communication Electronics:
2. Voltage regulation. See the figure below. An example of

such a regulator circuit will be considered next.
(Source: Sedra and Smith, fourth ed.)
Whites, EE 320
Lecture 6
Page 6 of 11
Example N6.1 (similar to text example 3.8). The Zener diode in

the circuit below has the following characteristics: 6.8-V rating
at 5 mA, rz = 20 , and IZK = 0.2 mA.
(Fig. 3.23a)
With these ratings
VZ = VZ 0 + rz I Z VZ 0 = VZ rz I Z
or
VZ 0 = 6.8 20 5 103 = 6.7 V
Note that the supply voltage can fluctuate by 1 V. Imagine this
fluctuation is a random process rather than a time periodic
variation.
Determine the following quantities:
(b) Find VO with no load and V+ at the nominal value. The
equivalent circuit for the reverse bias operation of the
Zener diode is
Whites, EE 320
Lecture 6
Page 7 of 11
From this circuit we calculate

10 6.7
IZ =
= 6.35 mA
500 + 20
Therefore,
VO = 10 I Z 500 = 10 6.35 103 500 = 6.83 V
(c) Find the change in VO resulting from a 1 V change in V+.
Using the circuit above the V+ = 11 V:
11 6.7
VO = 11
500 = 6.865 V
500 + 20
+
Similarly, with V =9 V:
9 6.7
VO = 9
500 = 6.788 V
500 + 20
Consequently, VO = 6.865 6.788 = 0.077
VO = 38.5 mV.
or
The ratio of the change in output voltage to the change in

the source voltage ( VO V + ) is called the line regulation
Whites, EE 320
Lecture 6
Page 8 of 11
of the regulator circuit. Its often expressed in units of

mV/V. For this example and no load attached,
VO
77 mV
mV
Line Regulation
3
8
.
5
=
=
V
V + 11 9 V
(d) Find the change in VO resulting from connecting a load of
RL = 2 k with a nominal V+ = 10 V.
Assuming that the diode is operating in the breakdown
region:
then
IL =
6.8
= 3.4 mA.
2000
Is this a reasonable value? Calculate IS:

10 6.8
IS =
= 6.4 mA.
500
So, yes, this is a reasonable value because I L < I S , as it
must.
From (1), VO = rz I Z and since I Z = 3.4 mA then
Whites, EE 320
Lecture 6
Page 9 of 11
VO = 20 ( 3.4 103 ) = 68 mV
The ratio of the change in output voltage to the change in
the load current ( VO I L ) is called the load regulation of
the regulator circuit. Its often expressed in units of
mV/mA. For this example,
V
mV
77 mV
= 22.6
Load Regulation O =
I L 3.4 mA
mA
(e) What is VO when RL = 0.5 k? Assume the diode is in

breakdown. In this case,
6.8
IL
= 13.6 mA.
500
Is this a reasonable value? No, because this value is greater
than IS = 6.4 mA.
Therefore, in this case the Zener diode is not operating in
the breakdown region. Also, the diode cant be forward
biased. Consequently, we conclude the diode must be
operating in the reverse bias region.
The equivalent circuit in this case is
Whites, EE 320
Lecture 6
Page 10 of 11
10 V
500
+
VO
-
From this circuit we calculate

500
VO =
10 = 5 V.
500 + 500
This voltage is less than the breakdown voltage VZK, which
is consistent with the reverse biased assumption.
(f) Determine the minimum RL for which the diode still
remains in breakdown for all V+. (We know from the results
in parts (c) and (d) of this example that RL must lie between
500 and 2 k when V + = 10 V.)
Referring to Fig. 3.21, at the knee I Z = I ZK = 0.2 mA and
VZ = VZK VZ 0 = 6.7 V.
Whites, EE 320
Lecture 6
Page 11 of 11
If V+ = 9 V:
9 6.7
= 4.6 mA.
500
Therefore, IL = 4.6 mA-0.2 mA = 4.4 mA, so that
V
6.7
RL = L =
= 1,522
I L 4.4 103
IS =
If V+ = 11 V:
11 6.7
= 8.6 mA.
500
Therefore, IL = 8.6 mA-0.2 mA = 8.4 mA, so that
V
6.7
RL = L =
= 798
3
I L 8.4 10
IS =
The smallest load resistance that can be attached to this

circuit and have the diode remain in breakdown is RL =
1,522 . The reason is that for any smaller value when
V+ = 9 V results in the diode leaving breakdown and
entering the reverse bias mode.
Whites, EE 320
Lecture 7
Page 1 of 9
Lecture 7: Diode Rectifier Circuits

(Half Cycle, Full Cycle, and Bridge).
We saw in the previous lecture that Zener diodes can be used in
circuits that provide (1) voltage overload protection, and (2)
voltage regulation.
An important application of regular diodes is in rectification
circuits. These circuits are used to convert AC signals to DC in
power supplies.
A block diagram of this process in a DC power supply is shown
below in text figure 3.24:
In this DC power supply, the first stage is a transformer:
An ideal transformer changes the amplitude of time varying

voltages as
Whites, EE 320
Lecture 7
Page 2 of 9
N2
vp
(1)
N1
This occurs even though there is no direct contact between the
input and output sections. This magic is described by
Faradays law:
d
E
dl
B ds
=
v
dt
C(S )
S (C )
vs =
or
emf =
d m
dt
(2)
By varying the ratio N 2 N1 in (1) we can increase or decrease

the output voltage relative to the input voltage:
If N 2 > N1 , have a step-up transformer
If N 2 < N1 , have a step-down transformer.
For example, to convert wall AC at ~120 VRMS to DC at, say,
13.8 VDC, we need a step down transformer with a ratio of:
N 2 15 1
=
or 8 :1 ratio ( N1 : N 2 ).
N1 120 8
We choose vs 15 VDC for a margin.
For the remaining stages in this DC power supply:

Diode rectifier. Gives a unipolar voltage, but pulsating
with time.
Filter. Smoothes out the pulsation in the voltage.
Whites, EE 320
Lecture 7
Page 3 of 9
Regulator. Removes the ripple to produce a nearly pure DC

voltage.
We will now concentrate on the rectification of the AC signal.

Well cover filtering in the next lecture.
Diode Rectification
We will discuss three methods for diode rectification:
1. Half-cycle rectification.
2. Full-cycle rectification.
3. Bridge rectification. (This is probably the most widely
used.)
1. Half-Cycle Rectification
Weve actually already seen this circuit before in this class!
(Fig. 3.25a)
We will use the PWL model for the diode to construct the
equivalent circuit for the rectifier:
Whites, EE 320
Lecture 7
Page 4 of 9
(Fig. 3.25b)
From this circuit, the output voltage will be zero if vS ( t ) < VD 0 .
Conversely, if vS ( t ) > VD 0 we can determine vO by superposition
of the two sources (DC and AC) in the circuit sources since we
have linearized the diode:
R
DC: vO ( t ) = VD 0
R + rD
R
AC: vO ( t ) = vS ( t )
R + rD
Notice that were not making a small AC signal assumption
here. Rather, we have used the assumption of the PWL model to
completely linearize this problem when vS ( t ) > VD 0 and then
used superposition of the two sources, which just happen to be
DC and AC sources. (Consequently, we should not use rd here.)
The total voltage is the sum of the DC and AC components:
R
vS ( t ) > VD 0
vO ( t ) = vO ( t ) + vO ( t ) = vS ( t ) VD 0
R + rD
(3.21),(3)
For vS ( t ) < VD 0 , vO ( t ) = 0 .
Whites, EE 320
Lecture 7
Page 5 of 9
In many applications, rD R so that R ( R + rD ) 1. Hence,

0
vS ( t ) < VD 0
(3.22),(4)
vO ( t ) =
vS ( t ) > VD 0
vS ( t ) VD 0
A sketch of this last result is shown in the figure below.
(Fig. 3.25d)
There are two important device parameters that must be
considered when selecting rectifier diodes:
1. Diode current carrying capacity.
2. Peak inverse voltage (PIV). This is the largest reverse
voltage across the diode. The diode must be able to
withstand this voltage without shifting into breakdown.
For the half-cycle rectifier with a periodic waveform input
having a zero average value
PIV = Vs
(5)
where Vs is the amplitude of vS.
Whites, EE 320
Lecture 7
Page 6 of 9
2. Full-Cycle Rectification
One disadvantage of half-cycle rectification is that one half of
the source waveform is not utilized. No power from the source
will be converted to DC during these half cycles when the input
waveform is negative in Fig. 3.25d.
The full-cycle rectifier, on the other hand, utilizes both the
positive and negative portions of the input waveform. An
example of a full-cycle rectifier circuit is:
(Fig. 3.26a)
Notice that the transformer has a center tap that is connected to
ground.
On the positive half of the input cycle vS > 0 , which implies that
D1 is on and D2 is off. Conversely, on the negative half of
the input cycle, vS < 0 which implies that D1 is off and D2 is
on.
Whites, EE 320
Lecture 7
Page 7 of 9
In both cases, the output current iO ( t ) 0 and the output voltage

vO ( t ) 0 :
(Fig. 3.26c)
While this full-cycle rectifier is a big improvement over the halfcycle, there are a couple of disadvantages:
PIV = 2Vs VD 0 , which is about twice that of the half-cycle
rectifier. This fact may require expensive or hard-to-find
diodes.
Requires twice as many transformer windings on the
secondary as does the half-cycle rectifier.
3. Bridge Rectification
The bridge rectifier uses four diodes connected in the famous
bridge pattern:
Whites, EE 320
Lecture 7
Page 8 of 9
Is
+
vp
vs
D4
D1
- vO +
D2
D3
Is
Oftentimes these diodes can be purchased as a single, fourterminal device.

Note that the bridge rectifier does not require a center-tapped
transformer, but uses four diodes instead.
The operation of the bridge rectifier can be summarized as:
1. When vS ( t ) > 0 then D1 and D2 are on while D3 and D4
are off:
2. When vS ( t ) < 0 then D1 and D2 are off while D3 and D4

are on:
i
D4
- vO +
i
D3
Whites, EE 320
Lecture 7
Page 9 of 9
In both cases, though, vO ( t ) > 0 :
(Fig. 3.27b)
The bridge rectifier is the most popular rectifier circuit.
Advantages include:
PIV = Vs VD 0 , which is approximately the same as the
half-cycle rectifier.
No center tapped transformer is required, as with the halfcycle rectifier.
Whites, EE 320
Lecture 8
Page 1 of 10
Lecture 8: Peak Rectifiers.

The output of the rectifier circuits discussed in the last lecture is
pulsating significantly with time. Hence, its not useful as the
output from a DC power supply.
One way to reduce this ripple is to use a filtering capacitor.
Consider the half-cycle rectifier again, but now add a capacitor
in parallel with the load:
(Fig. 3.29a)
We expect that as soon as we turn on the source, the capacitor
will charge up on + cycles of vI and discharge on the -
cycles.
To smooth out the voltage, we need this discharge to occur
slowly in time. This means we need to choose C large enough to
make this happen, presuming that R is a given quantity (the
Thvenin resistance of the rest of the circuit).
Whites, EE 320
Lecture 8
Page 2 of 10
The output voltage vO will then be a smoothed-out signal that

pulsates with time:
(Fig. 3.29)
Notice the diode current and the capacitor voltage. They display
behavior much different than what one would find in an AC
circuit.
Analysis of Peak Rectifier Circuits

Well require that = RC T , which means that the time
constant of the RC circuit must be much greater that the period
of the input sinusoidal signal:
Whites, EE 320
Lecture 8
Page 3 of 10
Now, our quest is to approximately determine the ripple voltage

Vr, assuming T :
v
Essentially a straight line for >> T
vO
Vr
Vp
t
td
vI
Diode on
Not sketched to scale.
When D is off, and assuming it is an ideal diode

vO ( t ) = V p e t
(1)
[If D is not ideal then vO ( t ) (V p 0.7 ) e t .]
At the end of the discharge time, td, the output voltage equals
vO ( td ) = V p Vr
(2)
Substituting for vO from (1) at this time td leads to
Vr
V p e td = V p Vr or
= 1 e td
Vp
(3)
Whites, EE 320
Lecture 8
Page 4 of 10
This equation has the two unknowns Vr and td, assuming is

known. If we can determine td, then we can find Vr. Finding td
can be done numerically by equating (1) to the expression for
the input voltage
vI ( t ) = V p cos (t )
(4)
and solving for the time td when the two are equal as
V p cos (td ) = V p e td or cos (td ) = e td
(5)
This needs to be done numerically since (5) is a transcendental

equation.
Alternatively, if t is small compared to T (true when T , as
assumed), then from (3)
Vr
T t
= 1 e ( ) 1 e T
(6)
Vp
Again, because T then we can truncate the series expansion
of the exponential function to two terms (see Lecture 4) giving
Vr T
( T )
(7)
Vp
This simple equation gives the ratio of the ripple voltage to the
peak voltage of the input sinusoidal signal for the half-cycle
rectifier. Its worth memorizing, or knowing how to derive.
Often R and T are fixed quantities. So from (7)
T
Vr V p
( T )
(3.28),(8)
RC
to obtain a small ripple voltage we need a large C in this case.
Whites, EE 320
Lecture 8
Page 5 of 10
Conduction Interval
Lastly, the conduction interval t is defined as the time interval
in which the diode is actually conducting current. This time
period is sketched in the preceding two figures.
The diode conducts current beginning at time td and ending at T,
within each period. Using equation (4) at time td
V p cos (T td ) = V p Vr or V p cos (t ) = V p Vr (9)
We expect the conduction interval to be small. So truncating the
series expansion of cosine to two terms, (9) gives
2Vr
t
(3.30),(10)
Vp
The factor t is sometimes called the conduction angle, . For
Vr V p this conduction angle (and conduction interval) will be
small, as expected.
Discussion
To reiterate, the objective of the peak rectifier is to charge the
shunt C when D is on, and slowly discharge it during those
times when D is off.
Whites, EE 320
Lecture 8
Page 6 of 10
When does D conduct? During the t periods in the previous

figure. Also see Fig. 3.29(c).
Note that this peak rectifier is not a linear circuit. iD is a very
complicated waveform and not a sinusoid, as seen earlier in Fig.
3.29(c). There are no simple exact formulas for the solution to
this problem. The text only shows approximate solutions for
peak iD:
Vp
2V p
(3.32),(11)
iD max 1 + 2
[A] (Vr V p )
R
Vr
Example N8.1 (similar to text example 3.9). A half-cycle peak

rectifier with R = 10 k is fed by a 60-Hz sinusoidal voltage
with a peak amplitude of 100 V.
(a) Determine C for a ripple voltage of 2 Vpp. From (8):

1
100
T Vp
C=
=
R Vr 60 10,000 2
C = 83.3 F.
or
For a factor of safety of two, make C twice as large.
Remember, a bigger C translates to smaller ripple.
(b) Determine the peak diode current. Using (11):
Whites, EE 320
iD
or
Lecture 8
max
Page 7 of 10
Vp
2V p
100
2 100
1
2
1 + 2
+
=
R
Vr 10,000
2
iD max 638 mA.
When specifying a diode for your circuit design, you would

need to find one that could safely handle this amount of
current.
Example N8.2. A half-cycle peak rectifier with R = 10 k is fed

by a 60-Hz triangular voltage with a peak amplitude of 100 V.
(a) Determine C for a ripple voltage of 2 Vpp. If you go back and

look at the derivation of (8) youll find that there were no
approximations made that required a sinusoidal waveform.
Consequently, (8) applies to this triangular waveform as
well, provided T . Hence, as before
C = 83.3 F.
(b) Determine the diode conduction time, t. Referring to this
sketch of the region near the positive peak voltage for vI:
Whites, EE 320
Lecture 8
Page 8 of 10
vO
Vr
Vp
vI
t
t
Diode on
Because the rising portion of the waveform is a straight line:

Vp
rise
vI =
t=
t
T /4
run
To find t, equate
4V p
4V p
vI =
t or Vr =
t
T
T
Therefore, for a triangular waveform
T Vr
t =
(12)
4 Vp
In this particular case,
1 60 2
t =
= 83.3 s
4 100
Compare this time to a sinusoidal waveform:
T 2Vr 1 60 2 2
t =
=
= 530.5 s
2 V p
2 100
This time is much longer than for the triangular waveform.
Consequently, we would expect iD max for D to be much
larger for the triangular waveform than for the sinusoid!
Whites, EE 320
Lecture 8
Page 9 of 10
Full-Cycle Peak Rectifiers

In a similar fashion, we can also add a shunt C to full cycle and
bridge rectifiers to convert them to peak rectifiers.
For example, for a full-cycle peak rectifier:
The output voltage has less ripple than from a half-cycle peak
rectifier (actually one half less ripple).
vO
vI
t
T
The ripple frequency is twice that of a half-cycle peak

rectifier. Using the same derivation procedure as before with the
half cycle, but with T T 2 gives from (7)
Vr T
( T )
(3.33),(13)
V p 2
Whites, EE 320
Lecture 8
Page 10 of 10
Lastly, it can be shown that the iD max for the full-cycle peak
rectifier:
Vp
Vp
(3.35),(14)
iD max 1 + 2
[A]
2Vr
R
is approximately one-half that of the half-cycle peak rectifier
when Vr V p .
Whites, EE 320
Lecture 9
Page 1 of 8
Lecture 9: Limiting and Clamping Diode

Circuits. Voltage Doubler. Special Diode Types.
Well finish up our discussion of diodes in this lecture by
consider a few more applications. Well discuss limiting and
clamping circuits for diodes as well as voltage doubling circuits.
Voltage Limiting Circuits

These types of circuits are used to cap voltages between preset
limits. These are useful as voltage protection circuitry or as
signal conditioning.
Examples of such circuits are shown in text Figure 3.35:
Whites, EE 320
Lecture 9
Page 2 of 8
A simple signal conditioning example is a circuit with the

following transfer function:
Then one would see this output voltage vO for this particular
input voltage vI:
vO
vI
-1
-3
A circuit with ideal diodes can be designed to realize the above

transfer function from a combination of the concepts shown
above in Fig. 3.35:
R
+
Ideal
vI
5V
+
Ideal vO
Whites, EE 320
Lecture 9
Page 3 of 8
Clamped Capacitor Circuits

An idealized circuit of this type in shown below:
(Fig. 3.36b)
There are three important things to note about this circuit:
1. The ideal D keeps vO 0 .
2. C charges only when vI < 0 . Without a load, there is no
other path for current.
3. The vC polarity is positive as shown above.
With these insights, lets look at a specific example to illustrate
the operation of this circuit. Consider this input voltage:
(Fig. 3.36a)
C in Fig. 3.36b will eventually charge completely so that vC = +6
V. In that case, the lowest output voltage will be clamped to
zero. The output voltage will appear as:
Whites, EE 320
Lecture 9
Page 4 of 8
(Fig. 3.36c)
Hence, this is called a clamped capacitor circuit. Without the
diode present in this circuit, the capacitor would not retain any
net charge per period so it would never charge up to 6 V.
Note that here we are looking at the steady state response. It
may take a few periods for the capacitor to completely charge.
Were not looking at the transient response.
There are two applications of the clamped capacitor circuit
discussed in the text.
(a) Pulse width modulation detector. PWM is used for
motor speed control, for example. The width of the pulse
contains the information.
To demodulate the signal, one AC couples to give zero

time average voltage (i.e., 0 VDC). The signal is then
passed through a clamped capacitor circuit to give a
Whites, EE 320
Lecture 9
Page 5 of 8
well-defined DC component, then through a low pass

filter to extract the DC.
This DC voltage is the time average value, which
changes depending on the width of the pulses (if the
period is constant, as assumed).
(b) Combined clamped capacitor with peak rectifier. This
is also called a voltage doubler circuit.
+
C1
Vpcos( t)
D1
-
D2
+
vD1 C2
-
+
vO
-
Clamped
capacitor
Half-cycle peak
rectifier
Ignoring the transient behavior when the input voltage is

first applied, vD1 is:
2Vp
vD1
This voltage is fed to a half-cycle peak rectifier yielding

the output voltage:
vO
2Vp
Whites, EE 320
Lecture 9
Page 6 of 8
Its obvious now why this is called a voltage doubler

circuit.
Special Diode Types

1. Schottky barrier diode. Often just called a Schottky
diode. (Used in Laboratory #1 and in the NorCal 40A in EE
322.)
These are formed from a metal and an n-doped
semiconductor. The big difference from a silicon diode is a
smaller forward-bias voltage drop of approximately 0.2 V.
Also, because all conduction current in a Schottky diode is
carried by majority carriers (electrons) there is little to no
junction capacitance due to the absence of minority carrier
charge accumulation in the vicinity of the depletion region.
Because of this, one would expect the switching speeds of the
Schottky diodes to be faster than silicon diodes, for example
2. Varactor. A reversed biased diode acting as a voltagecontrolled capacitance. (Used in the NorCal 40A in EE 322.)
Whites, EE 320
Lecture 9
Page 7 of 8
To understand the operation of the varactor, recall that in the

pn junction:
This separated charge region acts as a capacitance. As shown

in the text, the junction capacitance can be expressed as
C j0
Cj =
(3.55),(1)
1 + VR V0
It is readily apparent from this equation that as VR changes,
so does Cj. (This model is used in Spice.)
+++
+++
+++
+++
+++
+++
+++
3. Photodiodes. This is a reversed biased pn junction

illuminated by light:
When the pn junction is exposed to incident light in the

correct frequency band(s), the incident photons can break
covalent bonds in the depletion region thus generating
electron-hole pairs. These are swept away from the junction
Whites, EE 320
Lecture 9
Page 8 of 8
by the electric field in the depletion region with e- to the n

region and holes to the p region.
Thus a reverse bias current has been generated. This is called
a photocurrent.
+
+
+
+
+
+
+
4. Light Emitting Diode (LED). This is the reverse of the

photodiode. In the LED, a pn junction is forward biased:
When electron-hole recombination occurs, light can be given

off in certain types of semiconductors such as GaAs.
Whites, EE 320
Lecture 10
Page 1 of 9
Lecture 10: Bipolar Junction Transistor

Construction. NPN Physical Operation.
For the remainder of this semester we will be studying
transistors and transistor circuits.
The transistor is a three terminal device. It is probably only the
second such device youve encountered in electrical
engineering, after the op amp. Roughly speaking, the transistor
acts an electronic valve: the node current or voltage at one
terminal controls the current entering the second terminal and
exiting the third.
It would be difficult to overstate the importance of the transistor
to electronics. Some of its uses are:
Digital logic
Memory circuits
Amplifiers
Electronic switches.
The two basic families of transistors are bipolar junction
transistors (BJTs) and field effect transistors (FETs). Well start
by discussing BJTs for approximately 13 lectures followed by
FETs for the remaining 12 lectures. BJTs are covered in Chapter
5 of your text.
Whites, EE 320
Lecture 10
Page 2 of 9
BJT Physical Structure

BJTs are formed from three doped regions on a silicon crystal.
These can either be npn doped regions or pnp. A simplified
sketch of an npn transistor is:
(Fig. 5.1)
As can be seen, the BJT is formed from two back-to-back pn
junctions:
Emitter-base junction (EBJ)
Collector-base junction (CBJ).
This specific way of drawing the BJT has been around from the
very beginning of these transistors. This figure:
is from William Shockleys U.S. patent 2,569,347 issued in

1951.
Whites, EE 320
Lecture 10
Page 3 of 9
BJTs can also be fabricated from two p-type regions and one ntype. This is called a pnp transistor:
(Fig. 5.2)
While the BJT might appear to be symmetrical by looking at
Fig. 5.1, the actual devices are not.
For example, the cross section below of an npn transistor clearly
shows that the EBJ and CBJ, for example, have very differently
sized surface contact areas, which will greatly change their
relative behaviors.
(Fig. 5.6)
There are four basic modes of operation for a BJT depending on
the states of the two pn junctions of the transistor:
Whites, EE 320
Lecture 10
Mode
Cutoff
Active
Saturation
Reverse Active
Emitter-Base Jct.
Reverse
Forward
Forward
Reverse
Page 4 of 9
Collector-Base Jct.
Reverse
Reverse
Forward
Forward
In digital logic applications, the transistor switches between the

cutoff and saturation modes. As a linear amplifier in a
communication circuit, the transistor would operate in the active
mode.
Because of the asymmetrical physical construction, the reverse
active mode is not the same as interchanging the collector and
emitter leads.
The states of the two pn junctions can be altered by the external
circuitry connected to the transistor. This is called biasing the
transistor.
NPN Transistor in the Active Mode

Well begin the discussion of the BJT physical operation by
considering an npn transistor in the active mode. To bias it in the
active mode, we need to forward bias the EBJ and reverse bias
Whites, EE 320
Lecture 10
Page 5 of 9
the CBJ (notice that the emitter and collectors have swapped
positions from Fig. 5.1 shown earlier):
(Fig. 1)
The overall objective of this circuit is to create a current flowing
from the collector to the emitter terminals in the transistor that is
controlled, so to speak, by the base voltage VBB.
How does this transistor operate in this circuit?
Because of the forward bias on the EBJ, charges can flow
across this junction giving rise to iE. This current is
primarily electrons that are injected from n to p.
The electrons injected in the base diffuse across the thin
base region towards the collector. Some of the e- recombine
in the base, but this region is manufactured to be thin and
lightly doped compared to the emitter so this recombination
is kept small. Otherwise, the BJT would just operate as two
back-to-back diodes and no current would flow.
Whites, EE 320
Lecture 10
Page 6 of 9
A representative minority carrier concentration profile is

shown below in Fig. 5.4. (Note that C and E are switched with
reference to Fig. 1 above.)
(Fig. 5.4)
The e- that reach the reverse-biased CBJ encounter a large
electric field. This E sweeps them into the collector
forming the collector current iC as shown in Fig. 1 above.
A small base current iB is present largely due to
recombination in the base with the small amount of injected
holes from the base to the emitter. This is an important
current, though.
Discussion About BJT in the Active Mode

1. The proportion of electrons from the emitter that make it to
the base is called the collector efficiency, :
Whites, EE 320
Lecture 10
Page 7 of 9
iC
or iC = iE
(5.16),(1)
iE
Typically it has values of near 0.99. Note that is called the
common-base current gain in the text.
From KCL in the circuit of Fig. 1:

iE = iB + iC
or
iB = iE iC = (1 ) iE
(5.13),(2)
(3)
We can deduce from (3) that with 1, then iB will be much,

much smaller than iE.
2. The ratio of collector current to base current is called the
current gain, :
i
C or iC = iB
(5.10),(4)
iB
3. Dividing (1) by (4) we find that
iC
=
iB 1
Equating this to (4) we find
1
and solving this equation for
=
+1
=
(5.19),(5)
(5.17),(6)
Whites, EE 320
Lecture 10
Page 8 of 9
With 0.99 100 .

4. One can think of the base current in the BJT as controlling the
collector current: iC = iB . Since is large, then a small
change in iB produces a large change in iC. If the base were an
input signal and the collector the output, then this would be
signal amplification! Awesome!
5. The circuit symbol and current conventions for the npn BJT
are
The arrows indicate the assumed directions for positive

current for the npn BJT. The filled arrow is always located on
the emitter and helps us to remember the direction of the
emitter current.
6. For biasing in the active mode as shown in Fig. 1, one biasing
circuit might be
Whites, EE 320
Lecture 10
(Fig. 5.14a)
Page 9 of 9
Whites, EE 320
Lecture 11
Page 1 of 8
Lecture 11: PNP Bipolar Junction Transistor

Physical Operation. BJT Examples.
The second type of BJT is formed from pnp doped regions as
(Fig. 5.11)
Differences between pnp and npn BJTs are:
Biasing voltages are applied oppositely to the npn, though
still forward biasing EBJ and reverse biasing the CBJ for
active mode operation, for example.
Current is primarily composed of holes (in the p type
regions) rather than electrons as in the npn BJT.
The current direction conventions are iE into the emitter
while iC and iB are out from the device.
The circuit symbol for the pnp BJT is
Whites, EE 320
Lecture 11
Page 2 of 8
Once again, the filled arrow is always located on the emitter and
helps us to remember the direction of the emitter current. Notice
that the currents are pointed in opposite directions compared to
the npn BJT.
For biasing in the active mode, a possible circuit is
(Fig. 5.14b)
As with the npn, for the pnp BJT in the active mode and with the
current convention shown above
iC = iE
(5.16),(1)
iB = (1 ) iE
iC = iB
=
+1
=
(2)
(5.10),(3)
(5.19),(4)
(5.17),(5)
Consequently, we need to only memorize this one set of

equations for use with both npn and pnp BJTs, plus the current
conventions for these two BJTs.
Whites, EE 320
Lecture 11
Page 3 of 8
Examples
Well now consider a few examples of the DC analysis of npn
and pnp BJT circuits.
Example N11.1 (text example 5.1). Design the following circuit

so that I C = 2 mA and VC = 5 V. For this particular transistor,
= 100 and VBE = 0.7 V at I C = 1 mA.
(Fig. 5.15)
The design of this circuit is to determine the RC and RE that
provide the specified IC and VC.
For IC = 2 mA, then
15 VC
15 5
= 5 k.
= 2 mA or RC =
3
2 10
RC
Whites, EE 320
Lecture 11
Page 4 of 8
Were assuming that the transistor is in the active mode with the
EBJ forward biased and the CBJ reversed biased.
For the forward biased EBJ junction,
vBE
VT
iC = I S e
(5.3),(6)
Its given that at IC = 1 mA, VBE = 0.7 V. What is VBE when IC = 2
mA? Using (6) for two different iC and vBE we find that
vBE 1 vBE 2
i
iC1
v v
= e VT
or BE1 BE 2 = ln C1
iC 2
VT
iC 2
Therefore,
i
vBE 2 = vBE1 + VT ln C1
(7)
iC 2
For this particular case,
2
VBE 2 = 0.7 + 25 103 ln = 0.717 V
1
This is not much of an increase from 0.7 V, which is what we
typically observe when the BJT is in the active mode.
VE = 0.717 V
Consequently,
Next,
then
iC = iE iE =
IE =
iC
+1
i
C
100 + 1
2 mA or I E = 2.02 mA
100
Whites, EE 320
Lecture 11
Page 5 of 8
We can use this emitter current to select the proper resistor RE:
V ( 15 V )
IE = E
RE
0.717 + 15
or
RE =
= 7.07 k
2.02 103
That completes the design.

One last thing, though. Notice how small the base current IB is
relative to IC and IE:
I B = I C I E = 20 A.
This is typical of BJTs operating in the active mode.
Example N11.2 (text exercise 5.10). Determine IE, IB, IC, and VC
in the circuit below if = 50 and VE = -0.7 V.
(Fig. E5.10)
Whites, EE 320
Lecture 11
Page 6 of 8
Because VB = 0, then the given VE means the BJT may be

operating in the active mode since VBE = 0.7 V. (It could also be
operating in the saturation mode.) Well assume active mode
operation for now, and confirm this assumption when were
finished.
(i) Compute IE.
IE =
(ii) Compute IC.
IC = I E =
0.7 ( 10 )
= 0.93 mA
10,000
+1
IE =
50
0.93 mA=0.91 mA
51
(iii) Compute IB.

IC = I B I B =
(iv) Compute VC.
IC
0.91 mA
= 18.2 A
50
VC = 10 5,000 I C = 5.45 V
Note that since VCB = VC VB = 5.45 0 = 5.45 V is greater than

zero (thus reverse biasing the CBJ) and the EBJ is forward
biased, the npn BJT is indeed operating in the active mode, as
assumed.
Whites, EE 320
Lecture 11
Page 7 of 8
Example N11.3 (text exercise 5.11). Given that VB = 1.0 V and

VE = 1.7 V, determine (and ) for the transistor in the circuit
below. Also calculate VC.
(Fig. E5.11)
Because VEB = VE VB = 0.7 V, the pnp transistor may be
operating in the active mode, which is what we will assume.
(i) Determine and . Well use the relationships iC = iE and
iC = iB to determine and .
From the circuit,

and
VB
1.0
=
= 10 A
100 103 100 103
10 1.7
IE =
= 1.66 mA
5,000
IB =
Using KCL:
I C = I E I B = 1.66 103 10 106 = 1.65 mA.
Therefore,
Whites, EE 320
Lecture 11
Page 8 of 8
I C 1.65 103
= =
= 165
6
IB
10 10
I C 1.65 103
= =
= 0.994
I E 1.66 103
and
Alternatively,
+1
= 0.994
(ii) Compute VC.
or
VC = 10 V + 5,000 I C = 10 V + 5,000 1.65 103

VC = 1.75 V.
Note that this VC means that the CBJ is reversed biased by the
voltage 1.0 ( 1.75 ) = 2.75 V. Hence, the active mode
operation for the pnp BJT is the proper assumption since weve
already determined that the EBJ is forward biased.
Whites, EE 320
Lecture 12
Page 1 of 9
Lecture 12: DC Analysis of BJT Circuits.

In this lecture we will consider a number of BJT circuits and
perform the DC circuit analysis. For those circuits with an active
mode BJT, well assume that VBE = 0.7 V (npn) or VEB = 0.7 V
(pnp).
Example N12.1 (text example 5.4). Compute the node voltages

and currents in the circuit below assuming = 100.
(Fig. 5.34a)
Well assume the device is operating in the active mode, then
well check this assumption at the end of the problem by
calculating the bias of the EBJ and CBJ.
If the BJT is in the active mode, VBE = 0.7 V then
V
3.3
VE = 4 VBE = 3.3 V and I E = E =
= 1 mA.
3
RE 3.3 10
With I C = I E then
Whites, EE 320
Lecture 12
IC =
+1
Page 2 of 9
1 mA=0.99 mA
Consequently, using KVL

VC = 10 I C RC = 10 0.99 103 4.7 103 = 5.3 V
Finally, using KCL I B + I C = I E , or
I B = I E I C = 1 0.99 = 0.01 mA
Now well check to see if these values mean the BJT is in the
active mode (as assumed).
VCB = 5.3 4 = 1.3 V. This is greater than zero, which means
the CBJ is reversed biased.
VBE = 0.7 V. This is greater than zero, which means the
EBJ is forward biased.
Because the CBJ is reversed biased and the EBJ is forward
biased, the BJT is operating in the active mode.
Note that in the text, they show a technique for analyzing such
circuits right on the circuit diagram in Fig. 5.34c. Very useful.
(Fig. 5.34c)
Whites, EE 320
Lecture 12
Page 3 of 9
Example N12.2 (text example 5.5). Repeat the previous

example but with VB = 6 V. Assuming the BJT is operating in
the active mode:
I C = I E = 0.99 1.6 mA = 1.58 mA
10 I C 4.7 k = 2.57 V
6 0.7 = 5.3 V
IE =
5.3 V
= 1.6 mA
3.3 k
From the last calculation VC = 2.57 V VCB = 3.43 V.

Consequently, the BJT is not in the active mode because the
CBJ is forward biased.
A better assumption is the transistor is operating in the
saturation mode. Well talk more about this later. For now,
suffice it to say that in the saturation mode VCE sat 0.2 V (see
Section 5.3.4).
Assuming this and reanalyzing the circuit:
Whites, EE 320
Lecture 12
IC =
Page 4 of 9
10 5.5
=0.96 mA
4700
VC = 5.3 + 0.2 = 5.5 V

I B = I E IC
= 0.64 mA
VCE
sat
= 0.2 V
6 0.7 = 5.3 V
IE =
5.3 V
= 1.6 mA
3.3 k
Notice that
I C 0.96
=
= 1.5
I B 0.64
This ratio is often called forced . Observe that its not equal to
100, as this ratio would be if the transistor were operating in the
active mode (see Section 5.3.4).
Example N12.3 (text example 5.7). Compute the node voltages

and currents in the circuit below assuming = 100. To begin,
well assume the pnp transistor is operating in the active mode.
Whites, EE 320
Lecture 12
IE =
I B = I E IC
= 0.05 mA
Page 5 of 9
10 0.7
=4.65 mA
2000
0.7 V
10 + 4.6 mA 1 k = 5.4 V
I C = I E = 0.99 4.65 mA = 4.6 mA
Now check if the BJT is in the active mode:

EBJ? Forward biased.
CBJ? Reversed biased.
So the BJT is in the active mode, as originally assumed.
Example N12.4 (text exercise D5.25). Determine the largest RC

that can be used in the circuit below so that the BJT remains in
the active mode. (This circuit is very similar to the one in the
previous example.)
Whites, EE 320
Lecture 12
Page 6 of 9
I E = 4.65 mA
0.7 V
I C = I E = 4.6 mA
Well begin by assuming the BJT is operating in the active

mode. In the active mode, the CBJ needs to be reversed biased.
The lowest voltage across this junction for operation in the
active mode is VCB = 0 VC = VB = 0 V.
Therefore, by KVL
10 + RC I C = 0
or
10
10
=
= 2,174
3
I C 4.6 10
This value of RC and smaller is required for the BJT to operate
in the active mode.
RC =
Example N12.5 (text example 5.10). Determine the node

voltages and currents in the circuit shown below. Assume the
BJT is operating in the active mode with = 100 .
Whites, EE 320
Lecture 12
Page 7 of 9
First, well use Thvenins theorem to simplify the base circuit

15 V
100 k
+
50 k
RTH
VTH
-
The Thvenin equivalent resistance and voltage are then

RTH = 100 k || 50 k = 33.33 k
50
VTH =
and
15 = 5 V
100 + 50
Using this Thvenin equivalent for the base circuit, the overall
circuit is then
Whites, EE 320
Lecture 12
Page 8 of 9
15 V
IC
5k
5V
VC
33.3 k
IB
VB
VE
KVL
3k
IE
To find the emitter current, well apply KVL over the loop
shown giving
5 = 33.3 103 I B + 0.7 + 3,000 I E
The quantity of interest is IB. With I C = I B and I C = I E for a
BJT in the active mode, we find
I
IE = C = IB =
IB

( + 1)
I E = ( + 1) I B
or
Using this in the KVL equation
5 0.7 = 33.3 103 + 3,000 ( + 1) I B
With = 100 then solving this equation we find
I B = 12.8 A I E = ( + 1) I B = 1.29 mA.
Next, by KCL
I C = I E I B = 1.29 m 12.8 A = 1.28 mA
The node voltages are then
Whites, EE 320
Lecture 12
Page 9 of 9
VC = 15 I C 5 k = 8.6 V
VE = I E 3 k = 3.87 V
VB = 5 I B 33.3 k = 4.57 V
Lastly, lets check if the BJT is operating in the active mode.

VBE = VB VE = 4.57 3.87 = 0.7 V. This is 0.7 V originally
assumed for a forward biased EBJ.
VBC = VB VC = 4.57 8.6 = 4.03 V. This is less than zero,
which means the CBJ is reversed biased.
Therefore the BJT is operating in the active mode, as originally
assumed.
Whites, EE 320
Lecture 13
Page 1 of 6
Lecture 13: The BJT as a Signal Amplifier.

One very useful application of the transistor is an amplifier of
time varying signals.
Next semester in EE 322, you will build a radio that receives
signals at power levels as low as pW and amplifies them to
power levels near 1 W!
This happens through the use of frequency selective filters and
the use of signal amplifiers formed from transistors. It is such
capabilities that make telecommunications possible.
Consider the conceptual BJT amplifier circuit shown below:
(Fig. 5.48a)
The DC voltages provide the biasing. The input signal is vbe and
the output signal is vc.
Whites, EE 320
Lecture 13
Page 2 of 6
We will assume the transistor is biased so that VC is greater than

VB by an amount that allows for sufficient signal swing at the
collector, but the transistor remains in the active mode at all
times. That is, the transistor does not become saturated or cutoff
during the cycle.
From the circuit above, the total base-to-emitter voltage is
vBE = VBE + vbe
N N
DC
(1)
AC
Correspondingly, the collector current is

iC = I S evBE VT = I S eVBE VT evbe VT

(2)
IC
or using (5.53)
iC = I C evbe VT
(5.82),(3)
For small vbe such that vbe 2VT (i.e., the small-signal
approximation), then (3) can be approximated by
v
I
iC I C 1 + be = I C + C vbe
(5.84),(4)
N
T
VT DC V
N
AC
This is a familiar result: We saw something very similar with

small signals and diodes back in Lecture 4.
The time varying current in (4)
IC
vbe
VT
(5.85),(5)
ic = g m vbe
(5.86),(6)
ic =
can be written as
Whites, EE 320
Lecture 13
Page 3 of 6
IC
[S]
(5.87),(7)
VT
is defined as the transistor small-signal transconductance. Its
units are Siemens. Note that g m I C .
gm
where
Significance of the BJT Small-Signal

Transconductance
What is the physical significance of gm? First, gm is the slope of
the iC-vBE characteristic curve at the Q point:
i
gm = C
(5.88),(8)
vBE i = I
C
Consider the plot shown in Fig. 5.49.
(Fig. 5.49)
With iC = I S evBE
vT
from (2), the right-hand side of (8) becomes
Whites, EE 320
Lecture 13
iC
I
= S evBE
vBE VT
Page 4 of 6
iC
(3) VT
(9)
IC
VT
(10)
=
N
VT
Therefore
gm =
iC
vBE
=
iC = I C
as we defined in (6).
Observe that:
The small-signal vbe assumption restricts the operation of

the BJT to nearly linear portions of the iC-vBE characteristic
curve.
From (6), the BJT behaves as a voltage controlled current
source for small signals: The small-signal vbe controls the
small-signal ic .
Signal Voltage Gain

Second, gm has an important relationship to the signal voltage
gain in this circuit. Using KVL in Fig. 5.48a, the total collector
voltage is
vC = VCC iC RC = VCC ( I C + ic ) RC
= VCC I C RC ic RC

=VC
or
vC = VC ic RC
N N
DC
AC
(5.101),(11)
Whites, EE 320
Lecture 13
Page 5 of 6
where VC is the DC voltage at the collector.

So from (11), the AC signal at the collector is
(5.102),(12)
vc = ic RC
This result is negative, which means this circuit operates as an
inverting amplifier for small, time varying signals.
From (6), ic = g m vbe . Using this result in (12) gives
vc = g mvbe RC = ( g m RC ) vbe
(5.102),(13)
Consequently, the small-signal AC voltage gain Av is
v
Av = c = g m RC
(5.104),(14)
vbe
In a broad sense, we can see that this transistor circuit can act an
amplifier of the time varying input signal, provided this input
voltage remains small enough.
V
vc = -gmRCvbe
Output (vC):
VC
Input (vBE):
vbe
VBE
t
Whites, EE 320
Lecture 13
Page 6 of 6
gm is a very important amplifier parameter since the voltage gain

in (14) is directly proportional to gm. BJTs have a relatively
large gm compared to field effect transistors, which we will
consider in the next chapter. Consequently, BJTs have better
voltage gain in such circuits.
Whites, EE 320
Lecture 14
Page 1 of 9
Lecture 14: BJT Small-Signal

Equivalent Circuit Models.
Our next objective is to develop small-signal circuit models for
the BJT. Well focus on the npn variant in this lecture.
Recall that we did this for the diode back in Lecture 4:
ID
rd =
nVT
ID
In order to develop these BJT small-signal models, there are two

small-signal resistances that we must first determine. These are:
1. r: the small-signal, active mode input resistance between

the base and emitter, as seen looking into the base.
2. re: the small-signal, active mode output resistance between
the base and emitter, as seen looking into the emitter.
These resistances are NOT the same. Why? Because the
transistor is not a reciprocal device. Like a diode, the behavior
of the BJT in the circuit changes if we interchange the terminals.
Whites, EE 320
Lecture 14
Page 2 of 9
Determine r
Assuming the transistor in this circuit
(Fig. 5.48a)
is operating in the active mode, then
i
1
IC
iB = C =
I
vbe
+
N
NC
(5.84) DC V
T
N
AC
I
g
so that
ib = C vbe = m vbe
VT
(1)
(5.90),(5.91),(2)
The AC small-signal equivalent circuit from Fig. 5.48a is
Whites, EE 320
Lecture 14
Page 3 of 9
(Fig. 1)
Notice the AC ground in the circuit. This is an extremely
important concept. Since the voltage at this terminal is held
constant at VCC, there is no time variation of the voltage.
Consequently, we can set this terminal to be an AC ground in
the small-signal circuit.
For AC grounds, we kill the DC sources at that terminal: short
circuit voltage sources and open circuit current sources.
So, from the small-signal equivalent circuit above:
(Fig. 2)
we see that
Whites, EE 320
Lecture 14
Page 4 of 9
vbe
ib
(5.92),(3)
r =
Hence, using (2) in (3)
r =
[]
(5.93),(4)
gm
This r is the BJT active mode small-signal input resistance of
the BJT between the base and the emitter as seen looking into
the base terminal. (Similar to a Thvenin resistance, this
statement means we are fictitiously separating the source from
the base of the BJT and observing the input resistance, as
indicated by the dashed line in Fig. 2.)
Determine re
Well determine re following a similar procedure as for r, but
beginning with
i
I
i
(5)
iE = C = C + c
N

N
DC
AC
The AC component of iE in (5) is

i
IC
ie = c =
vbe
N
(5.85) VT
(5.96),(6)
or with I E = I C ,
ie =
IE
vbe
VT
(5.96),(7)
Whites, EE 320
Lecture 14
Page 5 of 9
As indicated in Fig. 1 above, re is the BJT small-signal

resistance between the emitter and base seen looking into the
emitter:
Mathematically, this is stated as
ve
(8)
ie
Assuming an ideal signal voltage source, then ve = vbe and
v
re be
(5.97),(9)
ie
Using (7) in this equation we find
V
(5.98),(10)
re = T
IE
But from (5.87)
I
I
V
gm = C = E T =
I E gm
VT
VT
re
Therefore, using this last result in (10) gives
Whites, EE 320
Lecture 14
Page 6 of 9
1
[]
(5.99),(11)
gm gm
This is the BJT active mode small-signal resistance between the
base and emitter seen looking into the emitter.
re =
It can be shown that
r = ( + 1) re []
(5.100),(12)
It is quite apparent from this equation that r re . This result is

not unexpected because the active mode BJT is a non-reciprocal
device, as mentioned on page 1 of these notes.
BJT Small-Signal Equivalent Circuits

We are now in a position to construct the equivalent active
mode, small-signal circuit models for the BJT. There are two
families of such circuits:
1. Hybrid- model
2. T model.
Both are equally valid models, but choosing one over the other
sometimes leads to simpler analysis of certain circuits.
Hybrid- Model
Version A.
Whites, EE 320
Lecture 14
Page 7 of 9
(Fig. 5.51a)
Lets verify that this circuit incorporates all of the necessary
small-signal characteristics of the BJT:
9 ib = vbe r as required by (3).
9 ic = g m vbe as required by (5.86), which we saw in the last
lecture.
9 ib + ic = ie as required by KCL.
We can also show from these relationships that ie = vbe re .
Version B. We can construct a second equivalent circuit by

using
g m vbe =
g m r ib = ib
N g m ( ib r ) = N
(3)
(4)
Hence, using this result the second hybrid- model is
(Fig. 5.51b)
Whites, EE 320
Lecture 14
Page 8 of 9
T Model
The hybrid- model is definitely the most popular small-signal
model for the BJT. The alternative is the T model, which is
useful in certain situations.
The T model also has two versions:
Version A.
(Fig. 5.52a)
Version B.
Whites, EE 320
Lecture 14
Page 9 of 9
(Fig. 5.52b)
The small-signal models for pnp BJTs are identically the same
as those shown here for the npn transistors. It is important to
note that there is no change in any polarities (voltage or current)
for the pnp models relative to the npn models. Again, these
small-signal models are identically the same.
Whites, EE 320
Lecture 15
Page 1 of 10
Lecture 15: BJT Small-Signal

Amplifier Examples.
We will now consider three examples in this lecture of BJTs
used as linear amplifiers. Here are the steps to follow when
solving small-signal transistor amplifier problems:
1. Determine the Q point of the BJT using DC analysis.
Compute IC.
2. Calculate the small-signal model parameters for the BJT:
I
g m = C , and
(5.87),(1)
VT
r =
gm
, or
(5.93),(2)
VT
(5.99),(3)
gm I E
3. Rewrite the small-signal circuit: short out DC sources and
open DC current sources. Use the small-signal model for
the BJT.
4. Analyze the small-signal circuit for the desired quantities
such as voltage, small-signal voltage gain, etc.
re =
Example N15.1 (text example 5.14). Determine the small-signal

AC voltage gain for the circuit below, assuming = 100 and the
output voltage taken at the collector terminal.
Whites, EE 320
Lecture 15
Page 2 of 10
(Fig. 5.53a)
The first step in the solution is to determine the Q point through
DC analysis. By superposition, well force vi = 0 for this
analysis.
Assuming the BJT is in the active mode, the results of the DC
analysis are:
(Fig. 5.53b)
We see that the CBJ is reversed biased so this npn BJT is in the
active mode because of this and the EBJ is forward biased.
Next, we determine the BJT small-signal model parameters for
the hybrid- model:
Whites, EE 320
Lecture 15
Page 3 of 10
I C 2.3 103
From (1), g m =
=
= 0.092 S
3
VT 25 10
100
From (2), r =
=
= 1,087
g m 0.092
Now, we insert a small-signal equivalent model of the BJT into
the circuit of Fig. 5.53(a) after shorting the DC voltage sources
(VBB and VCC). This gives the small-signal equivalent circuit:
(Fig. 5.53c)
Notice the AC ground at RC. This is an AC ground because
the voltage at this node does not vary with time. For the
purposes of the AC signal analysis, we can set this node to an
AC ground. (As a side note, in the lab power supplies have a
finite internal resistance. This Thvenin equivalent resistance
must be included in the AC circuit for analysis purposes.)
Next, we perform the small-signal analysis referring to Fig.
5.53c. At the input
r
(5.105),(4)
vbe =
vi
r + RBB
while at the output
vo = RC ic = RC g m vbe
(5)
Substituting for vbe from (4) gives
Whites, EE 320
Lecture 15
r
vi
r + RBB
Therefore, the small-signal AC voltage gain, Av, is
v
r
Av = o = RC g m
vi
r + RBB
vo = RC g m
Page 4 of 10
(6)
(7)
For this particular problem

1,087
1,087 + 100,000
Av = 2.97 V/V
Av = 3,000 0.092
or
The negative sign indicates this is an inverting amplifier: the AC

output signal is inverted with respect to the input AC signal.
Example N15.2 (text example 5.15). Repeat the analysis of the

previous example but with a triangular input waveform of small
amplitude.
In the text, vi , p = 0.8 V is the peak amplitude of the triangular

input voltage (=Vi in the text).
Then from (4) above (and the fact that there are only resistors in
the circuit)
r
0.8 = 8.60 mV
vbe =
r + RBB
Whites, EE 320
Lecture 15
Page 5 of 10
which is less that 10 mV. This is fairly small with respect to

2VT = 50 mV so well go ahead and use the small-signal analysis
and models.
Sketches of the total voltages and currents from this circuit are
shown in Fig. 5.54:
Whites, EE 320
Lecture 15
Page 6 of 10
A few things to take special notice:

In Fig. 5.54c, vBE has a DC part and an AC part (see Fig.
5.54a) that is riding on the former. Notice the enlarged
vertical scale in Fig. 5.54c.
In Fig. 5.54d, iC is in-phase with the input voltage.
In Fig. 5.54e, vC = VC iC RC is 180 out-of-phase with the
input. As vi , iC vC . We can see how the AC
ground works here.
Example N15.3 (text example 5.16). Determine the small-signal

AC voltage gain for the BJT amplifier circuit shown in Fig.
5.55a.
Whites, EE 320
Lecture 15
Page 7 of 10
(Fig. 5.55a)
The two capacitors in this circuit serve as DC blocks. They have
a large enough C so that X C 0 at the operating frequency.
With these capacitors, the DC bias is unchanged by the source or
load attachments. We call this capacitively coupled input and
output.
As always, we first determine the DC bias. Well assume the
BJT is in the active mode and that = 100:
(Fig. 5.55b)
From this result
Whites, EE 320
Lecture 15
Page 8 of 10
I C = 0.92 mA VC = 10 + I C RC = 5.4 V
Since VC < VB (and VEB = 0.7 V), the pnp BJT is operating in the
active mode.
Next, we construct the small-signal equivalent circuit and

analyze the circuit to determine the voltage gain. Well use the T
model, though the hybrid- model would work as well.
(Fig. 5.55c)
Notice the two AC grounds in this circuit: one at RE and the
other at RC.
Also notice this is the first small-signal model of the pnp
transistor we have used. The small-signal model of the pnp
transistor is exactly the same as that for the npn with no change
in the polarities of the currents or voltages. This can be a little
confusing. Here, for example, ie is a negative quantity.
Using (3) for the small-signal equivalent model of the BJT
VT
25 103
re =
=
= 26.9
3
I E 0.93 10
Whites, EE 320
Lecture 15
From the small-signal AC circuit:

vo = ie RC
Because the base is grounded, ie = vi re .
Therefore,
v
v
R
vo = RC i Av = o = C
vi
re
re
Page 9 of 10
(8)
(9)
(10)
Notice that this small-signal voltage gain is a positive quantity.

The reason for this is the input is tied to the emitter. (Note that
this positive gain did not occur just because this is a pnp BJT.)
Now, with = 0.99 then from (10)
5,000
Av = 0.99
= 184.0 V/V.
26.9
Lastly, for linear operation of this amplifier, veb 3 10 mV. With
veb = vi then vi 3 10 mV for linear operation of the amplifier,
which implies that vo 3 1.8 V.
A sketch of the output from this small-signal amplifier is shown
in Fig. 5.57 for a sinusoidal input voltage:
Whites, EE 320
Lecture 15
Page 10 of 10
Were assuming the output remains linear and the BJT in the
active mode at all times for the entire voltage swing in vC.
If this input voltage were set to a larger value, this would no
longer be the case and the BJT would first encounter nonlinear
behavior and eventually saturate. Both of these effects would
distort the output voltage and it would no longer be an amplified
copy of the input voltage.
Whites, EE 320
Lecture 16
Page 1 of 7
Lecture 16: Graphical Analysis of a BJT

Small-Signal Amplifier.
We can use graphical analysis to approximately analyze the
response of simple transistor amplifier circuits. This technique is
primarily useful to develop physical insight.
Consider once again the conceptual BJT amplifier circuit:
(Fig. 5.27)
Similar to the analytical solution, there are two primary steps to
the graphical solution of such small-signal amplifiers:
1. DC basis analysis
2. AC small-signal analysis.
DC Bias
The first step in the bias calculations is to determine IB. This is
done with the iB-vBE characteristic curve and the load line:
Whites, EE 320
Lecture 16
VBB = I B RB + VBE
Page 2 of 7
IB =
VBE VBB
+
RB RB
(Fig. 5.28)
Once IB has been determined we can compute IC knowing that
I C = I B for a BJT in the active mode. With this IC value and
the iC-vCE characteristic curve of the transistor, we can determine
VCE.
We havent yet seen the iC-vCE characteristic curve of the BJT.
This can be measured using the circuit in Fig. 5.19(a) below. vBE
is fixed at some value, then vCE is swept while measuring iC. The
results are shown below for different values of vBE.
(Fig. 5.19)
Whites, EE 320
Lecture 16
Page 3 of 7
When vCE is very small, iC is nearly zero. This is the cutoff mode
of the BJT. As vCE increases, the CBJ is forward biased and the
BJT is in the saturation mode. When vCE becomes large enough,
the CBJ becomes reversed biased and the BJT enters the active
mode.
The slopes of the lines in Fig. 5.19 in the active mode are quite
exaggerated in this figure.
So, back to the graphical solution. With the I C = I B value from
Fig. 5.28 and the iC-vCE characteristic curve of the transistor
from Fig. 5.19, we can determine VCE:
VCC = I C RC + VCE
IC =
VCE VCC
+
RC RC
(Fig. 5.29)
Curve tracers are pieces of equipment that will measure and
display families of iC-vCE characteristic curves for transistors.
Whites, EE 320
Lecture 16
Page 4 of 7
AC Small-Signal Analysis
The first step in the AC small-signal analysis is to determine ib.
This is performed using a slightly complicated interaction of the
input waveform vi, the subsequent time variation of the load
line, and the iB-vBE characteristic curve of the BJT:
(Fig. 5.30a)
From this comes the small-signal quantities vbe and ib.
With ib known and ic = ib , then we use these values on the iCvCE characteristic curve to determine vce:
Whites, EE 320
Lecture 16
Page 5 of 7
(Fig. 5.30b)
Cutoff and Saturation

Notice that there are limits on vCE in which the BJT remains in
the active mode:
Too large ( VCC ) and the BJT cuts off
Too small (few tenths of a volt) and the transistor saturates.
These limits are readily apparent if we reexamine the previous
figure of the small-signal variation:
Whites, EE 320
Lecture 16
Page 6 of 7
(Fig. 5.30b)
Because of these limits on vCE, it is important to choose the Q
point properly to all for the desired swing in the signal voltage
(vce).
Whites, EE 320
Lecture 16
Better
compromise
Page 7 of 7
Perhaps not enough room

for positive excursions of
vce (BJT cuts off).
Perhaps not enough room

for negative excursions of
vce (BJT saturates).
(Fig. 5.31)
Whites, EE 320
Lecture 17
Page 1 of 10
Lecture 17: BJT Biasing. Current Mirror.

It is important for the biasing of a transistor amplifier that it
remains largely invariant to fairly large changes in and
temperature.
Proper biasing doesnt happen by chance. For example, the npn
and pnp inverter circuits in Laboratory #3 are highly sensitive to
variations in . That is usually a poor design (but was done on
purpose for the lab, of course).
In this lecture, we will study four BJT biasing methods:
1. Single power supply
2. Dual power supply
3. Alternate method for common emitter amplifiers
4. Current source.
Single Power Supply Biasing Method

Perhaps the most common method for biasing BJT amplifier
circuits with a single power supply is shown in Fig. 5.44:
Whites, EE 320
Lecture 17
Page 2 of 10
(Fig. 5.44a)
RE is part of this biasing method as well. When used as an
amplifier, the input signal would be capacitively coupled to the
base of the BJT while the output would be taken (through
capacitive coupling) at the collector or emitter of the transistor,
depending on the specific requirements for the amplifier.
We analyzed a specific example of this type of circuit in Lecture
12 employing Thvenins theorem to simplify the analysis:
IE
(Fig. 5.44b)
where VBB and RB are given in (5.68) and (5.69) in the text.
Whites, EE 320
Lecture 17
Page 3 of 10
Using KVL in the loop shown above

VBB = I B RB + VBE + I E RE
With I B = I E ( + 1) then (1) becomes
R
R
VBB = VBE + B I E + RE I E = VBE + B + RE I E
+1
+1
Consequently,
IE =
VBB VBE
R
RE + B
+1
(1)
(2)
(5.70),(3)
We can use (3) to design the biasing circuit so that it is largely

insensitive to variations in . The question is then how do we
make IE (and hence IC) largely insensitive to variations?
Examining (3), we deduce that the answer is to choose
R
RE B
(5.72),(4)
+1
Furthermore, we can design this biasing circuit so that it is
largely insensitive to variations in temperature. The effects of
temperature enter this circuit because VBE is a relatively strong
function of temperature having a temperature coefficient of -2
mV/C. (We saw this same behavior with diodes.)
From (3) we can see that if we choose
VBB VBE
(5.71),(5)
Whites, EE 320
Lecture 17
Page 4 of 10
then well have a biasing circuit design that is largely insensitive

to variations in temperature.
So physically how do these conditions (4) and (5) make a good
biasing circuit?
Eqn. (4) makes the base voltage largely independent of
and determined almost solely by R1 and R2. How? Because
the current in the divider is much greater than the base
current. The rule of thumb for much greater is that the
divider current should be on the order of IE to IE/10.
Eqn. (5) ensures that small variations in VBE (from its
nominal 0.7 V) due to temperature changes are much
smaller than VBB.
Additionally, there is an upper limit to VBB because a higher VBB
lowers VCB and affects the small values of the positive signal
swing. The rule of thumb here is that VBB VCC 3 and VCB (or
VCE) VCC 3 , and I C RC VCC 3 .
Example N17.1. Design the bias circuit below for VCC = 9 V to

provide VCC/3 V across RE and RC, IE = 0.5 mA, and the voltage
divider current of 0.2IE, as shown. Design the circuit for a large
, then find the actual value obtained for IE with a BJT having
= 100 .
Whites, EE 320
Lecture 17
Page 5 of 10
VCC
3
0.2 I E
VCC
3
0.5 mA
For the resistors RE and RC, I E RE = VCC 3 = 3 V. For IE = 0.5

mA, then RE = 6 k. For large , then I C I E . For
I C RC = VCC 3 = 3 V, then RC = 6 k.
For the voltage divider, if this BJT is in the active mode then
VBE 0.7 V. Hence,
VB = VBE + VE = 0.7 + 3 = 3.7 V
such that
V
3.7
R2 = B =
= 37 k
0.2 I E 0.2 0.5 mA
A large for a BJT in the active mode implies I B 0 . By

Ohms law
VCC
= 0.2 I E or R1 + R2 = 90 k
R1 + R2
Hence,
R1 = 90 k R2 = 53 k
Whites, EE 320
Lecture 17
Page 6 of 10
For the design with = 100 it can be shown that I E = 0.48 mA.
(This is only a -4% change from 0.5 mA with = .)
Dual Power Supply Biasing Method

When two power supplies are available, a possible biasing
method is
(Fig. 5.45)
Using KVL around the loop L gives
IE
R + V + I R = +VEE
(6)
+ 1 B BE E E
V VBE
(5.73),(7)
or
I E = EE
RB
RE +
+1
This is the same result as (3), but with VBB replaced by VEE.
Consequently, the - and temperature-invariant design equations
for this circuit are the same as those given earlier in (4) and (5)
with VBB replaced by VEE.
Whites, EE 320
Lecture 17
Page 7 of 10
Alternative Biasing for Common Emitter Amplifiers

This biasing method has a resistor tied from the collector to the
base as
(Fig. 5.46a)
As shown in the text, for IE to be insensitive to variations,
choose
R
RC B
(8)
+1
and for VBE to be insensitive to temperature variations, choose
VCC VBE
(9)
This latter requirement is most often very easy to meet!
Biasing with a Current Source

The last BJT amplifier biasing method well consider is one
using a current source.
Whites, EE 320
Lecture 17
Page 8 of 10
(Fig. 5.47a)
In this circuit, I E = I . If we are using a good current source,
then IE will not depend on . Very nice.
However, what weve done in this approach is to push the
technical problem to the design of a good current source.
Current Mirror
Simple biasing methods often fail to provide constant collector
currents if the supply voltage or ambient temperature change.
This is a problem with mobile telephones, for example, where
the battery voltage changes with use and the device operates in a
range of temperatures.
There are sophisticated circuits consisting of tens of devices that
can produce golden currents that are supply voltage and
temperature independent. These golden currents are replicated
throughout a device using a current mirror:
Whites, EE 320
Lecture 17
Page 9 of 10
0
0 0
(Fig. 5.47b)
There are better and more sophisticated approaches than this, of
course. This is just a simple example.
In this current mirror, Q1 is called a diode-connected BJT
because the collector and base terminals are connected together.
For proper operation of this circuit, it is very important that the
BJTs be matched, meaning they having the same ,
characteristic curves, etc. Usually this means that the BJTs must
be fabricated at the same time on the same substrate.
For the analysis of this circuit, we assume that is very large
and that Q1 and Q2 operate in the active mode. Because of this,
we ignore the base currents in Q1 and Q2.
Therefore, the collector (and emitter) current through Q1 is
approximately equal to IREF. By KVL,
VCC = I REF R + VBE VEE
1
I REF = (VCC VBE + VEE )
(5.76),(10)
or
R
Whites, EE 320
Lecture 17
Page 10 of 10
Now, since Q1 and Q2 are matched and they have the same VBE,
then the collector currents must be the same. This implies that
V + VEE VBE
I = I REF = CC
(5.77),(11)
R
This current mirror circuit will supply this current I as long as
Q2 operates in the active region:
V > VBE VEE
Notice that the diode-connected Q1 cannot saturate since the
base and collector terminals are shorted together. Hence, Q1
operates in the active mode or is simply cutoff.
Whites, EE 320
Lecture 18
Page 1 of 7
Lecture 18: Common Emitter Amplifier.

We will now begin the analysis of the three basic types of linear
BJT small-signal amplifiers:
1. Common emitter (CE)
2. Common base (CB)
3. Common collector (CC), which is oftentimes called the
emitter follower amplifier.
Well study the CE amplifier in this lecture and the next,
followed by the CB and CC amplifiers.
The CE amplifier is excited at the base of the BJT with the
output taken at the emitter:
(Fig. 5.60a)
The capacitor CE is called a bypass capacitor. At the operating
frequency, its purpose is to shunt out the effects of the DC
current source from the time varying signal. In other words, CE
sets an AC ground at this node at the frequency of operation.
Whites, EE 320
Lecture 18
Page 2 of 7
There are a number of ways to bias this amplifier, other than that
shown above. What were primarily interested in here is the
small-signal characteristics.
Common Emitter Small-Signal Amplifier Analysis

The small-signal equivalent circuit for the CE amplifier above is
shown below. Because the emitter is located at an AC ground is
the reason this type of amplifier is called a common emitter
amplifier.
(Fig. 5.60b)
Notice that weve included ro in this small-signal model. This is
the finite output resistance of the BJT. This accounts for the
finite slope of the characteristic curves of iC versus vCE
mentioned briefly in Lecture 16:
Whites, EE 320
Lecture 18
Page 3 of 7
(Fig. 5.19b)
where VA is called the Early voltage. Usually ro is fairly large, on
the order of many tens of k.
Our quest in the small-signal analysis of this amplifier is to
determine these quantities: input resistance Rin, the overall
small-signal voltage gain Gv = vo vsig , the partial small-signal
voltage gain Av = vo vi , the overall small-signal current gain
Gi = io ii , the short circuit small-signal current gain Ais = ios ii ,
and the output resistance Rout.
Input resistance, Rin. Directly from the small-signal equivalent
circuit, we see that
Rin = RB || r
(5.109),(1)
Oftentimes we select RB r so that
Rin r
r will often be a few k, which means this CE amplifier
presents a moderately large value of input impedance.
Whites, EE 320
Lecture 18
Page 4 of 7
Overall small-signal voltage gain, Gv. By overall voltage

gain we mean
v
Gv o
(2)
vsig
which is the actual small-signal voltage gain that would be
realized in the circuit above. At the output of this circuit
vo = g m v ( ro || RC || RL )
(3)
while at the input
vi = v =
r || RB
vsig
r || RB + Rsig
(5.113),(4)
Substituting (4) into (3) gives an expression for the overall

(i.e., realized) gain of this CE amplifier
g m ( r || RB )
vo
Gv =
=
( ro || RC || RL ) (5.121),(5)
vsig ( r || RB ) + Rsig
In the usual case that RB r , then
( ro || RC || RL )
Gv
r + Rsig
(5.122),(6)
Recall that r = g m . If it also turned out Rsig r , then we

see from (6) that Gv would be directly dependent on . This is
not a favorable condition since, as we learned when
discussing biasing of such BJT circuits, can vary
considerably between transistors.
Partial small-signal voltage gain, Av. This is only a partial
voltage gain since we are calculating
Whites, EE 320
Lecture 18
vo
vi
At the input, vi = v while at the output,
vo = g m v ( ro || RC || RL )
Av
Page 5 of 7
(7)
(8)
Therefore, the partial small-signal voltage gain is

Av = g m ( ro || RC || RL )
(5.116),(9)
Overall small-signal current gain, Gi. By definition

i
(10)
Gi o
ii
Referring to the small-signal equivalent circuit shown above,
we see that
v
v
ii = i and io = o
Rin
RL
Forming the ratio of these two currents, we find that the
current gain is
i
R v
Rin
r || RB
=
Gi = o = in o =
A
Av
N
v N
ii RL vi (7) RL (1) RL
or, using (9)
Gi =
g m ( r || RB )( ro || RC || RL )
RL
(11)
Short circuit small-signal current gain, Ais. This is the smallsignal current gain of the amplifier but with a short circuited
load ( RL = 0 ):
Whites, EE 320
Lecture 18
Page 6 of 7
ios
ii
(5.124),(12)
Ais
Equivalently,
Ais = Gi
(13)
RL = 0
Using (11) in (13) with RL 0 gives

Ais = g m ( r || RB )
(5.124),(14)
In the usual case that RB r then

Ais
(15)
This result is not unexpected because is by definition the
short circuit current gain for the BJT when operating in the
active mode.
Output resistance Rout. Using the small-signal equivalent
circuit above, we short out the source vsig = 0 which means
that v = 0 as well. Therefore, g m v = 0 , which is an open
circuit for a current source.
Consequently,
Rout = RC || ro
which is generally fairly large.
Summary of CE Amplifier Characteristics

Summary for the common emitter amplifier:
9 Big voltage and current gains are possible.
(16)
Whites, EE 320
Lecture 18
Page 7 of 7
9 Input resistance is moderately large.

9 Output resistance is fairly large.
This last characteristic is often not desirable. Why? Consider

this simple Thvenin equivalent for the output of a small-signal
amplifier:
The output signal voltage provided to this resistive load is

RL
vo =
vout
(17)
RL + Rout
Now, if Rout RL then
R
vo L vout
(18)
Rout
This is not a favorable result if this Thvenin equivalent circuit
is for an amplifier because the output voltage is being
attenuated. Conversely, if there were a small output resistance
such that Rout RL then (17) becomes
vo vout
(19)
which is much more favorable for an amplifier.
Whites, EE 320
Lecture 19
Page 1 of 10
Lecture 19: Common Emitter Amplifier

with Emitter Degeneration.
Well continue our discussion of the basic types of BJT smallsignal amplifiers by studying a variant of the CE amplifier that
has an additional resistor added to the emitter lead:
(Fig. 5.61a)
This is called emitter degeneration and has the effect of
greatly enhancing the usefulness of the CE amplifier.
Well calculate similar amplifier quantities for this circuit as
those in the previous lecture for the CE amplifier.
In contrast to the previous lecture, well use a T small-signal
model (Re in series with re) for the BJT and well also drop ro: it
turns out to have little effect here but complicates the analysis.
Whites, EE 320
Lecture 19
Page 2 of 10
(Fig. 5.61b)
Input resistance, Rin. From this circuit, we see directly that the
input resistance at the base Rib is defined as
v
(1)
Rib i
ib
Notice that here vi v , unlike the CE amplifier w/o emitter
degeneration. Referring to the small-signal circuit we see that
vi = ie ( re + Re )
(2)
i
(3)
ib = e
and
+1
Substituting these into (1) gives
Rib = ( + 1) ( re + Re )
(5.127),(4)
We see from this expression that the base input resistance is
+1 times the total resistance in the emitter circuit. This is
called the resistance reflection rule.
[In the previous lecture, we see in Fig. 5.60(b) that
Whites, EE 320
Lecture 19
Page 3 of 10
Rib = r
but r = ( + 1) re , which obeys this resistance reflection rule
since there is no Re in that circuit.]
This base input resistance can be much larger than without the
emitter resistance. Thats often a good thing. The designer can
change Re to achieve a desired input resistance [> (+1)re].
The total input resistance to this CE amplifier with emitter
degeneration is then
Rin = RB || Rib = RB || ( + 1) ( re + Re ) (5.125),(5)
Small-signal voltage gain, Gv. Well first calculate the partial

voltage gain
v
(6)
Av o
vi
At the output,
vo = ie ( RC || RL )
(7)
Substituting for ie from (2) gives
( RC || RL )
Av =
re + Re
(5.129),(8)
The overall (from the input to the output) small-signal voltage

gain Gv is defined as
v
Gv o
(9)
vsig
Whites, EE 320
Lecture 19
We can equivalently write this voltage gain as

v v
vi
Gv = i o =
Av
N
vsig vi ( 6) vsig
Page 4 of 10
(10)
with Av given in (8).

By simple voltage division at the input to the small-signal
equivalent circuit
Rin
vi =
vsig
(11)
Rin + Rsig
Substituting this result and (8) into (10) yields the final
expression for the overall small-signal voltage gain
( RC || RL ) Rin
v
Gv = o =
(12)
vsig
re + Re
Rin + Rsig
Using Rin in (5) and assuming RB Rib then (12) simplifies to
( RC || RL )
Gv
(5.135),(13)
Rsig + ( + 1) ( re + Re )
Notice that this gain is actually smaller than the CE amplifier
without emitter degeneration [because of the (+1)Re term in
the denominator]. However, because of this term it can be
shown that the gain is less sensitive to variations in .
i
Gi o
ii
(14)
Whites, EE 320
Lecture 19
Page 5 of 10
Using current division at the output of the small-signal

RC
RC
io =
ic =
ie
(15)
RC + RL
RC + RL
while at the input
RB
ib =
ii
(16)
RB + Rib
Substituting ie = ( + 1) ib and (16) into (15) gives
RC
R
io =
( + 1) B ii
RC + RL
RB + Rib
or
RB RC
(17)
Gi =
( RC + RL )( RB + Rib )
Short circuit current gain, Ais. In the case of a short circuit
load (RL = 0), Gi reduces to the short circuit current gain:
RB
(18)
Ais =
RB + Rib
In the usual circumstance when RB Rib , then
Ais
(19)
which is the same value as for a CE amplifier since there is no
Re in this expression.
Output resistance, Rout. Referring to the small-signal
equivalent circuit above and shorting out the input vsig = 0
Rout = RC
(20)
Whites, EE 320
Lecture 19
Page 6 of 10
which is the same as the CE amplifier (when ignoring ro).
Example N19.1 (based on text exercise 5.44). Given a CE

amplifier with emitter degeneration having Rsig = RL = 5 k.
The circuit is biased as in Exercise 5.41:
(Fig. E5.41a)
The small-signal equivalent circuit for this CE amplifier with
emitter degeneration is the same as that shown in the previous
lecture:
Whites, EE 320
Lecture 19
Page 7 of 10
(Fig. 5.61b)
With I E = 1 mA, then re = VT I E = 25 mV 1 mA = 25 .
Find the value of Re that gives Rin = 4 Rsig = 20 k. From (5)
Rin = RB || Rib , which implies that Rib = 25 k. Using (4)
R
Rib = ( + 1) ( re + Re ) re + Re = ib
+1
R
25,000
25 = 222.5
Re = ib re =
or
101
+1
Determine the output resistance. From (20),
Rout = RC = 8 k
Compute the overall small-signal voltage gain. Using (12)
( RC || RL ) Rin
v
Gv = o =
vsig
re + Re
Rin + Rsig
Gv =
0.99 ( 3,080 )
20,000
= 9.86 V/V
25 + 222.5 20,000 + 5,000
Whites, EE 320
Lecture 19
Page 8 of 10
Determine the open circuit small-signal voltage gain, Gvo.

This is the overall gain but with an open circuit load. Hence,
from this description we can define
Gvo = Gv R =
L
Using (12) once again but with RL = gives for the CE

amplifier with emitter degeneration
RC Rin
(21)
Gvo =
( re + Re ) ( Rin + Rsig )
For this particular amplifier
0.99 8,000 20,000
Gvo =
= 25.6 V/V
( 25 + 222.5)( 20,000 + 5,000 )
Note that this is not the same open circuit gain Avo used in the
text. Avo is the partial open circuit voltage gain
Avo = Av R =
L
which using (8) is

Avo =
RC
re + Re
(5.131),(22)
For this amplifier
0.99 8,000
= 32 V/V
25 + 222.5
Can you physically explain why Gvo and Avo are different
values?
Avo =
Compute the overall current gain and the short circuit current
gain. Using (17)
Whites, EE 320
Gi =
=
Lecture 19
Page 9 of 10
RB RC
( RC + RL )( RB + Rib )
100 100,000 8,000
= 49.2 A/A
(8,000 + 5,000 )(100,000 + 25,000 )
For the short circuit current gain, we use (18)

RB
100 100,000
=
= 80 A/A
Ais =
RB + Rib 100,000 + 25,000
If v is limited to 5 mV, what is the maximum value for vsig
with and without Re included? Find the corresponding vo. To
address this question, we need an expression relating vsig and
v. From (11) we know that
Rin
(11)
vi =
vsig
Rin + Rsig
while at the input to the small-signal equivalent circuit above

re
(23)
v =
vi
re + Re
Substituting (11) into (23) gives
R + Rsig re + Re
vsig = in
v
(24)
Rin
re
With v = 5 mV, then
20,000 + 5,000 25 + Re
5 mV
vsig =
20,000
25
or
vsig = 0.25 ( 25 + Re ) mV
(25)
Whites, EE 320
Lecture 19
Page 10 of 10
If Re = 0, then from (25) vsig = 6.25 mV is the maximum input

signal voltage and because Gv = 9.86 V/V, the
corresponding output voltage is vo = Gv vsig = 61.6 mV. If Re
= 222.5 , then from (25) vsig = 61.9 mV is the maximum
input signal voltage and the corresponding output voltage is
vo = 610.1 mV.
This is a demonstration of yet another benefit of emitter
degeneration: the amplifier can handle larger input signals
(and hence potentially larger output voltages) without
incurring nonlinear distortion.
Whites, EE 320
Lecture 20
Page 1 of 5
Lecture 20: Common Base Amplifier.

We will cover the second of the three families of BJT amplifiers
in this lecture by discussing the common base amplifier shown
in Fig. 5.62a:
(Fig. 5.62a)
The small-signal equivalent circuit for this amplifier is shown in
Fig. 5.62b (ignoring ro):
(Fig. 5.62b)
Whites, EE 320
Lecture 20
Page 2 of 5
As before, lets determine the small-signal AC characteristics of

this amplifier by solving or Rin, Gv, Gi, Ais, and Rout.
Input resistance, Rin. From direct inspection of the smallsignal equivalent circuit, we see that
(5.137),(1)
Rin = re
Since re is often small (on the order of 20 to 30 ), then Rin of
the CB amplifier is very small. Generally this is not desirable,
though in the case of certain high frequency amplifiers input
impedances near 50 is very useful (to reduce so-called
mismatch reflections at the input).
voltage gain
v
(2)
Av o
vi
At the output,
vo = ie ( RC || RL )
(3)
The small-signal emitter current is
v
(4)
ie = ii = i
re
Substituting (3) and (4) into (2) gives the partial voltage gain
to be
Av =
re
( RC || RL ) = g m ( RC || RL )
(5.138),(5)
Whites, EE 320
Lecture 20
Page 3 of 5
This is the same gain as for the CE amplifier (without ro),

except the gain here for the CB amplifier is positive.
v
Gv o
(6)
vsig
v v
vi
Gv = i o =
Av
N
vsig vi ( 2) vsig
(7)

equivalent circuit
Rin
(8)
vi =
vsig
Rin + Rsig
Substituting this result and (5) into (7) yields the final
expression for the overall small-signal voltage gain
( RC || RL ) Rin
(9)
Gv =
re
Rin + Rsig
Since from (1) Rin = re then Gv simplifies to
( RC || RL )
Gv =
re + Rsig
(5.142),(10)
If 1, we can interpret this small-signal overall voltage

expression in (10) as the ratio of the total resistance in the
collector lead to the total resistance in the emitter lead. This
Whites, EE 320
Lecture 20
Page 4 of 5
gain can be fairly large, though if Rsig is nearly the same size
as the total emitter resistance the gain will be small. In other
words, if this amplifier is connected to a high output
impedance stage, it will be difficult to realize high gain.
i
(11)
Gi o
ii
RC
RC
(12)
io =
ic =
ie
RC + RL
RC + RL
Because ii = ie this expression gives
i
RC
(13)
Gi = o =
ii RC + RL
load (RL = 0), Gi in (13) reduces to the short circuit current
gain:
i
(5.140),(14)
Ais = os =
ii
Output resistance, Rout. Referring to the small-signal
equivalent circuit above and shorting out the input vsig = 0
Rout = RC
(15)
which is the same as the CE amplifier (when ignoring ro).
Whites, EE 320
Lecture 20
Page 5 of 5
Summary
Summary of the CB small-signal amplifier:
1. Low input resistance.
2. Gv can be very large, though critically dependent on Rsig.
3. Ais=
4. Potentially large output resistance (dependent on RC).
One very important use of the CB amplifier is as a unity-gain
current amplifier, which is also called a current buffer amplifier.
This type of amplifier accepts an input signal current at a low
impedance level and outputs nearly the same current amplitude,
but at a high output impedance level. Even though this is a
buffer amplifier, there is still power gain.
Whites, EE 320
Lecture 21
Page 1 of 9
Lecture 21: Common Collector

(Emitter Follower) Amplifier.
The third, and final, small-signal BJT amplifier we will consider
is the common collector amplifier shown below:
(Fig. 5.63a)
The small-signal equivalent circuit is shown in Fig. 5.63b:
(Fig. 5.63b)
Weve included ro in this model since it can have an appreciable
effect on the operation of this amplifier.
Notice that ro is connected from the emitter to an AC ground.
We can simplify the AC small-signal analysis of this circuit by
Whites, EE 320
Lecture 21
Page 2 of 9
moving the collector-side lead of ro to the DC ground, as shown

in Fig. 5.63c:
ii
io
Rib
(Fig. 5.63c)
Similar to the previous BJT amplifiers, well determine the

characteristics of this one by solving for Rin, Gv, Gi, Ais, and Rout.
Input resistance, Rin. Looking into the base of the BJT,
v
Rib = b
ib
From the circuit above, we see that
vb = ie ( re + ro || RL )
Substituting this and ib = ie ( + 1) into (1) yields
Rib = ( + 1) ( re + ro || RL )
(1)
(2)
(3)
This expression for Rib follows the so-called resistance

reflection rule: the input resistance is (+1) times the total
resistance in the emitter lead of the amplifier. (We saw a
Whites, EE 320
Lecture 21
Page 3 of 9
similar result in Lecture 19 for the CE amplifier with emitter

degeneration.)
In the special case when re RL ro then
Rib ( + 1) RL
(4)
which can potentially be a large value.

Referring to circuit above, the input resistance to the amplifier
is
Rin = RB || Rib = RB || ( + 1) ( re + ro || RL )
(5)

voltage gain
v
(6)
Av o
vb
Beginning at the output,
r || R
vo = o L vb
(7)
ro || RL + re
from which we can directly determine that
r || R
(8)
Av = o L
ro || RL + re

v
Gv o
(9)
vsig
Whites, EE 320
Lecture 21

v v
vb
Gv = b o =
Av
N
vsig vb ( 6) vsig
Page 4 of 9
(10)

equivalent circuit
Rin
(11)
vb =
vsig
Rin + Rsig
Substituting this result into (10) yields an expression for the
overall small-signal voltage gain
v
r || R
Rin
Gv o = o L
vsig ro || RL + re Rin + Rsig
or
RB || ( + 1) ( re + ro || RL )
ro || RL
Gv =
ro || RL + re RB || ( + 1) ( re + ro || RL ) + Rsig
(12)
We can observe directly that each of the two factors in this

expression are less than one, so this overall small-signal
voltage gain is less than unity.
In the special instance that ro RL then (12) simplifies to
RB || ( + 1) ( re + RL )
RL
(13)
Gv
RL + re RB || ( + 1) ( re + RL ) + Rsig
and if RB ( + 1) ( re + RL ) then this further simplifies to
Whites, EE 320
Lecture 21
Gv
Page 5 of 9
RL
re + RL +
Rsig
(5.146),(14)
+1
We see from this expression that under the above two

assumptions and a third RL re + Rsig ( + 1) , the smallsignal voltage gain is less than but approximately equal to
one. This means that
v
(15)
Gv o 3 1 or vo 3 vsig
vsig
Because of this result, the common collector amplifier is also
called an emitter follower amplifier.
i
Gi o
(16)
ii
ro
ro
(17)
io =
ie =
( + 1) ib
ro + RL
ro + RL
while using current division at the input
RB
ib =
ii
(18)
RB + Rib
Substituting this into (17) gives
ro
RB
io =
ii
+
1
(19)
(
)
ro + RL
RB + Rib
from which we find that
Whites, EE 320
Lecture 21
Gi =
or
Gi =
( + 1) ro RB
io
=
ii ( ro + RL )( RB + Rib )
( + 1) ro RB
( ro + RL ) RB + ( + 1) ( re + ro || RL )
Page 6 of 9
(20)
(21)

load (RL = 0), Gi in (21) reduces to the short circuit current
gain:
( + 1) RB
i
Ais = os =
(22)
ii RB + ( + 1) re
In the case that RB ( + 1) ( re + RL ) = ( + 1) re , as was used
earlier, then
Ais + 1
(23)
which can be very large.
So even though the amplifier has a voltage gain less than one
(and approaching one in certain circumstances), it has a very
large small-signal current gain. Overall, the amplifier does
provide power gain to the AC signal.
Output resistance, Rout. With vsig = 0 in the small-signal
equivalent circuit, were left with
Whites, EE 320
Lecture 21
Page 7 of 9
(1 ) ie
ie
B
RB||Rsig
ie
re
E
ix
+
ro
vx
Rout
It is a bit difficult to determine Rout directly from this circuit

because of the dependent current source. The trick here is to
apply a signal source vx and then determine ix. The output
resistance is computed from the ratio of these quantities as
v
Rout x
(24)
ix
Applying KVL from the output through the input of this
circuit gives
vx = ie re (1 ) ie ( Rsig || RB )
(25)
= ie (1 ) ( Rsig || RB ) + re
Using KCL at the output
v
(26)
ix = x ie
ro
Substituting (26) into (25)
Whites, EE 320
Lecture 21
Page 8 of 9
vx
vx = ix (1 ) ( Rsig || RB ) + re
ro
(1 ) ( Rsig || RB ) + re
vx 1 +
= ix (1 ) ( Rsig || RB ) + re (27)
ro
Forming the ratio of vx and ix in (27) gives

(1 ) ( Rsig || RB ) + re
vx
Rout = =
ix
(1 ) ( Rsig || RB ) + re
1+
ro
ro (1 ) ( Rsig || RB ) + re
Rout =
or
ro + (1 ) ( Rsig || RB ) + re
such that
Rout = ro || (1 ) ( Rsig || RB ) + re
This is equivalent to
Rout
Rsig || RB
= ro ||
+ re
+1
(5.148),(28)
In the case ro is large, then

Rout
Rsig || RB
+1
+ re
(5.149),(29)
which is generally relatively small.
Summary
Summary of the CC (emitter follower) small-signal amplifier:
Whites, EE 320
Lecture 21
Page 9 of 9
1. High input resistance.

2. Gv less than one, and can be close to one.
3. Ais can be large.
4. Low output resistance.
These characteristics mean that the emitter follower amplifier is
highly suited as a voltage buffer amplifier.
Whites, EE 320
Lecture 22
Page 1 of 12
Lecture 22: BJT Internal Capacitances.

High Frequency Circuit Model.
The BJT amplifiers we have examined so far are all low
frequency amplifiers. For large valued DC blocking capacitors
and for frequencies of tens to hundreds of kHz, the simple smallsignal models we used will work well.
As the frequency increases, though, there are multiple sources of
effects that will limit the performance of these amplifiers
including:
1. Internal capacitances of the BJT. These are due to charge
storage effects at and near the two pn junctions.
2. Parasitic effects. These are due to packaging and transistor
construction that create additional capacitances, lead
inductances, and resistances.
Additionally, the performance of many BJT amplifiers weve
already examined will be sharply curtailed by DC blocking
capacitors that have finite value (i.e., less than infinity).
For these reasons, all real transistor amplifiers operate
effectively only over a limited (but hopefully large) range of
signal frequencies.
Whites, EE 320
Lecture 22
Page 2 of 12
Referring to Fig. 5.71(b), our analysis of small-signal BJT

amplifiers up to this point has focused on the Midband
frequency region. This frequency band is bounded by the
frequencies fL and fH, which are the -3-dB gain frequencies, or
half-power frequencies.
(Fig. 5.71)
The roll off in gain near fL and lower is due to effects of the DC
blocking capacitors CC1 and CC2, and the bypass capacitor CE.
Its not possible to eliminate this effect, though fL can be moved
about by choosing different values for these capacitors. But
large capacitors take up lots of space and can be expensive.
Whites, EE 320
Lecture 22
Page 3 of 12
The primary focus of this lecture, however, is the origin of the

roll off in gain experienced at higher frequencies near fH and
higher.
Capacitance of pn Junctions
There are basically two types of capacitances associated with pn
junctions:
1. Junction capacitance. This is related to the space charge
that exists in the depletion region of the pn junction.
2. Diffusion capacitance, or charge storage capacitance. This
is a new phenomenon we havent yet considered in this
course.
The junction capacitance effect was briefly mentioned earlier in
this course in Lecture 4. The width of the depletion region will
change depending on the applied voltage and whether the
junction is reversed or forward biased:
Whites, EE 320
Lecture 22
Page 4 of 12
The time-varying E due to the space charge in the depletion

region is a so-called displacement current that can be modeled
by a junction capacitance.
The second basic type of capacitance, diffusion capacitance, is
associated with pn junctions that are forward biased.
(Fig. 3.49)
In this state, current will flow across the junction, of course.
Because of the current source in Fig. 3.49 and the voltage drop
V, holes are injected across the junction into the n region while
electrons are injected across the junction into the p region.
Whites, EE 320
Lecture 22
Page 5 of 12
(Fig. 3.50)
The concentrations of these electrons and holes decrease in
value away from the junction, as shown in Fig. 3.50, due to
recombination effects.
The important point here is that these concentrations of charges
create an electric field across the pn junction that will vary with
time when a signal source is connected to this device. This
electric field is directed from the n to p region, and the overall
effect can be modeled by what is called the charge storage
capacitance, or diffusion capacitance.
To summarize, the capacitive effects of a reversed biased pn
junction are described by the junction capacitance while those of
a forward biased pn junction are described by both a junction
Whites, EE 320
Lecture 22
Page 6 of 12
and a diffusion capacitance. In the latter case, though, the

diffusion capacitance usually dominates.
BJT High Frequency Small-Signal Model

The active mode BJT has one forward biased pn junction (the
EBJ) and one reversed biased pn junction (the CBJ). In the case
of an npn BJT the capacitances associated with the pn junctions
in the device are labeled as:
As we just discussed, there is a junction capacitance associated

with the reversed biased CBJ, which is labeled C as shown
above. There will be a junction capacitance, Cje, associated with
the forward biased EBJ as well as a diffusion capacitance
labeled Cde. These latter two capacitances appear in parallel and
so can be combined as
C C je + Cde
(1)
Typically C ranges from a fraction of pF to a few pF while C
ranges from a few pF to tens of pF, which is dominated by Cde.
Whites, EE 320
Lecture 22
Page 7 of 12
With these capacitances, the high frequency small-signal model

of the BJT becomes
(Fig. 5.67)
Note the use of the V notation in this small-signal model. Your
textbook has switched to sinusoidal steady state notation for this
high frequency discussion.
The high frequency small-signal model in Fig. 5.67 also
includes the resistance rx, which is mostly important at high
frequencies. Its there to approximately model the resistance of
the base region from the terminal to a point somewhere directly
below the emitter:
rx
(Fig. 5.6)
C is sometimes referred to as Cob (or Cobo) in datasheets. This
designation reflects the fact that C can be the output resistance
when the BJT is used as a common base amplifier.
Whites, EE 320
Lecture 22
Page 8 of 12
The values of these small-signal circuit model elements may or

may not be available in a datasheet for your transistor. For
example, from the Motorola P2N2222A datasheet:
Actually, we would expect these capacitances to vary with the

voltage across the respective pn junction. In the following figure
from the Motorola P2N2222A datasheet, we see the dependence
of Ceb (= C ?) and Ccb (= C) for a range of junction
voltages. (Perhaps the labeled voltage for Ceb should be
forward voltage?)
Whites, EE 320
Lecture 22
Page 9 of 12
Unity-Gain Bandwidth
An important high frequency characteristic of transistors that is
usually specified is the unity-gain bandwidth, fT. This is defined
as the frequency at which the short-circuit current gain
I
h fe c
(2)
I b s.c. load
has decreased to a value of one.
A test circuit for this measurement would look something like:
The small-signal high frequency model of this test circuit is:
Applying KCL at the collector terminal provides an equation for

the short-circuit collector current
Whites, EE 320
Lecture 22
Page 10 of 12
I c = g mV jCV = ( g m jC )V
At the input terminal B
V = I b Z in = I b r || Z C + Z C
or
V = I b + j ( C + C )
r
(5.157),(3)
(5.158),(4)

1
I c = ( g m jC ) I b + j ( C + C )
r
Using the definition of hfe from (2) we find from this last
equation that
g m jC
I
h fe = c
=
(5)
1
I b s.c. load
+ j ( C + C )
r
It turns out that C is typically quite small and for the purposes
of determining the unity-gain bandwidth, gm is | jC | for the
frequencies of interest here. In other words, the frequency at
which C is important relative to gm is much higher than what
is of interest here.
Consequently, from (5)
Whites, EE 320
Lecture 22
h fe
gm
1
+ j ( C + C )
r
Page 11 of 12
g m r
1 + j r ( C + C )
(6)
We can recognize this frequency response of hfe in (6) as that for

a single pole low pass circuit:
(Fig. 5.69)
0 = g m r in this plot is the low frequency value of hfe, as weve

used in the past [see eqn. (5.93)], while the 3-dB frequency of
h fe is given by
1
(5.160),(7)
=
r ( C + C )
The frequency at which h fe in (6) declines to a value of 1 is
denoted by T, which we can determine from (6) to be
h fe = 1 =
or
such that
1 + jT r ( C + C )
0 = 1 + jT r ( C + C ) = 1 + j
Whites, EE 320
Lecture 22
T
2
0 = 1 +
Page 12 of 12
T

for T .
Therefore
T 0 =
g m r
gm
=
( C + C ) r C + C
(5.162),(8)
so that
fT
gm
2 ( C + C )
(5.163),(9)
This unity-gain frequency fT (or bandwidth) is often specified

on transistor datasheets. On page 8, for example, fT = 300 MHz
for the Motorola P2N2222A. Using (9), this fT can be used to
determine C + C for a particular DC bias current.
Lastly, the high frequency, hybrid-, small-signal model of Fig.
5.67 is fairly accurate up to frequencies of about 0.2 fT.
Furthermore, at frequencies above 5f to 10 f, the effects of r
are small compared to the impedance effects of C. Above that,
rx becomes the only resistive part of the input impedance at high
frequencies. Consequently, rx is a very important element of the
small-signal model at these high frequencies, but much less so at
low frequencies.
Whites, EE 320
Lecture 23
Page 1 of 17
Lecture 23: Common Emitter Amplifier

Frequency Response. Millers Theorem.
Well use the high frequency model for the BJT we developed in
the previous lecture and compute the frequency response of a
common emitter amplifier, as shown below in Fig. 5.71a.
(Fig. 5.71)
As we discussed in the previous lecture, there are three distinct
region of frequency operation for this and most transistor
amplifier circuits. Well examine the operation of this CE
Whites, EE 320
Lecture 23
Page 2 of 17
amplifier more closely when operated in three frequency

regimes.
Mid-band Frequency Response of the CE Amplifier

At the mid-band frequencies, the DC blocking capacitors are
assumed to have very small impedances so they can be replaced
by short circuits, while the impedances of C and C are very
large so they can be replaced by open circuits. The equivalent
small-signal model for the mid-band frequency response is then
Well define
RL = ro || RC || RL
(1)
Vo = g m RLV
(2)
so that at the output
Using Thvenins theorem followed by voltage division at the

input we find
Whites, EE 320
V =
Lecture 23
Page 3 of 17
r
r
RB
VTH =
Vsig
r + rx + RTH
r + rx + RB || Rsig RB + Rsig
(3)
Substituting (3) into (2) we find the mid-band voltage gain Am to

be
V
g m r
RB
( ro || RC || RL ) (4)
Am o =
Vsig r + rx + RB || Rsig RB + Rsig
High Frequency Response of the CE Amplifier

For the high frequency response of the CE amplifier of Fig.
5.71a, the impedance of the blocking capacitors is still
negligibly small, but now the internal capacitances of the BJT
are no longer effectively open circuits.
Using the high frequency small-signal model of the BJT
discussed in the previous lecture, the equivalent small-signal
circuit of the CE amplifier now becomes:
(Fig. 5.72a)
Whites, EE 320
Lecture 23
Page 4 of 17
Well simplify this circuit a little by calculating a Thvenin

equivalent circuit at the input and using the definition for RL in
(1):
(Fig. 5.72b)
where it can be easily shown that Vsig is V given in (3)
r
RB
Vsig =
Vsig (5.167),(5)
while
Rsig = r || rx + ( RB || Rsig )
(5.168),(6)
Millers Theorem
We can analyze the circuit in Fig. 5.72b through traditional
methods, but if we apply Millers theorem we can greatly
simplify the effort. Plus, it will be easier to apply an
approximation that will arise if we use Millers theorem.
You may have seen Millers theorem previously in circuit
analysis. It is another equivalent circuit theorem for linear
Whites, EE 320
Lecture 23
Page 5 of 17
circuits akin to Thvenins and Nortons theorems. Millers

theorem applies to this circuit topology:
(Fig. 1)
The equivalent Millers theorem circuit is
(Fig. 2)
where
ZA =
Zx
v
1 B
vA
and Z B =
Zx
v
1 A
vB
(7),(8)
The equivalence of these two circuits can be easily verified. For

example, using KVL in Fig. 1
v A = i A Z x + vB
v v
(9)
iA = A B
or
Zx
while using KVL in the left-hand figure of Fig. 2 gives
Whites, EE 320
Lecture 23
Page 6 of 17
vA
ZA
(10)
iA =
Now, for the left-hand figure to be equivalent to the circuit in

Fig. 1, then iA in (9) and iA in (10) must be equal. Therefore,
v A vB v A
=
Zx
ZA
The equivalent impedance ZA can be obtained from this equation
as
Zv
Zx
ZA = x A =
v A vB 1 vB
vA
which is the same as (7). A similar result verifies (8).
So, for a resistive element Rx, Millers theorem states that
Rx
Rx
and RB =
(12),(13)
RA =
vB
vA
1
1
vA
vB
while for a capacitive element Cx, Millers theorem states that
v
v
C A = C x 1 B and CB = Cx 1 A (14),(15)
vA
vB
Whites, EE 320
Lecture 23
Page 7 of 17
High Frequency Response of the CE Amplifier (cont.)

Returning now to the CE amplifier equivalent small-signal
circuit of Fig. 5.72b, well apply Millers theorem of Figs. 1 and
2 to this circuit and the capacitor C to give
(Fig. 3)
where, using (14) and (15),
V
V
C A = C 1 o and CB = C 1
V
Vo
(16),(17)
Actually, this equivalent circuit of Fig. 3 is no simpler to

analyze than the one in Fig. 5.72b because of the dependence of
CA and CB on the voltages Vo and V.
However, this equivalent circuit of Fig. 3 will prove valuable for
the following approximation. Note from Fig. 5.72b that
I L + I = g mV I L = g mV I
(18)
Up to frequencies near fH and better, the current I in the small
capacitor C will be much smaller than g mV . Consequently,
from (18)
Whites, EE 320
and
Lecture 23
Page 8 of 17
I L g mV
Vo I L RL = g m RLV
(19)
(5.169),(20)
Using this last result in (16) and (17) we find that

g R V
C A C 1 + m L = C 1 + g m RL
V
1
C B C 1 +
and
= C 1 +
g R V
g R
m L
m L
(21)
(22)
Most often for this type of amplifier, g m RL 1 so that in (22)

CB C . But as we initially assumed, the current through C is
much smaller than that through the dependent current source
g mV , which ultimately led to equation (19).
Consequently, we can ignore CB in parallel with g mV and the
final high frequency small-signal equivalent circuit for the CE
amplifier in Fig. 5.71a is
(Fig. 5.72c)
Whites, EE 320
where
Lecture 23
Page 9 of 17
Cin C + C A = C + C 1 + g m RL
(5.173),(22)
Based on this small-signal equivalent circuit, well derive the

high-frequency response of this CE amplifier. At the input
Z Cin
(23)
V =
Vsig
Z Cin + Rsig
while at the output
Vo = g m RLV
(24)
Vo = g m RL
Z Cin
Z Cin
+ Rsig
Vsig
Since Z Cin = ( jCin ) then (25) becomes

1
g m RL
jCin
Vo = g m RL
Vsig =
Vsig
1
1 + jCin Rsig
+ Rsig
jCin
If we define
1
H =
Cin Rsig
1
then substitute this into (26) gives

Vo
g m RL g m RL
=
=
f
Vsig 1 + j
1+ j
H
fH
(25)
(26)
(27)
(28)
Whites, EE 320
where
Lecture 23
fH =
H
1
=
2 2 Cin Rsig
Page 10 of 17
(5.176),(29)
You should recognize this transfer function (28) as that for a low
pass circuit with a cut-off frequency (or 3-dB frequency) of H.
This is the response of a single time constant circuit, which is
what we have in the circuit of Fig. 5.72c.
What were ultimately interested in is the overall transfer
function Vo Vsig from input to output. This can be easily derived
from the work weve already done here. Since
Vo
Vo Vsig
=
(30)
Vsig Vsig Vsig
We can use (28) for the first term in the RHS of (30), and use (5)
for the second giving
Vo
r
g m RL
RB
=
(31)
Vsig 1 + j f r + rx + RB || Rsig RB + Rsig
fH
We can recognize Am from (4) in this expression giving
Vo
Am
=
(5.175),(32)
Vsig 1 + j f
fH
Once again, this is the frequency response of a low pass circuit,
as shown below:
Whites, EE 320
Lecture 23
Page 11 of 17
(Fig. 5.72d)
Comments and the Miller Effect

Equation (32) gives the mid-band and high frequency
response of the CE amplifier circuit. It is not valid for the low
frequency response near fL and lower frequencies, as shown in
Fig. 5.71b.
It turns out that Cin in (22) is usually dominated by
C A = C 1 + g m RL . Even though C is usually much smaller
than C its effects at the input are accentuated by the factor
1 + g m RL .
The reason that CA undergoes this multiplication is because it

is connected between two nodes (B and C in Fig. 5.72a) that
experience a large voltage gain. This effect is called the
Whites, EE 320
Lecture 23
Page 12 of 17
Miller effect and the multiplying factor 1 + g m RL in (22) is

called the Miller multiplier.
Because of this Miller effect and the Miller multiplier, the

input capacitance Cin of the CE amplifier is usually quite
large. Consequently, from (20) the fH of this amplifier is
reduced. In other words, this Miller effect limits the high
frequency applications of the CE amplifier because the
bandwidth and gain will be limited.
Low Frequency Response of the CE Amplifier

On the other end of the spectrum, the low frequency response of
the CE amplifier and all other capacitively coupled amplifiers
is limited by the DC blocking and bypass capacitors.
This type of low frequency response analysis is rather
complicated because there is more than a single time constant
response involved. In the circuit of Fig. 5.71a there are three
capacitors involved, CC1, CC2, and CE. All three of these greatly
affect the low frequency response of the amplifier and cant be
ignored.
Whites, EE 320
Lecture 23
Page 13 of 17
The text presents an approximate solution in which the low

frequency response is modeled as the product of three high pass
single time constant circuits cascaded together so that
Vo
j
j
j
Am
(5.183),(33)
Vsig
j + p1 j + p 2 j + p 3
(Fig. 5.73e)
So there isnt a single fL as suggested by Fig. 5.71b but rather a
more complicated response at low frequencies as we see in Fig.
5.73e above. Computer simulation is perhaps the best predictor
for this complicated frequency response, but an approximate
formula for fL is given in the text as
1 1
1
1
+
+
f L f p1 + f p 2 + f p 3 =
2 CC1RC1 CE RE CC 2 RC 2
(5.184),(5.185),(34)
where RC1 , RE , and RC 2 are the resistances seen by CC1 , CE , and
CC 2 , respectively, with the signal source Vsig = 0 and the other
two capacitors replaced by short circuits.
Whites, EE 320
Lecture 23
Page 14 of 17
Example N23.1. Compute the mid-band small-signal voltage

gain and the upper 3-dB cutoff frequency of the small-signal
voltage gain for the CE amplifier shown in Fig. 5.71a. Use a
2N2222A transistor and the circuit element and DC source
values listed in Example 5.18 in the text. Use 10 F blocking
and bypass capacitors.
The circuit in Agilent Advanced Design System appears as:
V_DC
SRC2
Vdc=10.0 V
AC
AC
AC1
Start=100 Hz
Stop=1.0 MHz
Step=100 Hz
R
R2
R=8 kOhm
vo
C
C2
C=10 uF
vi
V_AC
R
SRC1
R3
Vac=polar(1,0) V R=5 kOhm
Freq=freq
C
C1
C=10 uF
R
R1
R=100 kOhm ap_npn_2N2222A_19930601
Q1
C
I_DC
C3
SRC4
Idc=1 mA C=10 uF
V_DC
SRC3
Vdc=-10.0 V
From the results of the ADS circuit simulation
R
R4
R=5 kOhm
Whites, EE 320
Lecture 23
Page 15 of 17
VCB = 2.03 V ( 400 mV ) = 2.43 V

VBE = 0.4 V ( 1.02 V ) = 0.62 V
From Fig. 9 in the Motorola 2N2222A datasheet (see the
previous set of lecture notes)
For VCB = 2.43 V Ccb = C 5.8 pF.
For VBE = 0.62 V Ceb = C 20 pF.
gm =
IC
1 mA
=
= 0.04 S
VT 25 mV
From (5.163),
fT
gm
0.04
=
= 246.8 MHz
2 ( C + C ) 2 ( 20 pF + 5.8 pF )
This value agrees fairly with the datasheet value of 300 MHz.
0 265 from the ADS parts list for this 2N2222A transistor.
Therefore,
r =
0
gm
265
= 6,625
0.04
From the 2N2222A datasheet, the nominal output resistance at

IC = 1 mA is ro 50 k.
What about rx? Its so small in value (~ 50 ) that well easily
be able to ignore it for the Am calculations compared to r (which
is 6,625 as we just calculated). From (4),
Whites, EE 320
Lecture 23
Am =
Page 16 of 17
g m r
RB
( ro || RC || RL )


2,898.6 = RL
0.02327
0.9524
V
V
Am ) = 36.2 dB
Am = 64.24
Therefore,
or in decibels
Am = 20 log10 (
From ADS:
m3
freq= 400.0 Hz
dB(vo)=33.632
40
dB(vo)
35
m3
m1
m2
freq= 6.300kHz freq= 84.40kHz
dB(vo)=36.053 dB(vo)=33.046
m1
m2
30
25
20
15
10
1E2
1E3
1E4
1E5
1E6
freq, Hz
From this plot, ADS computes a mid-band gain of Am = 36.05

dB, which agrees closely with the predicted value above.
From (29),
fH
1
2 Cin Rsig
Whites, EE 320
where from (22)
Lecture 23
Page 17 of 17
Cin = C + C 1 + g m RL = 20 + 5.8 (1 + 0.04 2,898.6 ) pF

= 20 + 678.3 = 698.3 pF
while from (6)
Rsig = r || rx + ( RB || Rsig )
Because RB || Rsig = 100 k || 5 k = 4,761.9 is so much larger
than rx (on the order of 50 ), we can safely ignore rx. Then,
Rsig 6,625 || 4,762 = 2,771 .
Therefore,
f H 2 698.3 1012 2,771 = 82.25 kHz
This agrees very closely with the value of 84.40 kHz predicted
by the ADS simulation shown above.
Add a short discussion on the gain-bandwidth product Am f H .
Whites, EE 320
Lecture 24
Page 1 of 5
Lecture 24: BJT as an Electronic Switch.

The transistor can be used as an electronic switch, in addition to
an amplifier. As a switch, we use the cutoff and saturation
regions of BJT operation.
(Fig. 5.74)
Cutoff Region. If vI 3 0.5 or so, the EBJ will conduct
negligible current. Also, the CBJ will be reversed biased with
a large VCC.
Consequently,
iB 0 , iC 0 , and iE 0
(1)
which means
vO = VCC
(2)
These are the cutoff conditions and the BJT is in the off
state.
Saturation Region. For the on state of the switch, we

increase vI until the BJT saturates. This occurs when the EBJ
and the CBJ are both forward biased.
Whites, EE 320
Lecture 24
Page 2 of 5
Due to asymmetries in the device fabrication, the voltage

drops are different for these two forward-biased junctions.
VCE
sat
0.2 V
VEC
sat
0.2 V
These are only approximate values for saturated BJTs. The

actual values of VCE sat and VEC sat depend heavily on iC.
Equivalent circuit models for these saturated BJTs are:
VBE 0.7 V
VCE
sat
0.2 V
VEB 0.7 V
VEC
So, with vI large, then

VCC
iC
RC
vO VCE
RB
+
vI
iB
iE
sat
sat
0.2 V
Whites, EE 320
Lecture 24
vO = VCE
With
Page 3 of 5
sat
(3)
then
VCC VCE sat
vI 0.7
, iC sat =
, iE = iB + iC sat
(4)
RB
RC
Remember that because the BJT is no longer operating in the
active region, iC iB .
iB =
Instead, if the BJT is operating in the saturation mode

iC sat
forced
<
iB
(5)
Example N24.1. The BJT in the circuit below has 50 150 .

Find the RB that saturates the BJT with a so-called overdrive
factor of at least 10.
VO 0.2 V
Designing at electronic switch has essentially two parts: cutoff

and saturation. Cutoff is easy to design. Just make vI 3 0.5 V or
so.
Whites, EE 320
Lecture 24
Page 4 of 5
Saturation is a bit more difficult to design. We need vI

sufficiently large so that the collector current becomes large
enough for the CBJ to become forward biased.
For this problem, assume the BJT is saturated so that
VCE sat = 0.2 V. Therefore,
10 0.2
I C = I C sat =
= 9.8 mA.
1,000
To saturate the BJT with the smallest we need to provide

IC
9.8 mA
= 0.196 mA
I B = sat =
50
min
This is IB just on the edge of saturation (EOS). For an overdrive
factor (ODF) of 10 means we want to force 10 times this
current into the base of the BJT:
I B = ODF I B EOS
(6)
I B = 10 0.196 mA = 1.96 mA.
or
Therefore, since
IB =
5 0.7
4.3
RB =
= 2.2 k
RB
IB
Now, with this design and the transistor saturated, what is the
forced ?
I
9.8 mA
forced = C sat =
=5
IB
1.96 mA
Whites, EE 320
Lecture 24
Page 5 of 5
This value is much smaller that min=50, as expected. Another

way to compute forced is to notice:
I
I C sat
forced = C sat =
IB
ODF I B sat
such that
forced =
ODF
(7)
Using (7) for this example,
forced =
50
=5
10
Lastly, what happens if is increased from 50 to 150 as stated in

the problem? Will the transistor stay saturated? Yes, it will.
Actually, nothing changes in our saturated circuit as varies.
However, forced becomes smaller indicating that the transistor is
becoming more saturated.
Whites, EE 320
Lecture 25
Page 1 of 10
Lecture 25: Enhancement Type MOSFET

Operation, P-channel, and CMOS.
We will now move on to the second major type of transistor
called the field effect transistor (FET). In particular, we will
examine in detail the metal oxide semiconductor FET
(MOSFET). This is an extremely popular type of transistor.
MOSFETs have similar uses as BJTs. They can be used as
signal amplifiers and electronic switches, for example.
MOSFETS can be manufactured using a relatively simple
process and made very small with respect to BJTs.
There are two major types of MOSFETS, called enhancement
type and depletion type. Each of these types can be
manufactured with a so-called n channel or p channel:
Whites, EE 320
Lecture 25
Page 2 of 10
Enhancement Type, N Channel MOSFET

The enhancement type MOSFET is the most widely used FET.
It finds extensive use in VLSI circuits, for example. (In general,
MOSFETs are not used too often in discrete component design.)
The physical structure of this type of MOSFET (enhancement
type NMOS) is shown in Fig. 4.1:
(Fig. 4.1a)
Four Terminals:
n+ means
heavily doped
Often the body and

source are connected.
(Fig. 4.1b)
Whites, EE 320
Lecture 25
Page 3 of 10
Typical dimensional values are L = 0.1 to 3 m, W = 0.2 to 100

m, and tox = 2 to 50 nm.
The minimum L and W dimensions are dictated by the resolution
of the lithography process used to create the device. Intel
recently developed a 45-nm process, as described in the attached
article from IEEE Spectrum. To avoid the so-called short
channel effects, the channel length is made generally two to
five times larger than the smallest possible feature sizes.
Consequently, one could expect the channel length to be ~90 nm
to 225 nm for the MOSFETs fabricated by this process.
Notice in the figures on the previous page that the MOSFET
device has four terminals, though often the body and source
terminals are connected together forming a three terminal
device.
With no bias voltage applied to the gate terminal, there exists
two back-to-back pn junctions between the drain and the source.
No current flows from drain to source (the resistance will be on
the order of 1012 ).
In order to obtain current flow the MOSFET needs to be biased,
similar to what is required for BJTs. For the MOSFET, however,
we apply a voltage to the gate with respect to the source: vGS.
Because of the oxide layer under the gate electrode, the gate
current will be essentially zero.
Whites, EE 320
Lecture 25
Page 4 of 10
(Fig. 4.2)
In effect, the gate and the channel region form a parallel plate
capacitor of sorts. Two things happen when vGS is applied:
1. Free holes in the p-type substrate are repelled from the
region under the gate. This process uncovers bound
negative charge.
2. Electrons from the heavily doped n+ regions (the drain and
source) are attracted under the gate.
These effects create an n-type channel. Notice that this bias
voltage vGS is required in order to create the channel: no vGS,
no channel.
Now, if a voltage is applied between the drain and source we
will have a flow of electrons from source to drain (i.e., a
current). This is the origin of the names source and drain.
Whites, EE 320
Lecture 25
Page 5 of 10
(Fig. 4.3)
The vGS required to accumulate sufficient numbers of mobile
electrons in the channel is called the threshold voltage Vt. For an
n-channel MOSFET, Vt 1 3 V (note that this is a positive
voltage).
A family of iD-vDS characteristic curves for the MOSFET with a
small vDS is shown in Fig. 4.4 with vGS as the parameter:
(Fig. 4.4)
Whites, EE 320
Lecture 25
Page 6 of 10
In this mode, the transistor is behaving like a resistor between

the drain and source terminals whose resistance is controlled by
vGS.
Actually, the conductance of this channel is proportional to the
so-called excess gate voltage vGS Vt , which must be greater
than zero for current to exist from drain to source.
iD-vDS for Larger vDS

The behavior of the MOSFET changes considerably when vDS
increases beyond small values:
(Fig. 4.5)
In these circumstances, an additional electric field is created
from drain to source that is large enough to alter the shape of the
channel. With the electric field from vDS directed as shown
above, there exists more negative charges near the source end of
Whites, EE 320
Lecture 25
Page 7 of 10
the channel than at the drain end. This produces a thicker

channel near the source than the drain.
Because of this tapered shape of the channel, the resistance of
the channel increases. Hence, the iD-vDS characteristic curve is
no longer a straight line:
(Fig. 4.6)
Note that it is possible to increase vDS large enough to reduce the
channel thickness to zero at the drain end.
(Fig. 4.7)
This is called pinch off ( vDS vGS Vt ).
Whites, EE 320
Lecture 25
Page 8 of 10
Does this mean that the current iD = 0 ? Actually, it does not. A

MOSFET that is pinched off at the drain end of the channel
still conducts current:
D
- - - - -
n+
E ++
+
+
Depletion region
p type
The large E in the depletion region surrounding the drain will

sweep electrons across the end of the pinched off channel to the
drain.
This is very similar to the operation of the BJT. For an npn BJT,
the electric field of the reversed biased CBJ swept electrons
from the base to the collector regions.
Regions of MOSFET Operation

There are three regions of operation for a MOSFET:
1. Off or cutoff region, where iD = 0 .
2. Triode region, where
vDS < vDS sat = vGS Vt
3. Saturation region, where
(4.1),(1)
Whites, EE 320
Lecture 25
vDS > vDS
Page 9 of 10
sat
(2)
The term saturation has a very different meaning for MOSFETs

than for BJTs.
As derived in the text on pp. 243-245, the iD-vGS relationships for
MOSFETs are given mathematically as
2
vDS
W
i
k
v
V
v
=
Triode region: D
(4.5a),(3)
( GS t ) DS
n
L
2
1 W
2
iD = kn ( vGS Vt )
(4.6a),(4)
2
L
where kn is the process transconductance parameter [A/V2] and
is equal to
Saturation region:
kn = nCox = n ox
(4.7),(5)
tox
Here, n is the mobility of electrons in the channel [cm2/(V-s)],
Cox is the capacitance per unit gate area [F/m2], and ox and tox
are the permittivity and thickness of the gate oxide layer,
respectively.
Enhancement-Type P-Channel MOSFET

The p-channel MOSFET (PMOS) is manufactured similarly to
the NMOS:
Whites, EE 320
Lecture 25
Page 10 of 10
IS
p+
p channel
ID
ISD
p+
n type
Holes are the charge carriers in the p-type channel. When

operating this device: vGS < 0 , vDS < 0 , and Vt < 0 .
PMOS was originally the dominant MOSFET, but was replaced
by NMOS. NMOS can be manufactured smaller than PMOS and
operate faster.
Complementary MOS (CMOS)

CMOS are transistor circuits formed from a combination of
NMOS and PMOS devices in the same circuit. Very popular.
(Fig. 4.9)
Whites, EE 320
Lecture 26
Page 1 of 8
Lecture 26: MOSFET Circuit Symbols,

iD-vDS Characteristics.
There are two circuit symbols you may encounter for the
enhancement type MOSFET. For the n-channel, one symbol is
(Fig. 4.10b)
Referring to this circuit symbol:
9 The arrowed terminal indicates the source,
9 This arrow direction indicates n-type (direction of current)
9 The gap at the gate indicates the oxide layer.
However, the body is often connected to the source. This leads
to a more common circuit symbol:
(Fig. 4.10c)
Similar circuit symbols are used for p-channel enhancement type
MOSFETS:
Whites, EE 320
Lecture 26
Page 2 of 8
(Fig. 4.18b,c)
MOSFET iDvDS Characteristics

Similar to a BJT, we can generate a set of iDvDS characteristic
curves for a MOSFET by setting vGS and varying vDS. This is
shown in Fig. 4.11 for an n-type MOSFET:
(Fig. 4.11)
There are three regions of operation:
(1) Cutoff. To operate an enhancement type MOSFET, we first
must induce the channel. For NMOS, this means that
vGS Vt (induce)
(4.8),(1)
Whites, EE 320
Lecture 26
Page 3 of 8
If vGS < Vt there is no channel and the device is cutoff,

which we see in Fig. 4.11.
When the MOSFET is cutoff, iD = iS = 0.
(2) Triode. To operate in this mode, we first must induce the
channel as in (1) above.
We must also keep vDS small enough so the channel is
continuous (not pinched off):
vGD > Vt (continuous)
(4.9),(2)
[Note how similar this last criterion is to vGS > Vt for the
channel to be induced. Here in (2), we have vGD > Vt for a
continuous channel at the drain end. This observation can
help us to remember these criterion.]
Another way of writing this criterion in (2) is in terms of
vDS. Referring to this circuit element
vGD
vDS
we see that
vDS = vGS + vDG

(3)
For a continuous channel, as required by (2), (3) becomes
Whites, EE 320
Lecture 26
Page 4 of 8
vDS vGS = vDG < Vt
Therefore,
vDS < vGS Vt (continuous)
(4.10),(4)
We can use either (2) or (4) to check for triode operation of
the MOSFET.
As given in the last lecture, in the triode region

W
1 2
iD = kn ( vGS Vt ) vDS vDS
L
2
2
If vDS
2 ( vGS Vt ) vDS then
W
iD kn ( vGS Vt ) vDS rDS1vDS
L

(4.11),(5)
(4.12),(6)
1
rDS
where rDS is defined as the (linear) resistance between the

drain and source terminals. The value of rDS is controlled
by vGS. (See Fig. 4.4).
(3) Saturation. To operate in this mode we need to first induce
the channel
(4.16),(7)
vGS Vt (induce)
then ensure that the channel is pinched off at the drain end
vGD Vt (pinch off)
(4.17),(8)
or equivalently
vDS vGS Vt (pinch off)
(4.18),(9)
As we saw in the previous lecture, the drain current in this
region is
Whites, EE 320
Lecture 26
1 W
2
iD = kn ( vGS Vt )
2
L
and is not dependent on vDS.
Page 5 of 8
(4.20),(10)
A plot of iD versus vGS for an enhancement type NMOS

device in saturation is shown in Fig. 4.12:
(Fig. 4.12)
In the saturation mode, this device behaves as an ideal
current source controlled by vGS:
(Fig. 4.13)
In reality, though, there is a finite output resistance (ro) that
should be added to this model:
Whites, EE 320
Lecture 26
iG = 0
vGS
Page 6 of 8
iD
kn W
2
( vGS Vt )
2 L
vDS
VA
(4.26),(11)
ID
This finite output resistance gives a slope to the iDvDS
characteristic curves:
where
ro =
(Fig. 4.16)
Example N26.1 (similar to text exercise 4.4). Given an

enhancement type NMOS with Vt = 2 V.
Whites, EE 320
Lecture 26
Page 7 of 8
VD
D
G
3V
Determine the region of operation of this device for the

following VD. Use these criteria for the region of operation:
Cutoff: vGS < Vt
Triode: vGS Vt and vDS < vGS Vt
Saturation: vGS Vt and vDS vGS Vt
(a) VD = 0.5 V. VGS = 3 V > Vt = 2 V not cutoff. Then
VDS = 0.5 V < VGS Vt (= 3 2 = 1 V) . triode mode.
(b) VD = 1 V. VGS = 3 V > Vt = 2 V not cutoff. Then
VDS = 1 V = VGS Vt (= 1 V). saturation (or triode) mode.
(c) VD = 5 V. VGS = 3 V > Vt = 2 V not cutoff. Then
VDS = 5 V > VGS Vt (= 1 V). saturation mode.
Example N26.2 (similar to text problem 4.16). An NMOS

enhancement type MOSFET has Vt = 2 V. If VGS ranges from 2.5
to 5 V what is the largest VDS for which the channel remains
continuous?
Whites, EE 320
Lecture 26
vGD
vDS
9 VGS > Vt, VGS so the channel is always present.

9 Then for the channel to remain open at the drain end,
VDS < VGS Vt (triode)
Which VGS to use here? The smallest. Therefore,
VDS max < 2.5 2 = 0.5 V
Page 8 of 8
Whites, EE 320
Lecture 27
Page 1 of 8
Lecture 27: MOSFET Circuits at DC.

We will illustrate the DC analysis of MOSFET circuits through
a number of examples.
Example N27.1 (similar to text example 4.2). Design the circuit

below so that the MOSFET operates with I D = 0.4 mA and
VD = 1 V. The MOSFET has Vt = 2 V, nCox = 20 A/V2, L = 10
m, and W = 400 m. Neglect the channel-length modulation
effect ( = 0 ).
I D = 0.4 mA
VD = 1 V
This last statement (i.e., = 0) means we can neglect the

MOSFET output resistance ( ro ).
RD =
5 1
= 10 k
0.4 mA
Whites, EE 320
Lecture 27
Page 2 of 8
From this circuit we can see that VGD = 1 V, which is less than
Vt. Consequently, the channel is pinched off at the drain end.
Therefore, the MOSFET is operating in the saturation or cutoff
modes (not the triode).
Well assume operation in the saturation mode. In this mode
1 W
1
W
2
2
I D = kn (VGS Vt ) = nCox (VGS Vt )
L
L
2
2
Substituting
1
A 400
2
0.4 mA = 20 106 2
(VGS 2 )
2
V 10
Therefore
2
(VGS 2 ) = 1 VGS 2 = 1
or
VGS = +1 V or +3 V
The first solution is not consistent with our initial assumption of
operation in the saturation mode since it is less than Vt.
Therefore,
VGS = 3 V VS = 3 V
Finally,
RS =
VS ( 5 ) VS + 5 3 + 5
=
=
= 5 k
IS
ID
0.4 mA
Example N27.2 (similar to text example 4.3). Design the circuit

below so ID = 0.4 mA. The MOSFET has Vt = 2 V, nCox = 20
A/V2, L = 10 m, and W = 100 m. Neglect ro.
Whites, EE 320
Lecture 27
Page 3 of 8
VD
With the gate and drain terminals connected together VGD = 0 ,

which is not greater than Vt. This means the channel is not
continuous and the MOSFET is not operating in the triode
mode. Well assume the device is operating in the saturation
mode.
1
W
2
I D = nCox (VGS Vt )
L
2
1
100
2
or 0.4 103 = 20 106
(VGS 2 ) VGS 2 = 2
2
10
Consequently,
VGS = 0 or 4 V
The first solution is not consistent with operation in the
saturation mode since VGS < Vt .
In saturation,
Hence, withVGS = 4 V and VDG = 0 V VD = 4 V.

Finally, since I G = 0 then
10 VD 10 4
R=
=
k = 15 k
0.4 mA
0.4
Whites, EE 320
Lecture 27
Page 4 of 8
Example N27.3 (text example 4.4). Design the circuit below for
a drain voltage of 0.1 V. Determine rDS. The MOSFET has Vt = 1
V and kn W L = 1 mA/V2. Neglect ro.
(Fig. 4.22)
With VGS = 5 V and greater than Vt, the MOSFET has an
induced channel and is not cutoff.
Next, lets check to see if the channel is pinched off at the drain
end. We can do this two (equivalent) ways. First, with VD = 0.1
V then
VGD = 5 0.1 = 4.9 V
which is greater than Vt (= 1 V), so the channel is not pinched
off at the drain. Alternatively, we can compute
VGS Vt = 5 1 = 4 V
which is greater than VDS (= 0.1 V). So again we find that the
channel is not pinched off at the drain.
Either of these two results means the MOSFET is operating in
the triode mode (continuous channel).
Whites, EE 320
Lecture 27
Page 5 of 8
In the triode region,
so that
Then
and
W
1 2
I D = kn (VGS Vt )VDS VDS
L
2
1
= 1 103 (5 1)0.1 (0.1) 2

2
I D = 0.395 mA
5 0.1
k = 12.41 k
0.395
V
0.1
= DS =
k = 253
I D 0.395
RD =
rDS
We could also use (4.13) for this last result, but the work was
already done here. From the text,
1
vDS
W
rDS
= kn
(4.13)
(VGS Vt )
iD vDS small L
vGS =VGS
Using the values above,

1
rDS = 103 ( 5 1) = 250 .

This value is slightly different than what was calculated earlier.
Which one is correct? Why is the other not as accurate?
Example N27.4 (text example 4.6). Design the circuit below so

that the MOSFET is operating in the saturation mode with
I D = 0.5 mA and VD = 3 V. What is the largest RD such that the
Whites, EE 320
Lecture 27
Page 6 of 8
MOSFET remains in the saturation mode? The MOSFET has

Vt = 1 V and k p W L = 1 mA/V2. Neglect ro.
(Fig. 4.24)
For saturation in an enhancement type PMOS device requires
VGS Vt (induced) or VSG Vt (induced)
(4.27)
and
VDS VGS Vt (pinched off)
(4.31)
In words, this last equation states that the drain-to-source
voltage must be less than the gate-to-source voltage plus |Vt|.
In the saturation mode (with = 0 )

1 W
2
(4.32)
I D = k p (VGS Vt )
L
2
1
2
or
0.5 103 = 1 103 (VGS + 1)
2
Therefore,
VGS + 1 = 1 VGS = 0 or -2 V.
The first result is not consistent with operation in the saturation
mode since VGS Vt must be met for saturation. Consequently,
VG = 5 + VGS = 5 2 = 3 V
Whites, EE 320
Lecture 27
Page 7 of 8
RG1 and RG2 must be chosen such that

RG 2
3
RG 2
VG =
VS or
=
RG1 + RG 2
5 RG1 + RG 2
The text chooses RG1 = 2 M and RG 2 = 3 M to satisfy this
requirement. (Why did the book use such large values for RG1
and RG2?)
The drain resistor can be determined from the circuit above
3
RD =
k = 6 k
0.5
For the largest RD, remember that the PMOS device remains in
the saturation mode as long as the drain end of the channel is
pinched off.
VSG Vt
VDG < Vt
Pinch off at the drain end requires

VDG < Vt (pinched off)
which holds up to the point where VD exceeds VG by Vt . That is,
VDmax = VG + Vt = 3 + 1 = 4 V.
From this result,
Whites, EE 320
Lecture 27
RDmax =
VDmax
ID
4V
= 8 k.
0.5 mA
Page 8 of 8
Whites, EE 320
Lecture 28
Page 1 of 7
Lecture 28: MOSFET as an Amplifier.

Small-Signal Equivalent Circuit Models.
As with the BJT, we can use MOSFETs as AC small-signal
amplifiers. An example is the so-called conceptual MOSFET
amplifier shown in Fig. 4.34:
iD
vDS
(Fig. 4.34)
This is only a conceptual amplifier for two primary reasons:
1. The bias with VGS is impractical. (Will consider others
later.)
2. In ICs, resistors take up too much room. (Would use
another triode-region biased MOSFET in lieu of RD.)
To operate as a small-signal amplifier, we bias the MOSFET in
the saturation region. For the analysis of the DC operating point,
we set vgs = 0 so that from (4.22) with = 0
1 W
2
(4.20),(1)
iD = kn ( vGS Vt )
2
L
From the circuit
VDS = VDD I D RD
(4.55),(2)
Whites, EE 320
Lecture 28
Page 2 of 7
For operation in the saturation region

vGD Vt vGS vDS Vt
vDS vGS Vt
or
where the total drain-to-source voltage is
vDS = VDS + vds
N N
bias
(4.18),(3)
AC
Similar to what we saw with BJT amplifiers, we need make sure

that (3) is satisfied for the entire signal swing of vds.
With an AC signal applied at the gate
vGS = VGS + vgs
Substituting (4) into (4.20)
2
2
1 W
1 W
iD = kn (VGS + vgs Vt ) = kn (VGS Vt ) + vgs
2
L
2
L
(4.56),(4)
(5)
1 W
W
1 W
2 2
= kn (VGS Vt ) + kn (VGS Vt ) vgs + kn vgs2 (4.57),(6)
2
L
2
L
2
L
= I D (DC)
(time varying)
The last term in (6) is nonlinear in vgs, which is undesirable for a
linear amplifier. Consequently, for linear operation we will
require that the last term be small:
1 W 2
W
kn
vgs << kn (VGS Vt ) vgs
L
L
2
vgs << 2 (VGS Vt )
(4.58),(7)
or
Whites, EE 320
Lecture 28
Page 3 of 7
If this small-signal condition (7) is satisfied, then from (4.57) the

total drain current is approximately the linear summation
iD I D + id
(4.60),(8)
N N
DC
where
AC
W
id = kn (VGS Vt ) vgs .
L
(9)
From this expression (9) we see that the AC drain current id is

related to vgs by the so-called transistor transconductance, gm:
i
W
g m d = kn (VGS Vt ) [S]
(4.61),(10)
vgs
L
which is sometimes expressed in terms of the overdrive voltage
VOV VGS Vt
W
(4.62),(11)
g m = kn VOV [S]
L
Because of the VGS term in (10) and (11), this gm depends on the
bias, which is just like a BJT.
Physically, this transconductance gm equals the slope of the iDvGS characteristic curve at the Q point:
i
gm D
(4.63),(12)
vGS v =V
GS
GS
Whites, EE 320
Lecture 28
Page 4 of 7
(Fig. 4.35)
Lastly, it can be easily show that for this conceptual amplifier in
Fig. 4.34,
vd
(4.65),(13)
= g m RD
vgs
Consequently, Av g m , which is the same result we found for a
similar BJT conceptual amplifier [see (5.103)].
MOSFET Small-Signal Equivalent Models

For circuit analysis, it is convenient to use equivalent smallsignal models for MOSFETs as it was with BJTs.
Whites, EE 320
Lecture 28
Page 5 of 7
In the saturation mode, the MOSFET acts as a voltage controlled

current source. The control voltage is vgs and the output current
is iD, which gives rise to this small-signal model:
ig = 0
id
VA
1
=
ID ID
is
(Fig. 4.37b)
Things to note from this small-signal model include:
1. ig = 0 and vgs 0 infinite input impedance.
2. ro models the finite output resistance. Practically speaking,
it will range from 10 k 1 M. Note that it depends
on the bias current ID.
3. From (10) we found
W
(14)
g m = kn (VGS Vt )
L
Alternatively, it can be shown that
I
ID
gm = D =
(4.71),(15)
Veff (VGS Vt ) / 2
which is similar to g m = I C VT for BJTs.
One big difference from BJTs is VT 25 mV while Veff = 0.1 V

or greater. Hence, for the same bias current gm is much larger for
BJTs than for MOSFETs.
Whites, EE 320
Lecture 28
Page 6 of 7
A small-signal T model for the MOSFET is shown in Fig. 4.40:

id
ig = 0
is
(Fig. 4.40a)
Notice the direct connection between the gate and both the
dependent current source and 1/gm. While this model is correct,
weve added the explicit boundary condition that ig = 0 to
this small-signal model.
It isnt necessary to do this because the currents in the two
vertical branches are both equal to g m vgs , which means ig = 0 .
But adding this condition ig = 0 to the small-signal model in Fig.
4.40a makes this explicit in the circuit calculations. (The T
model usually shows this direct connection while the model
usually doesnt.)
MOSFETs have many advantages over BJTs including:
1. High input resistance
2. Small physical size
3. Low power dissipation
Whites, EE 320
Lecture 28
Page 7 of 7
4. Relative ease of fabrication.

One can combine advantages of both technologies (BJT and
MOSFET) into what are called BiCMOS amplifiers:
(Fig. 6.46a)
Such a combination provides a very large input resistance from
the MOSFET and a large output impedance from the BJT.
Whites, EE 320
Lecture 29
Page 1 of 8
Lecture 29: MOSFET Small-Signal

Amplifier Examples.
We will illustrate the analysis of small-signal MOSFET
amplifiers through two examples in this lecture.
Example N29.1 (text example 4.10). Determine Av (neglecting

the effects of RG), Rin, and Rout for the circuit below given that
Vt = 1.5 V, kn W L = 0.25 mA/V2, and VA = 50 V.
(Fig. 4.38a)
The first step is to determine the DC operating point. The DC
equivalent circuit is:
Whites, EE 320
Lecture 29
=0
Page 2 of 8
ID
Since VGD = 0 < Vt the MOSFET is operating in the saturation

mode if I D 0 . Assuming operation in the saturation mode the
DC drain current from (4.22) is
1 W
2
(4.22)
I D = kn (VGS Vt ) (1 + VDS )
L
2
Notice in the circuit that VGS = VDS , so we will eventually create
a triatic equation in VGS for ID.
However, the last factor in (4.22) will be quite small for large VA
(small ). So, for simplicity we will neglect ro giving
1 W
2
(4.20)
I D kn (VGS Vt )
2
L
For this DC circuit
1
2
2
I D = 0.25 103 (VGS 1.5 ) = 1.25 104 (VGS 1.5 )
2
Notice in the circuit that VGS = VDS so that this last equation
becomes
2
I D = 0.125 (VDS 1.5 ) mA
(4.73),(1)
Also, by KVL
Whites, EE 320
Lecture 29
Page 3 of 8
VDS = 15 RD I D = 15 10,000 I D
(4.74),(2)
Substituting (2) into (1)

2
I D = 1.25 104 (15 10,000 I D 1.5 )
Solving this equation gives
I D = 1.06 mA VDS = 4.4 V(= VGS )
or
I D = 1.72 mA VDS = 2.2 V(= VGS )
This latter result is not consistent with the assumption of
operation in the saturation mode since VGS < Vt = 1.5 V. So the
proper solution for ID is the first ( I D = 1.06 mA).
Next, we construct the small-signal equivalent circuit. Well use
the small-signal model of the MOSFET with ro included:
(Fig. 4.38b)
W
(VGS Vt ) = 0.25 103 ( 4.4 1.5) = 0.725 mS
L
V
50
= 47.2 k
9 ro = A =
I D 1.06 mA
9 g m = k n
Recall from the previous lecture that the proper ID in the ro

calculation is that with = 0, which is what we ended up
calculating earlier.
Whites, EE 320
Lecture 29
Page 4 of 8
To compute the small-signal voltage gain, we start at the output

(assuming RG is extremely large RG ro || RD || RL )
vo g m vgs ( ro || RD || RL )
At the input notice that vgs = vi . Therefore
v
Av = o g m ( ro || RD || RL ) = g m (4,521) = 3.28 V/V
vi
Notice that the assumption RG ro || RD || RL is met and hugely
exceeded since 10 M >> 4,521 .
For the input resistance Rin calculation, we cannot set vgs = 0
and subsequently open circuit the dependent current source
since this would artificially force Rin = 0 . Rather, we need to
determine ii as a function of vi and use this in the definition:
v
Rin i
ii
The dependent current source will remain in these calculations.
Proceeding, at the input of the small-signal equivalent circuit

shown above
v v
v v v
ii = i o = i 1 o = i (1 Av )
RG
RG vi RG
v
ii = i (1 + 3.28)
Therefore,
RG
Consequently, using this expression we find that
v
R
Rin = i = G = 2.34 M
ii 4.28
Whites, EE 320
Lecture 29
Page 5 of 8
Lastly, to determine the output resistance, we can set vgs = 0 in

the small-signal equivalent circuit above, which will open circuit
the dependent current source leading to the equivalent circuit:
from which we see that

Rout = RG || ro || RD = 8.24 k
Example N29.2 (text exercise 4.23). Determine the following

quantities for the conceptual MOSFET small-signal amplifier of
Fig. 4.34 given that VDD = 5 V, RD = 10 k, and VGS = 2 V.
0.2sin (t ) V =
2V=
(Fig. 4.34)
The MOSFET characteristics are Vt = 1 V, kn = 20 A/V2, W/L
= 20, and = 0.
Whites, EE 320
Lecture 29
Page 6 of 8
(a) Determine ID and VD. We see from the circuit that VGS > Vt .
Therefore, the MOSFET is operating in the saturation or
triode mode. Well assume saturation. In that case
1 W
1
2
I D = kn (VGS Vt ) = 20 106 20(2 1) 2 = 0.2 mA
L
2
2
VD = VDD I D RD = 3 V
and
Lets check if the MOSFET is operating in the saturation
mode:
VGD = 2 3 = 1 < Vt
Therefore, the MOSFET is indeed saturated, as assumed.
(b) Determine gm. Using (4.61)
W
g m = kn (VGS Vt ) = 20 106 20 (2 1) = 4.0 mS
L
(c) Determine the voltage gain Av. We begin by first
constructing the small-signal equivalent circuit
vgs
g m vgs
Directly from this circuit,

vo = g m vgs RD
vo
Whites, EE 320
so Av =
Lecture 29
Page 7 of 8
vo
= g m RD = 0.4 103 10 103 = 4 V/V
vgs
(d) If vgs = 0.2sin (t ) V, find vd and the max/min vD.

v
Av o vd = Av vgs = 4 0.2sin (t )
vgs
Therefore,
vd = 0.8sin (t ) V
Hence,
while
vD max = VD + Vd = 3 + 0.8 = 3.8 V

vD min = VD Vd = 3 0.8 = 2.2 V
(e) Determine the second harmonic distortion. From (4.57) or

(6) in the previous lecture notes, the drain current is given as
W
1 W
iD = I D + kn (VGS Vt ) vgs + kn vgs2
L
2
L
1
or iD = I D + 20 106 20(2 1)vgs + 20 10 6 20vgs2
2
3
3 2
= I D + 0.4 10 vgs + 0.2 10 vgs
Substituting vgs = 0.2sin (t ) into this equation gives
iD = I D + 80 106 sin (t ) + 8 106 sin 2 (t )
Using the trigonometry identity
sin 2 (t ) = 1 2 1 2cos ( 2t )
this last expression becomes
iD = 200 + 80sin (t ) + 4 4cos ( 2t ) A
iD = 204 + 80sin (t ) 4cos ( 2t ) A
or
Whites, EE 320
Lecture 29
Page 8 of 8
The first term in iD is ID, the DC current. We see that there is

a slight shift upward in value by 4 A.
The third term in iD is the second harmonic term because it
varies with time at twice the frequency of the input signal.
The second harmonic distortion is
4
100% = 5 %
80
Whites, EE 320
Lecture 30
Page 1 of 8
Lecture 30: Biasing MOSFET

Amplifiers. MOSFET Current Mirrors.
There are two different environments in which MOSFET
amplifiers are found, (1) discrete circuits and (2) integrated
circuits (ICs). The methods of biasing transistor amplifiers are
different in these two environments.
Why? Primarily because its expensive to fabricate resistors
(and large capacitors) on ICs. Of course, this is not a problem
for discrete component circuits.
We will discuss these two environments separately.
Biasing Discrete MOSFET Amplifier Circuits

The methods we can use here are virtually identical to the BJT
amplifier circuits we saw in Chapter 5. A few of these biasing
topologies are:
(Fig. 4.30d)
Whites, EE 320
Lecture 30
(Fig. 4.32)
Page 2 of 8
(Fig. 4.33a)
Example N30.1. Design the MOSFET amplifier below so that

I D = 1 mA and allow for a drain voltage swing of 2 V. The
amplifier is to present a 1-M input resistance to a capacitively
coupled input signal. The transistor has kn W L = 0.5 mA/V2
and Vt = 2 V.
I D = 1 mA
vi
vo
Whites, EE 320
Lecture 30
Page 3 of 8
We can see directly from this circuit that at DC, VG = 0 . Recall

that for operation in the saturation mode VGD Vt (with VGS > 0 ).
Now, for 2 -V swing in vo and large AC gain, we want RD to be
large. Hence, lets choose VD = 0 (since Vt = 2 V). Then for this
2 -V swing in vo
VGD min = 0 2 = 2 V < Vt
and
VGD max = 0 + 2 = 2 V = Vt
Because of these results, the MOSFET stays in saturation.
Consequently, with VD = 0
V VD 10 0
RD = DD
=
= 10 k
1 mA
1 mA
For a saturated MOSFET
1 W
2
2
I D = kn (VGS Vt ) = 0.25 103 (VGS 2 )
2
L
For I D = 1 mA
(VGS 2) 2 = 4
or
VGS = 2 + 2 = +4 V or 0 V.
With VG = 0 and VGS = 4 V then VS = 4 V. Hence,

4 ( 10 )
= 6 k
RS =
1 mA
Lastly, for a 1-M AC input resistance, then referring to the

input portion of the small-signal model
Whites, EE 320
Lecture 30
vgs
Page 4 of 8
g m vgs
vo
we see that
Rin = RG RG = 1 M
Biasing IC MOSFET Amplifiers. Current Mirrors.

For MOSFET amplifier biasing in ICs, DC current sources are
usually used. As discussed in Lecture 17, golden currents are
produced using sophisticated multi-component circuits. Then
current mirroring (aka current steering) circuits are used to
replicate this golden current to provide DC biasing currents at
different points in the IC.
The basic MOSFET current mirror is shown in Fig. 4.33b for
NMOS. (This is basically the same circuit we saw with the BJT
current mirror in Lecture 17.)
Whites, EE 320
Lecture 30
Page 5 of 8
(Fig. 4.33b)
Q1 has the drain and gate terminals connected together. This
forces Q1 to operate in the saturation mode in this particular
circuit if I D1 0 . In this mode
1
W
2
I D1 = kn1 1 (VGS Vt1 )
(4.50),(1)
2
L1
With a zero gate current,
I REF = I D1
(2)
where we can easily see from the above circuit that
V V ( VSS )
I REF = DD GS
(4.51),(3)
R
Now, well assume the two MOSFETs in the circuit have the
same VGS. Consequently, the drain current in the second
transistor is
1
W
2
I D 2 = kn 2 2 (VGS Vt 2 )
(4)
2
L2
Whites, EE 320
Lecture 30
Page 6 of 8
If these two transistors are perfectly matched but perhaps

fabricated with different channel dimensions, then kn1 = kn 2 ,
and Vt1 = Vt 2 so that we see by comparing (1) and (4) that
W L
W L
I D 2 = 2 2 I D1 = 2 2 I REF
(4.53),(5)
W1 L1
W1 L1
In this NMOS current mirror shown above, Q2 acts as a current
sink since it pulls current I O = I D 2 from the load, which is the
amplifier circuit of Fig. 4.33a in this case.
In PMOS this current mirror circuit is constructed as
VDD
Q2
Q1
0
IO = I D 2
R
I REF
To amplifier circuit
Here Q2 acts as a current source since it pushes current I O = I D 2

into the load.
Example N30.2. Design an NMOS current mirror with VDD = 5

V, VSS = 0, and I REF = 100 A. For the matched transistors
L = 10 m, W = 100 m, Vt = 1 V, and kn = 20 A/V2.
Whites, EE 320
Lecture 30
Page 7 of 8
Referring to the NMOS current mirror circuit in Fig. 4.33b

above, notice that the drain of Q1 is connected to its gate so that
VGD1 = 0 , which is less than Vt. This means Q1 is operating in the
saturation mode (or is possibly cutoff).
Assuming operation in saturation,
1 W
2
I D1 = I REF = kn (VGS Vt )
L
2
1
100
2
= 20 106
(VGS 1)
2
10
For I REF = 100 A 100 = 10 10 (VGS 1) or
VGS = 1 + 1 = 2 V or 0 V
2
Now, by KVL
VDD = I REF R + VGS
With VGS = 2 V then

R=
52
VDD VGS
=
= 30 k
100 A
I REF
Here are a few additional questions based on this design:

What is the lowest possible value for VO = VD 2 and still have a
functioning current mirror?
As with Q1, the transistor Q2 must also operate in saturation if
its going to supply a constant current.
Whites, EE 320
Hence
Therefore,
Lecture 30
Page 8 of 8
VGD 2 Vt VG 2 VD 2 Vt
VO = VD 2 VG 2 Vt
or VO VGS Vt = 2 1 = 1 V
VO min = 1 V
Imagine that VA = 107 L . (Notice that VA is proportional to the

channel length, which is commonplace.) What is ro?
VA = 107 10 106 = 100 V
V
100 V
ro = A =
= 1 M
I O 100 A
What is change in the output current IO if VO changes by 3 V?
V
3V
= 3 A
IO = O =
ro
1 M
Whites, EE 320
Lecture 31
Page 1 of 5
Lecture 31: Common Source Amplifier.

Weve studied MOSFET small-signal equivalent models and the
biasing of MOSFET amplifiers in the previous three lectures.
Well now apply those skills by looking closely at three basic
MOSFET amplifier types:
1. Common source amplifiers, including configurations with a
source resistor (called source degeneration).
2. Common gate amplifiers.
3. Common drain (or source follower) amplifiers.
All of these amplifier types are appropriate for discrete
component designs. In the case of IC amplifiers, well also show
corresponding designs implemented in CMOS, beginning in
Lecture 33.
Common Source Small-Signal Amplifier

This type of amplifier is shown in Fig. 4.43a, as biased by a
combination of voltage and current sources:
Whites, EE 320
Lecture 31
Page 2 of 5
(Fig. 4.43a)
Assuming sufficiently large values for the coupling capacitors
(CC1 and CC2) and the bypass capacitor (CS) so that their
reactances are very small at the frequency of operation the
equivalent small-signal circuit for this amplifier is shown in Fig.
4.43(b):
(Fig. 4.43b)
The text mentions performing the small-signal analysis directly
on the amplifier circuit, as illustrated in Fig. 4.43(c). We do not
recommend this approach. It is better to take the time and
construct the small-signal equivalent circuit, as were doing
here.
Whites, EE 320
Lecture 31
Page 3 of 5
Small-Signal Amplifier Characteristics

As we did when studying BJT amplifiers, well calculate the
following quantities for this MOSFET common source
amplifier: Rin, Av, Gv, Gi, and Rout.
Input resistance, Rin. From the small-signal circuit above, and
noting that ig = 0 , then
(4.78),(1)
Rin = RG
Partial small-signal voltage gain, Av. From the output side of
the small-signal circuit
vo = g m vgs ( ro || RD || RL )
(2)
while at the input,
vi = vgs
(3)
Substituting (3) into (2), we find that the partial voltage gain
as
v
Av o = g m ( ro || RD || RL )
(4.80),(4)
vi
Overall small-signal voltage gain, Gv. As we did with BJT

amplifiers, we can derive an expression for Gv in terms of Av.
By definition,
Whites, EE 320
Lecture 31
Gv
vo
v v
v
= i o = i Av
vsig vsig vi vsig
N
Page 4 of 5
(5)
= Av
Applying voltage division at the input of the small-signal

equivalent circuit,
RG
Rin
vi =
vsig =
vsig
(6)
N
Rin + Rsig
R
+
R
(1) G
sig
Substituting (6) into (5) and using (4) we find
RG
Gv =
g m ( ro || RD || RL )
RG + Rsig
(4.82),(7)
Overall small-signal current gain, Gi. Using current division

at the output in the small-signal model above
ro || RD
(8)
io =
g m vgs
ro || RD + RL
while at the input,
vgs = ii RG
(9)
Substituting (9) into (8) we find that the overall small-signal
current gain is
i
ro || RD
Gi o =
g m RG
(10)
ii ro || RD + RL
Notice that as RG in this last expression, Gi . Is this
a problem? (To help answer this question, notice that as
RG , ii 0 .) Also, what does Gi as RG mean
for the overall small-signal output power of this amplifier?
Whites, EE 320
Lecture 31
Page 5 of 5
Output resistance, Rout. To calculate the output resistance, we

first set vsig = 0 , which also means that g m vgs = 0 . The input
impedance of the dependent current source is infinite.
Consequently,
(4.85),(11)
Rout = ro || RD
Summary
In summary, we find for the CS small-signal amplifier that it has
a
o High input resistance [see (1)].
o Relatively high small-signal voltage gain [see (7)].
o Very high small-signal current gain [see (10)].
o Relatively high output resistance [see (11)].
Whites, EE 320
Lecture 32
Page 1 of 9
Lecture 32: Common Source Amplifier with

Source Degeneration.
The small-signal amplification performance of the CS amplifier
discussed in the previous lecture can be improved by including a
series resistance in the source circuit. (This is very similar if
not identical to the effect of adding emitter degeneration to the
BJT CE amplifier.) This so-called CS amplifier with source
degeneration circuit is shown in Fig. 4.44(a).
vO
(Fig. 4.44a)
We have a choice of small-signal models to use for the
MOSFET. A T model will simplify the analysis, on one hand, by
allowing us to incorporate the effects of RS by simply adding
this value to 1/gm in the small-signal model, if we ignore ro.
Whites, EE 320
Lecture 32
Page 2 of 9
This small-signal circuit is shown in Fig. 4.44(b).
(Fig. 4.44b)
On the other hand, using the T model makes the analysis more
difficult when ro is included. (The hybrid model is better at
easily including the effects of ro.) However, ro in the MOSFET
amplifier is large so we can reasonably ignore its effects for now
in the expectation of making the analysis more tractable.

Well now calculate the following small-signal quantities for
this MOSFET common source amplifier with source
degeneration: Rin, Av, Gv, Gi, and Rout.
Whites, EE 320
Lecture 32
Page 3 of 9
Input resistance, Rin. Referring to the small-signal equivalent

circuit above in Fig. 4.44(b), with ig = 0 , then
(4.84),(1)
Rin = RG
Partial small-signal voltage gain, Av. We see at the output side
of the small-signal circuit in Fig. 4.44(b)
vo = g m vgs ( RD || RL )
(2)
which is the same result (ignoring ro) as we found for the CS
amplifier without source generation. At the gate, however, we
find through voltage division that
1 / gm
vi
vgs =
vi =
(4.86),(3)
1 / g m + RS
1 + g m RS
This is a different result than for the CS amplifier in that vgs is
only a fraction of vi here, whereas vgs = vi without RS.
Substituting (3) into (2), gives the partial small-signal AC

voltage gain to be
g ( R || R )
v
Av o = m D L
(4.88),(4)
vi
1 + g m RS
Overall small-signal voltage gain, Gv. As we did in the
previous lecture, we can derive an expression for Gv in terms
of Av. By definition,
v
v v
v
(5)
Gv o = i o = i Av
vsig vsig vi vsig
N
= Av
Whites, EE 320
Lecture 32
Page 4 of 9
Applying voltage division at the input of the small-signal

equivalent circuit in Fig. 4.44(b),
RG
Rin
vi =
vsig =
vsig
(6)
N
Rin + Rsig
R
+
R
(1) G
sig
Substituting (6) into (5) we the overall small-signal AC
voltage gain for this CS amplifier with source degeneration to
be
RG g m ( RD || RL )
Gv =
(4.90),(7)
RG + Rsig 1 + g m RS
at the output in the small-signal model above in Fig. 4.44(b)
RD
io =
g m vgs
(8)
RD + RL
while at the input,
v 1 + g m RS
(9)
ii = i =
vgs
N
RG (3) RG
Substituting (9) into (8) we find that the overall small-signal
AC current gain is
i
g m RD
RG
(10)
Gi o =
ii RD + RL 1 + g m RS
Output resistance, Rout. From the small-signal circuit in Fig.

4.44(b) with vsig = 0 then i must be zero leading to
Rout = RD
(11)
Whites, EE 320
Lecture 32
Page 5 of 9
Discussion
Adding RS has a number of effects on the CS amplifier. (Notice,
though, that it doesnt affect the input and output resistances.)
First, observe from (3)
vi
(3)
1 + g m RS
that we can employ RS as a tool to lower vgs relative to vi and
lessen the effects of nonlinear distortion.
vgs =
This RS also has the effect of lowering the small-signal voltage

gain, which we can directly see from (7).
A major benefit, though, of using RS is that the small-signal
voltage (and current) gain can be made much less dependent on
the MOSFET device characteristics. (We saw a similar effect in
the CE BJT amplifier with emitter degeneration.)
We can see this here for the MOSFET CS amplifier using (7)
RG g m ( RD || RL )
Gv =
(7)
RG + Rsig 1 + g m RS
The key factor in this expression is the second one. In the case
that g m RS 1 then
Whites, EE 320
Lecture 32
Gv
RG RD || RL
RG + Rsig RS
Page 6 of 9
(12)
which is no longer dependent on gm.

Conversely, without RS in the circuit ( RS = 0 ), we see from (7)
that Gv g m and is directly dependent on the physical properties
of the transistor (and the biasing) because
i
W
g m d = kn (VGS Vt )
(4.61),(13)
vgs
L
in the case of an NMOS device.
The price we pay for this desirable behavior in (12) where
Gv is not dependent on gm is a reduced value for Gv. This Gv is
largest when RS = 0 , as can be seen from (7).
Example N32.1 (based on text exercises 4.32 and 4.33).

Compute the small-signal voltage gain for the circuit below with
RS = 0 , kn W L = 1 mA/V2, and Vt = 1.5 V. For a 0.4-Vpp
sinusoidal input voltage, what is the amplitude of the output
signal?
Whites, EE 320
Lecture 32
Page 7 of 9
W
mA
kn = 1 2
L
V
Vt = 1.5 V
vO
For the DC analysis, we see that VG = 0 and I D = I S = 0.5 mA.

(Why is VG = 0 ?) Consequently,
VD = 10 RD I D = 10 14k 0.5m = 3 V
Assuming MOSFET operation in the saturation mode
1 W
2
I D = kn (VGS Vt )
2
L
1
2
0.5 mA = 1 103 (VGS 1.5 )
such that
2
VGS 1.5 = 1 VGS = 2.5 V or 0.5 V
or
VS = 2.5 V
Therefore,
for operation in the saturation mode.
For the AC analysis, from (13)
g m = 103 ( 2.5 1.5 ) = 1 mS
Using this result in (7) with RS = 0 gives
Whites, EE 320
Lecture 32
Page 8 of 9
4.7M
V
103 (14k ||14k ) = 6.85
4.7M + 100k
V
For an input sinusoid with 0.4-Vpp amplitude, then
Vo = Gv Vsig = 6.85 0.4 Vpp = 2.74 Vpp
Gv =
Will the MOSFET remain in the saturation mode for the entire
cycle of this output voltage? For operation in the saturation
mode, vDG = vD > Vt = 1.5 V. On the negative swing of the output
voltage,
v
2.74
vD min = VD o ,pp = 3
= 1.63 V
2
2
which is greater than Vt, so the MOSFET will not leave the
saturation mode on the negative swings of the output voltage.
On the positive swings,
v
2.74
vD max = VD + o ,pp = 3 +
= 4.37 V
2
2
which is less than VDD = 10 V so the MOSFET will not cutoff
and leave the saturation mode.
(Interestingly, the MOSFET does leave the saturation mode on
the negative swings for RD = RL = 15 k, as used in the text
exercises 4.32 and 4.33.)
Lastly, imagine that for some reason the input voltage is
increased by a factor of 3 (to 1.2 Vpp). What value of RS can be
used to keep the output voltage unchanged?
Whites, EE 320
Lecture 32
Page 9 of 9
From (7), we can choose RS so that the so-called feedback factor

1 + g m RS equals 3. The output voltage amplitude will then be
unchanged with this increased input voltage.
Hence, for
3 1
2
= 3 = 2 k.
g m 10
With RS = 2 k the new overall small-signal AC voltage gain is
from (7)
V
6.85
6.85
Gv =
=
= 2.28
1 + g m RS
3
V
The overall small-signal voltage gain has gone down, but the
amplitude of the output voltage has stayed the same since the
input voltage amplitude was increased.
1 + g m RS = 3 RS =
Whites, EE 320
Lecture 33
Page 1 of 8
Lecture 33: CMOS Common

Source Amplifier.
As was mentioned in Lecture 30, there are two different
environments in which MOSFET amplifiers are found, (1)
discrete circuits and (2) integrated circuits (ICs). We will now
begin to look at the IC MOSFET amplifiers.
There are three basic configurations of IC MOSFET amplifiers:
VDD
I
vO
vI
vO
vO
vI
vI
Common source
Common gate
-VSS
Common drain
(source follower)
As was also mentioned in Lecture 30, large-valued resistors and

capacitors are not often used in these IC environments. Instead,
active loads are incorporated using MOSFETs as loads. In the
amplifier circuits shown above, the active loads are actually the
nonideal current sources. [Also notice that there are no bypass
capacitors as we saw with discrete MOSFET (and BJT)
amplifiers.]
Whites, EE 320
Lecture 33
Page 2 of 8
We will look at all three of these amplifiers more closely over

the next few lectures. The intention is to pair the discrete version
of the MOSFET amplifier with its IC version. Since weve
covered the CS amplifier in discrete form already, well begin
with the analysis of the CMOS CS amplifier.
CMOS Common Source Amplifier

An example of a complementary MOSFET amplifier is shown
in text Figure 6.18(a):
(Fig. 6.18a)
In this circuit, Q2 and Q3 form a PMOS current mirror. Because
both PMOS and NMOS devices are used in this circuit, it is
called a complementary MOS (CMOS) circuit.
In addition to forming part of the current mirror, Q2 also
functions as the current source load (aka active load) for Q1.
Whites, EE 320
Lecture 33
Page 3 of 8
For Q2 to be a current source, Q2 must operate in the saturation

mode, of course. The output resistance ro2 of Q2 is
|V |
(6.47),(1)
ro 2 = A 2
I REF
It is helpful to observe the characteristic curve for Q2 to
understand its active-load role:
(Fig. 6.18b)
Referring to the CS amplifier circuit above in Fig. 6.18(a), when
i = I REF then VGD 2 = 0 (by symmetry with Q1). This implies that
v = VSG , which is the Q point shown in Fig. 6.18(b).
Furthermore, it is useful to observe the graphical construction of
the transfer function vO/vI for this amplifier, as illustrated in
Figs. 6.18(c) and (d) shown below. The drain currents of Q1 and
Q2 are the same. The operating point of the amplifier is found
Whites, EE 320
Lecture 33
Page 4 of 8
from the intersection of the Q1 characteristic curve with the load

curve of Q2 for a particular vGS1:
vO = VDD v
= iD 2
(Fig. 6.18c)
Collecting these intersections from this figure as vGS1 ( = vI )
changes, we can construct point-by-point the transfer
characteristic curve for this amplifier:
(Fig. 6.18d)
From this plot, we can see that Region III shows a linear
relationship between vO and vI. This is the region where the
circuit of Fig. 6.18(a) can be used as a linear amplifier.
Whites, EE 320
Lecture 33
Page 5 of 8
Small-Signal Voltage Gain and Output Resistance

Now well determine the small-signal voltage gain and output
resistance of this amplifier. The small-signal equivalent circuit
for this CMOS CS amplifier is:
vgs1
g m1vgs1
vo
Rout
It is important to recognize that no small-signal model is needed

for Q2 because its affect on the signal vo can be incorporated
using the small-signal resistance ro2 as shown above.
So, at the output
while at the input
vo = g m1vgs1 ( ro1 || ro 2 )
(2)
vgs1 = vi
(3)
Substituting (3) into (2) gives the open circuit small-signal

voltage gain for the CMOS CS amplifier to be
v
Avo o = g m1 (ro1 || ro 2 )
(6.49),(4)
vi
or substituting for gm1, ro1, and ro2
Whites, EE 320
Lecture 33
W
2 k n
L 1
Avo =
1
1
+
VA1 VA 2
Page 6 of 8
1
I REF
(5)
Since ro1 and ro2 are usually large, this Avo gain is typically
relatively large (approximately -20 to -100, or so).
Neat! We have incorporated the effects of relatively large
resistance for this amplifier without having to actually construct
a large resistor.
From the small-signal model we see from inspection that
Rout = ro1 || ro 2
Summary for CMOS CS amplifier:
1. Very large input resistance.
2. Very large output resistance.
3. Potentially large small-signal voltage gain.
Example N33.1 (similar to text exercise 6.15). A CMOS CS

amplifier shown in Fig. 6.18(a) is fabricated with
W L = 100 m 1.6 m for all transistors. With kn = 90 A/V2,
k p = 30 A/V2, I REF = 100 A, VAn = 8 V/m, and VAp = 12
V/m, determine the following quantities:
Whites, EE 320
Lecture 33
Page 7 of 8
(a) Find gm1. The common expression for gm we use is

W
(4.61),(6)
g m = kn (VGS Vt )
L
For a MOSFET in the saturation mode
1 W
2
I D = kn (VGS Vt )
(4.54),(7)
L
2
Substituting (7) into (6) gives the transconductance for Q1
in terms of ID1 to be
W
g m1 = 2kn I D1
(4.70),(8)
L
1
[This form of gm was actually used earlier in (5).] Because
the amplifier is biased so that I D1 = I REF , then
100
100 106 = 1.06 mA/V2
gm1 = 2 90 106
1.6
(b) Find ro1.
ro1 =
| VA |1 VAn
8 1.6
=
=
= 128 k
I D1
I REF 100 106
(c) Find ro2.

| VA |2 VAp
12 1.6
=
=
= 192 k
ro2 =
ID2
I REF 100 106
(d) Find Avo.
Avo = g m ( ro1 || ro 2 ) = 1.06 103 (128 k ||192 k)
Whites, EE 320
Lecture 33
Page 8 of 8
V
V
This value represents the largest gain. The gain will be
reduced when an actual load is attached to the amplifier.
Avo = 81.4
Whites, EE 320
Lecture 34
Page 1 of 9
Lecture 34: MOSFET Common Gate

Amplifier.
Well continue our discussion of discrete MOSFET amplifiers
we began with the common source amplifier in Lectures 31 and
32.
Here well cover the common gate amplifier, which is shown in
Fig. 4.45. It has a grounded gate terminal, a signal input at the
source terminal, and the output taken at the drain.
(Fig. 4.45a)

As weve done with previous amplifiers in this course, well
calculate the following small-signal quantities for this MOSFET
Whites, EE 320
Lecture 34
Page 2 of 9
common gate amplifier: Rin, Av, Avo, Gv, Gi, Ais, and Rout. To
begin, we construct the small-signal equivalent circuit:
(Fig. 4.45b)
The T model was used since we ignored ro while Rsig appears in
series with 1/gm.
Input resistance, Rin. Because the gate is grounded, we can see
directly from this small-signal equivalent circuit that
1
Rin =
(4.91),(1)
gm
Actually, this result may not be that readily apparent to you

since while the gate is grounded, the current in the gate is zero
( ig = 0 ).
To verify this result in (1), we can apply a voltage source vx at
the source terminal and calculate the ratio of this voltage to
Whites, EE 320
Lecture 34
Page 3 of 9
the current directed into the source terminal, which well

define as ix:
vo
i = g m vgs
At the input to this circuit

vx 0
= ix ix = g mvgs
1 / gm
This current ix doesnt flow through the gate terminal! Instead,
ix flows through the dependent source, then to ground. Indeed,
we see that
ix = g mvgs = i
Tricky! In any event, the input resistance in (1) has been
verified.
Partial small-signal voltage gains, Av and Avo. At the output
side of the small-signal circuit
vo = g m vgs ( RD || RL )
(2)
At the input, we can see that because the gate is grounded
Whites, EE 320
Lecture 34
vi = vgs
Page 4 of 9
(3)

voltage gain to be
v
Av o = g m ( RD || RL )
(4.94),(4)
vi
In the case of an open circuit load ( RL ), the small-signal
voltage gain becomes
Avo Av R = g m RD
(4.95),(5)
L
Overall small-signal voltage gain, Gv. Using voltage division

at the input to the small-signal equivalent circuit
Rin
vi =
vsig
(6)
Rin + Rsig
Substituting this into
Gv
vo
v v
v
= i o = i Av
vsig vsig vi vsig
N
(7)
= Av
gives the overall small-signal voltage gain of this common

gate amplifier to be
v
Rin
Gv o =
g m ( RD || RL )
(4.96a),(8)
vsig Rin + Rsig
More specifically, using (1) in this expression
g ( R || R )
Gv = m D L
1 + g m Rsig
(4.96b),(9)
Whites, EE 320
Lecture 34
Page 5 of 9

at the output in the small-signal circuit above
RD
io =
g m vgs
(10)
RD + RL
Because ig = 0 , then at the input we see that
ii = g mvgs
(11)
Substituting (11) into (10) gives the overall small-signal AC
current gain to be
i
RD
Gi o =
(12)
ii RD + RL
Short-circuit small-signal current gain, Ais. The short circuit
small-signal AC current gain can be easily determined from
(12) with RL = 0 as
Ais Gi R =0 = 1
(13)
L
Output resistance, Rout. From the small-signal circuit above

with vsig = 0 we find that i = 0 since the gate is grounded.
Consequently,
Rout = RD
(4.97),(14)
Summary
In summary, we find for the CG small-signal amplifier:
o A non-inverting amplifier.
Whites, EE 320
Lecture 34
Page 6 of 9
o Moderate input resistance [see (1)].

o Moderately large small-signal voltage gain [see (9)], but
smaller than CS amplifier.
o Small-signal current gain less than one [see (12)].
o Potentially large output resistance (dependent on RD)
[see (14)].
Similar to the BJT CB amplifier we discussed in Lecture 20, the

CG amplifier finds use as a current buffer amplifier. It has the
relatively small input resistance, relatively large output
resistance, and Gi less than (and potentially near) one
characteristics of such amplifiers. (Does this amplifier provide
any power gain for a signal?)
Example N34.1 (based on text exercise 4.34). Use the circuit of

Fig. E4.30 to design a common gate amplifier. Find Rin, Rout, Avo,
Av, Gv, and Gi for RL = 15 k and Rsig = 50 . What will the
overall voltage gain become for Rsig = 50 ? 10 k? 100 k?
The DC analysis results are shown in Fig. E4.30:
Whites, EE 320
Lecture 34
Page 7 of 9
(Fig. E4.30)
Using (4.71)
gm =
2 I D 2 0.5 m
=
= 1 mS
VOV 2.5 1.5
Based on this DC biasing, the corresponding common gate

amplifier circuit is:
vO
Whites, EE 320
Lecture 34
Page 8 of 9
The small-signal equivalent circuit for this amplifier is:

D
g m vgs
G
4.7 M
vo
RD=
15 k
RL=
15 k
ig=0
1/gm
Rout
Rsig
+
vsig
-
Rin
The 4.7-M resistor functions to force the gate to ground

potential. But since ig = 0 , it will have no other impact on the
circuit.
From (1), Rin =
1
1
= 3 = 1 k.
g m 10
From (14), Rout = RD = 15 k.

From (5), Avo = g m RD = 103 15 103 = 15
V
V
From (4), Av = g m ( RD || RL ) = 103 (15k ||15k ) = 7.5
V
V
Whites, EE 320
Lecture 34
g m ( RD || RL )
Av
7.5
=
=
N
1 + g m Rsig ( 4) 1 + g m Rsig 1 + 103 50
V
= 7.14
V
RD
15
1 A
=
=
From (12), Gi =
RD + RL 15 + 15 2 A
From (9), Gv =
Page 9 of 9
(15)
What is the overall voltage gain when:

o Rsig = 1 k? From (15),
Av
7.5
V
Gv =
=
=
3.75
1 + g m Rsig 1 + 103 103
V
7.5
V
o Rsig = 1 0 k? Gv =
=
0.68
1 + 103 10 103
V
7.5
V
o Rsig = 1 00 k? Gv =
=
0.074
1 + 103 100 103
V
We see from these calculations that the overall voltage gain

decreases substantially as Rsig increases. Can you explain what
is physically happening to cause this to occur?
Whites, EE 320
Lecture 35
Page 1 of 12
Lecture 35: CMOS Common Gate Amplifier.

The IC version of the common gate amplifier with an active load
is shown below implemented in CMOS:
The common gate amplifier functions similar to a BJT common

base amplifier as we discovered in Lecture 34.
In the CMOS implementation of this amplifier shown above, Q2
and Q3 function as a current mirror (as with the CMOS common
source amplifier we studied in Lecture 33) with Q2 further
serving as an active load.
There is one subtlety with this IC amplifier that can affect its
performance thats not found in the other two types of CMOS
amplifiers. Its called the body effect. Well first study this
MOSFET body effect and then come back to the analysis of the
CMOS CG amplifier.
Whites, EE 320
Lecture 35
Page 2 of 12
MOSFET Body Effect

In ICs, the body or substrate is shared amongst all (or most) of
the transistors.
G
S
D
n-channel
n+
etio
Depl
ion
n reg
n+
p-type substrate (body)
(Fig. 1)
To guarantee that the body-to-source junction (and the other

parts of the channel) remain reversed biased for all transistors in
the IC, the substrate is connected to VSS , which is the smallest
voltage in the circuit:
The reason is that if any body-to-source pn junctions (or any

other parts of the channel) become forward biased, there would
be a catastrophic failure in the transistor operation!
Whites, EE 320
Lecture 35
Page 3 of 12
To avoid this problem, one idea is to just connect the body

terminal to the source terminal for all transistors in the IC.
For the common gate amplifier, however, we see there is a
problem in doing this. For circuits with input at the source (such
as the common gate amplifier), we dont want the source
connected to the most negative voltage in the circuit (or
whatever voltage is assigned to the body).
So instead, well connect VB to -VSS. The question now is what
affect will this have on the device operation? Referring to Fig. 1,
the resulting reverse-bias voltage between the source and body
(VSB for NMOS):
1. Will widen the depletion region.
2. This, in turn, will decrease the channel depth. (To return the
channel to its original depth, vGS would need to be increased.)
It can be shown that this effect of VSB on the channel can be
modeled as simply a change in the threshold voltage according
to
Vt = Vt 0 + 2 f + VSB 2 f [V]
(4.33),(1)
where
Vt 0 is the threshold voltage for VSB = 0
2 f is the material dependent Fermi potential (often 2 f 0.6
V for NMOS)
Whites, EE 320
Lecture 35
Page 4 of 12
is a fabrication process parameter (the body-effect

parameter) given as
2qN A s
=
[V1/2]
(4.34),(2)
Cox
(often 0.4 V1/2).
Notice in (1) that with this body effect a change in VSB produces
a change in Vt. This change in Vt will change iD, even though vGS
doesnt change. (Why? Because the channel depth changes with
changing VSB, as weve just learned.)
Consequently, this body voltage VSB controls iD like vGS does.
In other words, the body is acting like a second gate (of sorts),
sometimes called the backgate.
This phenomenon is called the body effect. It can degrade the
performance of MOSFET amplifiers in some cases.
Small-Signal Modeling of the Body Effect

A change in the body-to-source voltage vBS will cause a change
in the drain current iD, as weve just seen. This behavior can be
quantified for time varying signals by the relationship
i d = g mb vbs
(3)
where gmb is the so-called body conductance
Whites, EE 320
Lecture 35
g mb
iD
vBS
Page 5 of 12
(4.75),(4)
vGS = constant
vDS = constant
It can be shown that
g mb = g m [S]
(4.76),(5)
where is dimensionless and typically lies in value between 0.1
and 0.3.
For small-signal modeling, in light of (3) a second dependent

current source is added to the MOSFET equivalent circuit, as
shown in Fig 4.41, which is dependent on vbs.
vgs
g m vgs
g mb vbs
vbs
(Fig. 4.41b)
Alternatively, the small-signal T model for the MOSFET
amplifier including the body effect is:
g m vgs + g mb vbs
( g m + g mb )
Whites, EE 320
Lecture 35
Page 6 of 12
Common Gate Amplifier with Active Load

The text models the active load for this CG amplifier as a simple
ideal current source as shown in Fig. 6.27(a):
(Fig. 6.27a)
Note here that the body terminal is not connected to the source
terminal, but rather is connected to the lowest voltage in the
circuit (ground). Because of this we need to account for the body
effect in the small-signal T model of this amplifier:
Whites, EE 320
Lecture 35
Page 7 of 12
io
g m vgs
vgs , vbs
vo
g mb vbs
iro
ii
vi
(Fig. 2)
Notice that weve incorporated the body effect into the T smallsignal model of the MOSFET. Because the gate and body are
both grounded in Fig. 2, then
vgs = vbs
(6)
Consequently, the body effect in this CG amplifier can be
completely accounted for by simply replacing gm of the
MOSFET with g m + g mb . That is,
g m g m + g mb = (1 + ) g m
(7)

Well calculate the following small-signal quantities for this
CMOS common gate amplifier: Rin, Av, Gv, Gi, and Rout.
Whites, EE 320
Lecture 35
Page 8 of 12
Input resistance, Rin. Using KCL at the source terminal in Fig.

2 as well as (6) we find
ii + ( g m + g mb ) vgs = iro
(8)
An important insight into this circuit can be realized by
examining the supernode contained in the dashed outline in
the small-signal circuit. Because ig = ib = 0 , applying KCL to
this supernode
io = ii
(9)
Since vgs = vi and
v v
v i R
vi ii RL
(6.82),(10)
iro = i o = i o L =
N
ro
ro
ro
(9)
then (8) becomes
v
R
(11)
ii = ( g m + g mb )( vi ) + i ii L
ro
ro
From this result, we can quickly determine that
v
ro + RL
Rin i =
(6.83),(12)
ii 1 + ( g m + g mb ) ro
We see from this expression that the body effect tends to
reduce the input resistance.
Notice that Rin depends on RL. This type of amplifier is called
a bilateral amplifier, in contrast to a unilateral amplifier in
which Rin is not dependent on RL.
Partial small-signal voltage gain, Av. At the output side of the

small-signal circuit
Whites, EE 320
Lecture 35
vo = io RL =
N ii RL
Page 9 of 12
(6.89),(13)
(9)
while at the input
vi = ii Rin
(6.90),(14)
Dividing these two equations we arrive at the partial smallsignal voltage gain
RL 1 + ( g m + g mb ) ro
vo RL
(6.91),(15)
Av =
=
N
vi Rin (12)
ro + RL
Here we see that the body effect tends to increase Av.
Overall small-signal voltage gain, Gv. As we have done many

times in the past for other types of amplifiers
v
Rin
Gv o =
Av
(16)
vsig Rin + Rsig
Substituting for Av from (15) gives
RL
Gv =
Rin + Rsig
(6.93),(17)
Since the body effect tends to reduce Rin, we see from this
expression that it tends to increase Gv.
Overall small-signal current gain, Gi. From (9) we see directly

that
i
(18)
Gi o = 1
ii
Whites, EE 320
Lecture 35
Page 10 of 12
Output resistance, Rout. To determine Rout from the smallsignal circuit above we set vsig = 0 and apply a fictitious AC
voltage source vx at the output as shown:
ix
vgs
i1
iro
vs
(Fig. 3)
We can see that with vx attached, the voltage vgs will not
usually be zero. This means the current in the dependent
current source is also not zero. Consequently, we need to
analyze this circuit including the effects of the dependent
current source to determine the output resistance.
Employing KCL at the drain terminal
ix + iro = ( g m + g mb ) vgs
It is easy to see in Fig. 3 that
(19)
vs vx
(20)
ro
Applying KCL to the supernode indicated in Fig. 3, we find
i1 = ix
(21)
Because
iro =
Whites, EE 320
Lecture 35
Page 11 of 12
vs = i1Rsig =
N ix Rsig
(22)
(21)
then using this in (20) and substituting into (19)

R
v
ix + ix sig = ( g m + g mb ) vgs + x
ro
ro
From the small-signal circuit in Fig. 3
vgs = vs = ix Rsig
(23)
(24)

R
v
ix + ix sig + ( g m + g mb ) ix Rsig = x
ro
ro
or rearranging
v
Rout x = ro + 1 + ( g m + g mb ) ro Rsig (6.101),(25)
ix
We see from this result that the body effect tends to increase
Rout.
Since Rout depends on Rsig, this is another reason why this

amplifier is a bilateral rather than a unilateral amplifier.
Summary of the Small-Signal Characteristics

o A non-inverting amplifier [see (17) and (18)].
Whites, EE 320
Lecture 35
Page 12 of 12
o Moderately large input resistance. From (12), with

ro = O (105 ) , RL = O (103 ) , g m , g mb = O (103 ) , then from
(12), Rin = O (103 ) .
o Relatively modest small-signal voltage, depending on the
choices for RL and Rsig [see (17)].
o Small-signal current gain equal to one [see (18)].
o Potentially very large output resistance [see (25)].
These are characteristics similar to the discrete version of the

common gate amplifier we discussed in the previous lecture. No
surprise.
Example N35.1.
Whites, EE 320
Lecture 36
Page 1 of 10
Lecture 36: MOSFET Common Drain

(Source Follower) Amplifier.
The third, and last, discrete-form MOSFET amplifier well
consider in this course is the common drain amplifier. This type
of amplifier has the input signal fed at the gate similar to the
CS amplifier but the signal output is taken at the source
terminal, as shown in Fig. 4.46(a):
(Fig. 4.46a)

Well calculate the following small-signal quantities for this
MOSFET common gate amplifier: Rin, Av, Avo, Gv, Gi, Ais, and
Rout. To begin, we construct the small-signal equivalent circuit:
Whites, EE 320
Lecture 36
Page 2 of 10
g m vgs
Rsig
+
vsig
-
ii
+ ig=0
vi
RG vgs
Rin
1/gm
S
vo
Rout
RL
ro
io
(Fig. 4.46b)
Because the drain terminal is an AC ground, we shifted one end

of the output resistance ro so it appears in parallel with RL. This
makes the T model particularly well suited for the CD amplifier
since RL || ro appears in series with 1 g m .
Input resistance, Rin. With vsig = 0 and ig = 0 , we can see
directly from this small-signal equivalent circuit that
Rin = RG
(4.99),(1)
Partial small-signal voltage gains, Av and Avo. At the output
side of the small-signal circuit with ig = 0
vo = g m vgs ( RL || ro )
(2)
At the input, using voltage division

1 gm
vgs =
vi
1 g m + RL || ro
(3)
Whites, EE 320
Lecture 36
Page 3 of 10

voltage gain to be
v
RL || ro
Av o =
(4.102),(4)
vi RL || ro + 1 g m
Notice that if ro RL and RL 1 g m then
Av 3 1
In the case of an open circuit load ( RL ), the small-signal
partial voltage gain becomes
ro
(4.103),(5)
Avo Av R =
L
ro + 1 g m
Overall small-signal voltage gain, Gv. Using voltage division

at the input to the small-signal equivalent circuit
Rin
vi =
vsig
(6)
Rin + Rsig
Substituting this into
Gv
vo
v v
v
= i o = i Av
vsig vsig vi vsig
N
(7)
= Av
and using (1) and (4) gives the overall small-signal voltage
gain of this common drain amplifier to be
v
RG
RL || ro
Gv o =
(4.104),(8)
vsig RG + Rsig RL || ro + 1 g m
Again, notice that if ro RL and RL 1 g m , as well as
RG Rsig , then
Whites, EE 320
Lecture 36
Page 4 of 10
Gv 3 1
(9)
Consequently, this common drain amplifier is often called the

source follower amplifier.
Overall small-signal current gain, Gi. Applying current
division at the output and noting that ig = 0 then
ro
io =
g m vgs
(10)
ro + RL
while at the input
vi 1 + g m ( RL || ro )
ii =
=
vgs
(11)
N
RG ( 3)
RG
Substituting (11) into (10) gives the overall small-signal AC
current gain to be
i
ro
g m RG
Gi o =
(12)
ii ro + RL 1 + g m ( RL || ro )
With a little manipulation, this can be expressed as
g m ( RL || ro ) RG
Gi =
1 + g m ( RL || ro ) RL
(13)
If ro RL and g m RL 1, then
Gi
which likely is quite large.
RG
RL
(14)
Whites, EE 320
Lecture 36
Page 5 of 10
Short-circuit small-signal current gain, Ais. The short circuit

small-signal AC current gain can be easily determined from
(12) with RL = 0 as
Ais Gi R =0 = g m RG
(15)
L
Output resistance, Rout. To determine Rout from the smallsignal circuit above we set vsig = 0 and apply a fictitious AC
voltage source vx at the output as shown:
g m vgs
(Fig. 1)
Notice that the gate terminal has zero voltage because vsig = 0
and isig = 0 .
By definition
Rout
vx
ix
(16)
Whites, EE 320
Lecture 36
Page 6 of 10
We can see that with vx attached, the voltage vgs will not
usually be zero. This means the current in the dependent
current source is also not zero.
In such instances, we would normally need to analyze this
circuit to find the voltage vx in terms of ix, and then apply (16)
to determine the output resistance of this amplifier.
However, in this case both terminals of the dependent current
source are grounded so it makes no contribution to the output
resistance. By inspection, the output resistance is simply
1
Rout = ro ||
(17)
gm
Summary and Comparison with the CE Amplifier

o A non-inverting amplifier.
o Potentially very large input resistance [see (1)].
o Small-signal voltage gain less than one, and potentially
close to one [see (8) and (9)].
o Potentially very large small-signal current gain [see (13)
and (14)].
o Relatively small output resistance [see (19)].
Whites, EE 320
Lecture 36
Page 7 of 10
Similar to the BJT common collector (emitter follower)

amplifier we discussed in Lecture 21, the common drain (source
follower) amplifier finds use in applications that require a unitygain voltage buffering function. That is, in applications where a
voltage signal source has sufficient amplitude, for example, but
it has a large internal resistance while the signal needs to be
supplied to a load with a much smaller resistance.
Other applications of voltage buffering amplifiers are:
The output stage of a multi-stage amplifier chain to provide a
low resistance output.
To separate a filter circuit from a subsequent amplifier circuit
that loads the filter with a varying impedance load, which
will likely adversely affect the filter behavior.
Example N36.1 (based on text exercise 4.35). Use the circuit of

Fig. E4.30 to design a common drain amplifier. Assume Rsig = 1
M, RL = 15 k, and ro = 150 k. Computer Rin, Avo, Av, Gv, Gi,
and Rout both with and without considering ro.
This is the same DC biasing circuit we used in Example N34.1

for the design of a common gate amplifier. Here were going to
use it as the basis for a common drain amplifier.
The DC analysis results are shown in Fig. E4.30:
Whites, EE 320
Lecture 36
Page 8 of 10
(Fig. E4.30)
Using (4.71)
gm =
2 I D 2 0.5 m
=
= 1 mS
VOV 2.5 1.5
Based on this DC biasing, the corresponding common drain

amplifier circuit is:
Notice the addition of the bypass capacitor on the drain terminal

of the MOSFET. This was added so that RD will affect only the
Whites, EE 320
Lecture 36
Page 9 of 10
DC functionality of the circuit. In the AC operation, the drain

terminal will be an AC ground, which fits the analysis presented
in this lecture.
The small-signal equivalent circuit for this amplifier is then:
g m vgs
From (1), Rin = RG = 4.7 M (with and without ro).

From (17), Rout = ro ||
Rout =
1
= 150k ||103 = 0.993 k (w/ ro), or
gm
1
= 1 k (w/o ro).
gm
From (5), Avo =

or Avo = 1
ro
150k
V
=
=
(w/ ro),
0.9993
ro + 1 g m 150k + 1 103
V
V
(w/o ro).
V
Whites, EE 320
Lecture 36
Page 10 of 10
RL || ro
15k ||150k
V
=
=
0.932
RL || ro + 1 g m 15k ||150k + 103
V
RL || ro
15k
V
=
=
(w/o ro).
(w/ ro), or Av =
0.938
RL || ro + 1 g m 15k + 103
V
From (4), Av =
From (8),
RG
RL || ro
4.7M
15k ||150k
Gv =
=
RG + Rsig RL || ro + 1 g m 4.7M + 1M 15k ||150k + 103
RG
RL
V
= 0.768
(w/ ro), or Gv =
RG + Rsig RL + 1 g m
V
4.7M
15k
V
=
=
0.
77
3
(w/o ro).
3
4.7M + 1M 15k + 10
V
From (13),
g m ( RL || ro ) RG
103 (15k ||150k ) 4.7M
A
Gi =
313.3
=
=
1 + g m ( RL || ro ) RL 1 + 103 (15k ||150k ) 15k
A
g m RL RG
103 15k 4.7M
A
(w/ ro), or Gi =
=
=
29
3.8
1 + g m RL RL 1 + 103 15k 15k
A
(w/o ro).
Whites, EE 320
Lecture 37
Page 1 of 10
Lecture 37: CMOS Digital Logic Inverter.

The basic circuit element for digital circuit design is the logic
inverter. This element is used to build logic gates and more
complicated digital circuits.
The basic CMOS logic inverter is shown in Fig. 4.53. Well
assume the body and source terminals are connected together, so
theres no body effect to consider. Well also assume that the
MOSFETs are matched transistors.
(Fig. 4.53)
The operation of this circuit can be summarized as:
When vI is low, QN is off, QP is on vO is high
When vI is high, QN is on, QP is off vO is low
Conceptually, this CMOS circuit is intended to function as
complementary switches shown in Fig. 1.32(a):
Whites, EE 320
Lecture 37
Page 2 of 10
(Fig. 1.32a)
The directions of the arrows indicate the complementary nature
of the two switches: when one is closed the other is open, and
vice versa.
Graphical Analysis of the CMOS Logic Inverter

A more complete analysis of this CMOS logic inverter can be
performed graphically, as shown in Figs. 4.54 and 4.55. Here,
QP is treated as an active load for QN though the converse would
produce identical results. Well consider the two extremes of the
input: vI = 0 (low) and vI = VDD (high).
With QN considered the driving transistor and QP the active load,
then for a graphical solution well be plotting characteristic and
load curves in the iDN-vDSN plane.
For this digital logic inverter circuit in Fig. 4.53, we see that
iDP = iDN .
Whites, EE 320
Lecture 37
Page 3 of 10
The vDS values are different for the two transistors, of course. By
KVL,
(1)
VDD vSDP = vDSN
How we interpret this equation can give us the answers on how
to plot the QP characteristic curve in the iDN-vDSN plane:
The minus sign in (1) tells us to flip the QP characteristic
curve about the vertical axis.
The VDD term tells us to shift this flipped curve VDD units to
the right.
(This is the same process we used for the graphical solution of
the CMOS common source amplifier discussed in Lecture 33.)
Whites, EE 320
Lecture 37
Graphical solution when vI is high:
Page 4 of 10
Whites, EE 320
Lecture 37
Graphical solution when vI is low:
Page 5 of 10
Whites, EE 320
Lecture 37
Page 6 of 10
Summary of the CMOS Digital Logic Inverter

1. The output voltage levels are ~10 mV and ~VDD-10mV, thus
the output signal swing is nearly the maximum possible.
(Gives rise to the so-called noise margins.)
2. The static power dissipation is nearly zero (a fraction of a
W) in both states. The dynamic power dissipation is not zero
as the gates are changing states.
3. Low output resistance in either state: low resistance to ground
in the low output state, and low resistance to VDD in the
high state.
4. Input resistance of the inverter is very large (ideally infinite).
The inverter can drive a very large number of similar inverters
with little loss in signal level.
5. The gate input capacitance is not negligible, so it will take
time to charge up. Low output resistance helps to keep the
time constant = Rout Cin small when driving similar inverters.
Characteristic Curve for the CMOS Logic Inverter

Rather than using a graphical solution, it is fairly straightforward
to numerically construct the characteristic curve vO versus vI.
Whites, EE 320
Lecture 37
Page 7 of 10
To obtain an equation to plot for the inverter characteristic

curve, we will use the equations for the MOSFET current in the
triode and saturation regions of operation.
The iD-vDS characteristic curve for QN is given by
1
W
iDN = kn vI Vtn vO vO2
N
2N
L n vN
2
vDS
vDS
GS
iDN
1 W
= kn vI Vtn
2 L n vN
GS
vO vI Vtn
(4.142),(2)
vO vI Vtn
(4.143),(3)
while the iD-vDS characteristic curve for QP is given by

iDP
= k p VDD vI Vtp

L p
vGS
iDP
1 W
= k p VDD vI Vtp

2 L p
vGS
(VDD vO ) 1 VDD vO

2
vSD
vSD
v v +V
I
tp
O
(4.144),(4)
vO vI + Vtp
(4.145),(5)
For the digital logic inverter circuit, these two currents must be
equal:
iDN = iDP
(6)
To construct the complete characteristic curve for this logic
inverter, we solve (6) for vO using (2) through (5) as vI varies
from 0 to VDD.
In the case of symmetrical MOSFETs in which Vtn = Vtp and
kn (W L )n = k p (W L ) p , the voltage transfer characteristic
curve will also be symmetrical, as shown below in Fig. 4.56.
Whites, EE 320
Lecture 37
Page 8 of 10
Noise Margins
We can observe from this characteristic curve that there is a
range of input values (from 0 to VIL) that produce a high output
Whites, EE 320
Lecture 37
Page 9 of 10
voltage, and a range of input values (from VIH to VDD) that

produce a low output voltage. This is one advantage that digital
circuits have over analog ones.
These ranges of input voltages are called noise margins. In
particular, the noise margin for high input NMH is defined as:
(1.25),(7)
NM H VOH VIH
and the noise margin for low input NML is defined as:
NM L VIL VOL
(1.26),(8)
Referring to Fig. 4.56, the voltages VIH and VIL are defined
where the slope of the characteristic curve is -1. Solving (6) at
these two points, its shown in the text that
1
VIH = ( 5VDD 2Vt )
(4.148),(9)
8
1
and
VIL = ( 3VDD + 2Vt )
(4.149),(10)
8
Using (9) and (10) in (7) and (8) we can determine expressions
for the two noise margins to be
1
NM H = ( 3VDD + 2Vt )
(4.150),(11)
8
1
and
NM L = NM H = ( 3VDD + 2Vt )
(4.151),(12)
8
These two noise margins are equal because we assumed the two
MOSFETs in the inverter circuit to be symmetrical.
Whites, EE 320
Lecture 37
[Add material on propagation delay?]
Page 10 of 10

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EE 320 Electronics I

Laboratory for Applied Electromagnetics and Communications

2009 Keith W. Whites

Lecture 1: Ideal Diode

Linear Circuit Elements

where m is a constant. In other words, f is a linear function if

2009 Keith W. Whites

Here are a couple of examples of linear components in electrical

This is perhaps a bit tricker, but notice that differentiation

The circuit symbol is

which is related to the physical markings on a typical diode as

In stark contrast to resistors, inductors, and capacitors, the diode

We will find this valve behavior very useful in some

If a ground is not shown, one is assumed

When vI > 0 , current will flow into the anode of D and

Conversely, when vI < 0 , the ideal diode is off and there is

Assuming the voltages are 0 V for low signals and 5 V for

Example N1.1 Determine the voltage V and current I in the

This is a nonlinear circuit, so a completely different analysis

Lecture 2: Physical Operation of Diodes.

which is true for operation in the reverse bias region.

Well now take a quick look at the basic semiconductor physics

For T > 0, random thermal vibration provides enough energy for

Donors and Acceptors

At room temperature, thermal ionization breaks some covalent

Through the mechanism of diffusion (random motion due to

With this electron now gone, we have uncovered a

(2) Similarly, the majority carriers in the n-type region

This contact region between the p and n regions now has a

Reverse and Forward Biased Junction

For the reversed biased state of the pn junction, the electric

enough to strip electrons from the covalent bonds of the

When V is large enough so that Ebattery > E, then (i) holes

Lecture 3: DC Analysis of Diode Circuits.

We will assume that the diode is forward biased. Using KVL

Assuming n, IS, and VT are known, we have two equations for

which is a transcendental equation for VD. There is no simple

2009 Keith W. Whites

1. Graphical Analysis. Begin with the diode i-v characteristic

From (1), we can rearrange the equation in terms of I to also

We call this straight line the load line.

2. Simulation packages. SPICE, Agilents Advanced Design

3. Numerical methods. Use Mathematica, Matlab, Mathcad, etc.

4. Iterative analysis. See example 3.4 in the text.

Approximate Diode Circuit Solutions

Constant-Voltage-Drop (CVD) Model

Example N3.1. Determine the current I in the circuit below

Using the CVD model, the equivalent approximate circuit is:

Assuming the diode is forward conducting (i.e., on) with VD =

Piecewise Linear (PWL) Diode Model

Example N3.2. Determine the current I in the circuit below

Assuming the diode is on,, then by KVL:

This is close to the 1.3 mA we computed in the last example

Lecture 4: Small-Signal Diode Model

The analysis of the circuit is then divided into two parts:

2009 Keith W. Whites

The total voltage at any time t is the sum of the DC and AC

where ID is the DC diode current.

(Note that this rd is a fundamentally different quantity than rD

Because we have linearized the operation of the diode (by

The diode specifications are

We use this rd as the equivalent resistance in the small-signal

The AC voltage across the diode is found from voltage division

The corresponding phasor diode voltage is then

In many applications, rD R so that R ( R + rD ) 1. Hence,