Learnings:

The VLSI CAD and optimizations course has introduced us to several

modeling issues in nanometer design and briefed about several optimization
and implementation techniques for the challenges in VLSI design. There are
several topics that amazed me and were fascinating to learn. I have briefed
about some in the section below.
Detailed placement technique Global Swap: Evaluating Optimal
Region
This is a very simple algorithm in terms of computation, but gives maximum
benefit in terms of wire length reduction. This is a greedy algorithm and is
linear in terms of time complexity. For any cell, it tries to identify a good
swap pair, so that after the swap would be in the position that gives the best
wire length when all other cells are fixed and the region is termed as optimal
region. To evaluate it, we find the bounding box for all the nets associated
with the cell (excluding the cell itself) and find the median of the x and y
edges to find the optimal region as shown in the picture below.

Continuous Wire Sizing for a Line

This method proposes to minimize the wire delay to minimum possible value.
Given driver resistance RD, loading capacitance CL and wire length we can
assuming the wire has infinite segments and find function f(x), optimal wire
width at position x to minimize delay. It is interesting to see that the closed
form solution can be obtained as a decaying exponential function given
below.

The2-pi Crosstalk Noise Model

This paper models the victim net as 2-pimodel of 2 RC circuits, one before
the coupling and one after the coupling. The victim driver is modeled by
effective resistance RD. It is interesting to see the problem formulation and
the conclusions arrived with rigorous mathematics.

My experimentation of re-deriving the Vpeak and twidth with ramp, step and
exponential functions gave me gist of the amount of work that has been put
in order to write this article. Also, the analysis performed on the obtained
results is exhaustive and a few among them are quoted below.
1. The noise twidth is monotonic function and is bounded by (tr , tr + tv
ln2).
2. The product of noise peak voltage and width is bounded by (tx , tx ln2)
3. The victim driver sizing effective only if Rs C1< Re CL.
4. It is effective to do wire spacing rather than wire sizing.
The most interesting thing is to prove that the Vittal and Devgan models are
the special cases of 2-pi model.
The aforementioned techniques and models gave me great insight into the
field of VLSI CAD and optimization.