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Ee101 Dac 1
Ee101 Dac 1
Ee101 Dac 1
M. B. Patil
mbpatil@ee.iitb.ac.in
www.ee.iitb.ac.in/~sequel
Department of Electrical Engineering
Indian Institute of Technology Bombay
Introduction
Introduction
Introduction
Introduction
Introduction
Introduction
DAC
VR
DN1
N-bit
digital
input
VA
D2
D1
D0
ground
analog
output
DAC
VR
DN1
N-bit
digital
input
VA
analog
output
D2
D1
D0
ground
* For a 4-bit
DAC, with input S3 S2 S1 S0 , the output voltage
is
VA = K (S3 23 ) + (S2 22 ) + (S1 21 ) + (S0 20 ) .
PN1
Sk 2k .
In general, VA = K
0
DAC
VA
VR
maximum
output
voltage
DN1
VA
analog
output
D2
resolution
D1
D0
* For a 4-bit
DAC, with input S3 S2 S1 S0 , the output voltage
is
VA = K (S3 23 ) + (S2 22 ) + (S1 21 ) + (S0 20 ) .
PN1
Sk 2k .
In general, VA = K
0
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
ground
0000
N-bit
digital
input
digital
input
DAC
VA
VR
maximum
output
voltage
DN1
VA
analog
output
D2
resolution
D1
D0
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
ground
0000
N-bit
digital
input
digital
input
* For a 4-bit
DAC, with input S3 S2 S1 S0 , the output voltage
is
VA = K (S3 23 ) + (S2 22 ) + (S1 21 ) + (S0 20 ) .
PN1
Sk 2k .
In general, VA = K
0
* K is proportional to the reference voltage VR . Its value depends on how the
DAC is implemented.
M. B. Patil, IIT Bombay
VR
I3
A3
S3 VR
R3 = R
A2
I2
A1
R2 = 2 R
I1
A0
R1 = 4 R
I0
R0 = 8 R
S2 VR
Rf
S1 VR
I
S0 VR
VA
I3
A3
R3 = R
A2
I2
A1
R2 = 2 R
I1
A0
R1 = 4 R
I0
R0 = 8 R
Rf
I
VA
VR
I3
A3
S3 VR
R3 = R
A2
I2
A1
R2 = 2 R
I1
A0
R1 = 4 R
I0
R0 = 8 R
S2 VR
Rf
S1 VR
I
S0 VR
VA
I3
A3
R3 = R
A2
I2
A1
R2 = 2 R
I1
A0
R1 = 4 R
I0
Rf
I
R0 = 8 R
VA
VR
I3
A3
S3 VR
R3 = R
A2
I2
A1
R2 = 2 R
I1
A0
R1 = 4 R
I0
R0 = 8 R
S2 VR
Rf
S1 VR
I
S0 VR
VA
I3
A3
R3 = R
A2
I2
A1
R2 = 2 R
I1
A0
R1 = 4 R
I0
Rf
I
R0 = 8 R
VA
VR
I3
A3
S3 VR
R3 = R
A2
I2
A1
R2 = 2 R
I1
A0
R1 = 4 R
I0
R0 = 8 R
S2 VR
Rf
S1 VR
I
S0 VR
VA
I3
A3
R3 = R
A2
I2
A1
R2 = 2 R
I1
A0
R1 = 4 R
I0
Rf
I
R0 = 8 R
VA
VR
I3
A3
S3 VR
R3 = R
A2
I2
A1
R2 = 2 R
I1
A0
R1 = 4 R
I0
S2 VR
Rf
S1 VR
R0 = 8 R
S0 VR
VA
I3
A3
R3 = R
A2
I2
A1
R2 = 2 R
I1
A0
R1 = 4 R
I0
Rf
I
R0 = 8 R
VA
N1
X
VR
k
Sk 2 (N = 4 here).
2N1 R 0
VR
I3
A3
S3 VR
R3 = R
A2
I2
A1
R2 = 2 R
I1
A0
R1 = 4 R
I0
S2 VR
Rf
S1 VR
R0 = 8 R
S0 VR
VA
I3
A3
R3 = R
A2
I2
A1
R2 = 2 R
I1
A0
R1 = 4 R
I0
Rf
I
R0 = 8 R
VA
N1
X
VR
k
Sk 2 (N = 4 here).
2N1 R 0
Rf
2N1 R
N1
X
0
Sk 2 .
M. B. Patil, IIT Bombay
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
R0 = 27 R
Rf
I
VA
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
R0 = 27 R
Rf
I
VA
* Consider an 8-bit DAC with VR = 5 V. What is the smallest value of R which will limit the
current drawn from the supply (VR ) to 10 mA?
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
R0 = 27 R
Rf
I
VA
* Consider an 8-bit DAC with VR = 5 V. What is the smallest value of R which will limit the
current drawn from the supply (VR ) to 10 mA?
Maximum current is drawn from VR when the input is 1111 1111.
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
R0 = 27 R
Rf
I
VA
* Consider an 8-bit DAC with VR = 5 V. What is the smallest value of R which will limit the
current drawn from the supply (VR ) to 10 mA?
Maximum current is drawn from VR when the input is 1111 1111.
All nodes A0 to A7 get connected to VR .
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
R0 = 27 R
Rf
I
VA
* Consider an 8-bit DAC with VR = 5 V. What is the smallest value of R which will limit the
current drawn from the supply (VR ) to 10 mA?
Maximum current is drawn from VR when the input is 1111 1111.
All nodes A0 to A7 get connected to VR .
VR
VR
VR
1 VR 0
1
7
10 mA =
+
+ + 7 = 7
2 + 2 + + 2
R
2R
2 R
2 R
1 VR 8
255 VR
= 7
2 1 =
2 R
128 R
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
R0 = 27 R
Rf
I
VA
* Consider an 8-bit DAC with VR = 5 V. What is the smallest value of R which will limit the
current drawn from the supply (VR ) to 10 mA?
Maximum current is drawn from VR when the input is 1111 1111.
All nodes A0 to A7 get connected to VR .
VR
VR
VR
1 VR 0
1
7
10 mA =
+
+ + 7 = 7
2 + 2 + + 2
R
2R
2 R
2 R
1 VR 8
255 VR
= 7
2 1 =
2 R
128 R
255
5V
Rmin =
= 996 .
10 mA
128
M. B. Patil, IIT Bombay
VR
I7
A7
R7 = R
A1
I1
Rf
A0
R1 = 2 R
I0
R0 = 2 R
VA
VR
I7
A7
R7 = R
A1
I1
Rf
A0
R1 = 2 R
I0
R0 = 2 R
VA
* If Rf = R, what is the resolution (i.e., VA corresponding to the input LSB changing from 0
to 1 with other input bits constant)?
VR
I7
A7
R7 = R
A1
I1
Rf
A0
R1 = 2 R
I0
R0 = 2 R
VA
* If Rf = R, what is the resolution (i.e., VA corresponding to the input LSB changing from 0
to 1 with other input bits constant)?
h
i
Rf
7
1
0
VA = VR N1
S7 2 + + S1 2 + S0 2
2
R
VR
I7
A7
R7 = R
A1
I1
Rf
A0
R1 = 2 R
I0
R0 = 2 R
VA
* If Rf = R, what is the resolution (i.e., VA corresponding to the input LSB changing from 0
to 1 with other input bits constant)?
h
i
Rf
7
1
0
VA = VR N1
S7 2 + + S1 2 + S0 2
2
R
VR Rf
5V
5
VA = N1
= 81 1 =
= 0.0391 V.
2
R
2
128
VR
I7
A7
R7 = R
A1
I1
Rf
A0
R1 = 2 R
I0
R0 = 27 R
I
VA
VR
I7
A7
R7 = R
A1
I1
Rf
A0
R1 = 2 R
I0
R0 = 27 R
VA
VR
I7
A7
R7 = R
A1
I1
Rf
A0
R1 = 2 R
I0
R0 = 27 R
VA
VR
I7
A7
R7 = R
A1
I1
Rf
A0
R1 = 2 R
I0
R0 = 27 R
I
VA
VR
I7
A7
R7 = R
A1
I1
Rf
A0
R1 = 2 R
I0
R0 = 27 R
I
VA
VR
I7
A7
R7 = R
A1
I1
Rf
A0
R1 = 2 R
I0
R0 = 27 R
I
VA
VR
I7
A7
R7 = R
A1
I1
Rf
A0
R1 = 2 R
I0
R0 = 27 R
VA
VR
I7
A7
R7 = R
A1
I1
Rf
A0
R1 = 2 R
I0
R0 = 27 R
VA
VR
I7
A7
R7 = R
A1
I1
Rf
A0
R1 = 2 R
I0
R0 = 27 R
I
VA
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
Rf
I
R0 = 2 R
VA
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
Rf
I
R0 = 2 R
VA
* If the resistors are specified to have a tolerance of 1 %, what is the range of |VA |
corresponding to input 1111 1111?
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
Rf
I
R0 = 2 R
VA
* If the resistors are specified to have a tolerance of 1 %, what is the range of |VA |
corresponding to input 1111 1111?
|VA | is maximum when (a) currents I0 , I1 , etc. assume their maximum values, with
Rk = Rk0 (1 0.01) and (b) Rf is maximum, Rf = Rf0 (1 + 0.01).
(The superscript 0 denotes nominal value.)
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
Rf
I
R0 = 2 R
VA
* If the resistors are specified to have a tolerance of 1 %, what is the range of |VA |
corresponding to input 1111 1111?
|VA | is maximum when (a) currents I0 , I1 , etc. assume their maximum values, with
Rk = Rk0 (1 0.01) and (b) Rf is maximum, Rf = Rf0 (1 + 0.01).
(The superscript 0 denotes nominal
value.)
Rf max
255
1.01
255
max
|VA |11111111 = VR
=5
= 10.162 V.
128
R
128
0.99
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
Rf
I
R0 = 2 R
VA
* If the resistors are specified to have a tolerance of 1 %, what is the range of |VA |
corresponding to input 1111 1111?
|VA | is maximum when (a) currents I0 , I1 , etc. assume their maximum values, with
Rk = Rk0 (1 0.01) and (b) Rf is maximum, Rf = Rf0 (1 + 0.01).
(The superscript 0 denotes nominal
value.)
Rf max
255
1.01
255
max
|VA |11111111 = VR
=5
= 10.162 V.
128
R
128
0.99
255
0.99
Similarly, |VA |min
= 9.764 V.
11111111 = 5
128
1.01
M. B. Patil, IIT Bombay
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
R0 = 27 R
Rf
I
VA
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
R0 = 27 R
Rf
I
VA
* VA for input 1111 1111 = 10.162 9.764 0.4 V which is larger than the resolution
(0.039 V) of the DAC. This situation is not acceptable.
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
R0 = 27 R
Rf
I
VA
* VA for input 1111 1111 = 10.162 9.764 0.4 V which is larger than the resolution
(0.039 V) of the DAC. This situation is not acceptable.
* The output voltage variation can be reduced by using resistors with a smaller tolerance.
However, it is difficult to fabricate an IC with widely varying resistance values (from R to
2N1 R) and each with a small enough tolerance.
VR
I7
A7
R7 = R
A1
A0
I1
R1 = 26 R
I0
R0 = 27 R
Rf
I
VA
* VA for input 1111 1111 = 10.162 9.764 0.4 V which is larger than the resolution
(0.039 V) of the DAC. This situation is not acceptable.
* The output voltage variation can be reduced by using resistors with a smaller tolerance.
However, it is difficult to fabricate an IC with widely varying resistance values (from R to
2N1 R) and each with a small enough tolerance.
use R 2R ladder network instead.
R
2R
2R
A0
LSB
R
2R
A1
R
2R
A2
2R
A3
MSB
R
2R
2R
R
2R
A0
LSB
R
2R
A1
2R
A2
A3
MSB
2R
2R
2R
2R
S 0 VR
S1 VR
S2 VR
S3 VR
R
2R
2R
R
2R
R
2R
2R
R
2R
2R
R
2R
R
2R
2R
R
2R
2R
R
2R
R
R
R
2R
R
2R
2R
R
2R
2R
R
2R
2R
R
2R
R
R
R
2R
R
2R
2R
R
2R
2R
R
2R
2R
R
2R
R
R
R
2R
R
2R
R
2R
R
R
2R
2R
R
2R
2R
R
2R
2R
R
2R
R
R
R
2R
R
2R
R
2R
R
R
2R
2R
R
2R
2R
R
2R
2R
R
2R
R
R
R
2R
R
2R
R
2R
R
R
2R
2R
R
2R
2R
R
R
2R
R
2R
2R
R
2R
R
R
R
2R
R
2R
R
2R
R
R
2R
2R
R
2R
2R
R
R
2R
R
2R
2R
R
2R
R
R
R
2R
R
2R
R
2R
R
R
2R
2R
R
2R
2R
R
R
2R
RTh = R
2R
VR
R
2R
R
2R
2R
2R
VR
R
2R
R
2R
2R
2R
R
2R
R
2R
2R
VR
R
R
VR
2
R
2R
R
2R
2R
2R
R
2R
R
2R
2R
VR
R
R
VR
2
R
2R
R
2R
2R
2R
R
2R
R
2R
2R
VR
R
R
R
2R
R
2R
2R
VR
2
R
R
VR
4
R
2R
2R
2R
R
2R
R
2R
2R
VR
R
R
R
2R
R
2R
2R
VR
2
R
R
VR
4
R
2R
2R
2R
R
2R
R
2R
2R
VR
R
R
R
2R
R
2R
2R
VR
2
R
R
R
2R
2R
VR
4
R
R
VR
8
2R
2R
R
2R
R
2R
2R
VR
R
R
R
2R
R
2R
2R
VR
2
R
R
R
2R
2R
VR
4
R
R
VR
8
2R
2R
R
2R
R
2R
2R
VR
R
R
R
2R
R
2R
2R
VR
2
R
R
R
2R
2R
VR
4
R
R
VR
8
2R
VTh =
VR
16
2R
R
2R
VR
R
2R
2R
2R
R
2R
VR
R
2R
2R
2R
R
2R
2R
2R
VR
R
2R
2R
VR
R
2R
2R
2R
R
2R
2R
2R
VR
R
2R
2R
VR
R
2R
2R
2R
R
2R
2R
2R
VR
R
2R
2R
R
2R
2R
VR
R
R
VR
2
R
2R
2R
2R
R
2R
2R
2R
VR
R
2R
2R
R
2R
2R
VR
R
R
VR
2
R
2R
2R
2R
R
2R
2R
2R
VR
R
2R
2R
R
2R
2R
VR
R
R
R
2R
2R
VR
2
R
R
VR
4
2R
2R
R
2R
2R
2R
VR
R
2R
2R
R
2R
2R
VR
R
R
R
2R
2R
VR
2
R
R
VR
4
2R
2R
R
2R
2R
2R
VR
R
2R
2R
R
2R
2R
VR
R
R
R
2R
2R
VR
2
R
R
VR
4
2R
VTh =
VR
8
2R
R
2R
R
2R
VR
2R
2R
R
2R
R
2R
VR
2R
2R
2R
2R
2R
VR
R
2R
2R
VR
2R
2R
2R
2R
2R
VR
R
2R
2R
VR
2R
2R
2R
2R
2R
VR
R
2R
2R
2R
VR
R
R
VR
2
2R
2R
2R
2R
2R
VR
R
2R
2R
2R
VR
R
R
VR
2
2R
2R
2R
2R
2R
VR
R
2R
2R
2R
VR
R
R
VR
2
2R
VTh =
VR
4
2R
R
2R
R
2R
2R
VR
2R
R
2R
R
2R
2R
VR
2R
R
2R
R
2R
2R
VR
2R
2R
VR
2R
R
2R
R
2R
2R
VR
2R
2R
VTh =
VR
VR
2
R
2R
2R
2R
2R
2R
S0 VR
S1 VR
S2 VR
S3 VR
RTh
VTh
R
2R
2R
2R
2R
2R
S0 VR
S1 VR
S2 VR
S3 VR
RTh
VTh
* RTh = R .
R
2R
2R
2R
2R
2R
S0 VR
S1 VR
S2 VR
S3 VR
RTh
VTh
* RTh = R .
(S0)
* VTh = VTh
(S1)
(S2)
(S3)
R
2R
2R
2R
2R
2R
S0 VR
S1 VR
S2 VR
S3 VR
RTh
VTh
* RTh = R .
(S0)
* VTh = VTh
(S1)
+ VTh
(S2)
+ VTh
(S3)
+ VTh
i
VR h
0
1
2
3
S0 2 + S1 2 + S2 2 + S3 2 .
=
16
* We can use the R-2R ladder network and an Op Amp
to make up a DAC next slide.
Rf
Rf
R
2R
2R
S 0 VR
R
2R
S 1 VR
RTh
R
2R
S 2 VR
2R
Vo
VTh
Vo
S 3 VR
Rf
Rf
R
2R
2R
S 0 VR
* Vo =
R
2R
S 1 VR
RTh
R
2R
S 2 VR
2R
Vo
VTh
Vo
S 3 VR
i
Rf
Rf VR h
0
1
2
3
VTh =
S0 2 + S1 2 + S2 2 + S3 2 .
RTh
RTh 16
Rf
Rf
R
2R
2R
S 0 VR
* Vo =
R
2R
S 1 VR
RTh
R
2R
S 2 VR
2R
Vo
VTh
Vo
S 3 VR
i
Rf
Rf VR h
0
1
2
3
VTh =
S0 2 + S1 2 + S2 2 + S3 2 .
RTh
RTh 16
N1
Rf
Rf VR X
k
Sk 2 .
VTh =
RTh
RTh 2N 0
Rf
Rf
R
2R
2R
S 0 VR
* Vo =
R
2R
S 1 VR
RTh
R
2R
S 2 VR
2R
Vo
Vo
VTh
S 3 VR
i
Rf
Rf VR h
0
1
2
3
VTh =
S0 2 + S1 2 + S2 2 + S3 2 .
RTh
RTh 16
N1
Rf
Rf VR X
k
Sk 2 .
VTh =
RTh
RTh 2N 0
* 6- to 20-bit DACs based on the R-2R ladder network are commercially available in
monolithic form (single chip).
Rf
Rf
R
2R
2R
S 0 VR
* Vo =
R
2R
S 1 VR
RTh
R
2R
S 2 VR
2R
Vo
Vo
VTh
S 3 VR
i
Rf
Rf VR h
0
1
2
3
VTh =
S0 2 + S1 2 + S2 2 + S3 2 .
RTh
RTh 16
N1
Rf
Rf VR X
k
Sk 2 .
VTh =
RTh
RTh 2N 0
* 6- to 20-bit DACs based on the R-2R ladder network are commercially available in
monolithic form (single chip).
* Bipolar, CMOS, or BiCMOS technology is used for these DACs.
Rf
r
8R
S0 VR
4R
S 1 VR
2R
S2 VR
R
S 3 VR
8R
S4 VR
4R
S5 VR
2R
S6 VR
Vo
S7 VR
Rf
r
8R
S0 VR
4R
S 1 VR
2R
S2 VR
R
S 3 VR
8R
S4 VR
4R
S5 VR
2R
S6 VR
Vo
S7 VR
* Find the valur of r for the circuit to work as a regular (i.e., binary to analog) DAC.
Rf
r
8R
S0 VR
4R
S 1 VR
2R
S2 VR
R
S 3 VR
8R
S4 VR
4R
S5 VR
2R
S6 VR
Vo
S7 VR
* Find the valur of r for the circuit to work as a regular (i.e., binary to analog) DAC.
* Find the valur of r for the circuit to work as a BCD to analog DAC.
VR
VA
DN1
final
value
N-bit
digital
input
VA
D2
D1
analog
output
initial
value
D0
ground
VR
VA
DN1
final
value
N-bit
digital
input
VA
D2
D1
analog
output
initial
value
D0
ground
* When there is a change in the input binary number, the output VA takes a finite time to
settle to the new value.
VR
VA
DN1
final
value
N-bit
digital
input
VA
D2
D1
analog
output
initial
value
D0
ground
* When there is a change in the input binary number, the output VA takes a finite time to
settle to the new value.
* The finite settling time arises because of stray capacitances and switching delays of the
semiconductor devices used within the DAC chip.
VR
VA
DN1
final
value
N-bit
digital
input
VA
analog
output
D2
D1
initial
value
D0
ground
* When there is a change in the input binary number, the output VA takes a finite time to
settle to the new value.
* The finite settling time arises because of stray capacitances and switching delays of the
semiconductor devices used within the DAC chip.
* Example: 500 ns to 0.2 % of full scale.
ADC: introduction
Vmax
V7R
VR
111
110
V6R
101
D2
analog
input
D1
VA
digital
output
VA
V5R
100
V4R
011
V3R
D0
010
V2R
ground
3bit ADC
001
V1R
0
000
ADC: introduction
Vmax
V7R
VR
111
110
V6R
101
D2
analog
input
D1
VA
digital
output
VA
V5R
100
V4R
011
V3R
D0
010
V2R
ground
3bit ADC
001
V1R
0
000
* If the input VA is in the range VRk < VA < VRk+1 , the output is the binary
number corresponding to the integer k. For example, for VA = VA0 , the output is
100.
ADC: introduction
Vmax
V7R
VR
111
110
V6R
101
D2
analog
input
D1
VA
digital
output
VA
V5R
100
V4R
011
V3R
D0
010
V2R
ground
3bit ADC
001
V1R
0
000
* If the input VA is in the range VRk < VA < VRk+1 , the output is the binary
number corresponding to the integer k. For example, for VA = VA0 , the output is
100.
* We may think of each voltage interval (corresponding to 000, 001, etc.) as a
bin. In the above example, the input voltage VA0 falls in the 100 bin; therefore,
the output of the ADC would be 100.
ADC: introduction
Vmax
V7R
VR
111
110
V6R
101
D2
analog
input
D1
VA
digital
output
VA
V5R
100
V4R
011
V3R
D0
010
V2R
ground
3bit ADC
001
V1R
0
000
* If the input VA is in the range VRk < VA < VRk+1 , the output is the binary
number corresponding to the integer k. For example, for VA = VA0 , the output is
100.
* We may think of each voltage interval (corresponding to 000, 001, etc.) as a
bin. In the above example, the input voltage VA0 falls in the 100 bin; therefore,
the output of the ADC would be 100.
* Note that, for an N-bit ADC, there would be 2N bins.
M. B. Patil, IIT Bombay
ADC: introduction
Vmax
V7R
VR
111
110
V6R
101
D2
analog
input
D1
VA
digital
output
VA
V5R
100
V4R
011
V3R
D0
010
V2R
ground
3bit ADC
001
V1R
0
000
ADC: introduction
Vmax
V7R
VR
111
110
V6R
101
D2
analog
input
D1
VA
digital
output
VA
V5R
100
V4R
011
V3R
D0
010
V2R
ground
3bit ADC
001
V1R
0
000
ADC: introduction
Vmax
V7R
VR
111
110
V6R
101
D2
analog
input
D1
VA
digital
output
VA
V5R
100
V4R
011
V3R
D0
010
V2R
ground
3bit ADC
001
V1R
0
000
ADC: introduction
Vmax
V7R
VR
111
110
V6R
101
D2
analog
input
D1
VA
digital
output
VA
V5R
100
V4R
011
V3R
D0
010
V2R
ground
3bit ADC
001
V1R
0
000
ADC: introduction
Vmax
V7R
VR
111
110
V6R
101
D2
analog
input
D1
VA
digital
output
VA
V5R
100
V4R
011
V3R
D0
010
V2R
ground
3bit ADC
001
V1R
0
000
ADC: introduction
Vmax
V7R
VR
111
110
V6R
101
D2
analog
input
D1
VA
digital
output
VA
V5R
100
V4R
011
V3R
D0
010
V2R
ground
3bit ADC
001
V1R
0
000
VA
Vmax
V7R
111
110
VR
V6R
R
101
D2
analog
input
D1
VA
VA
digital
output
V5R
100
V4R
D2
R
LOGIC
011
V3R
D0
010
D1
D0
V2R
001
ground
3bit ADC
V1R
0
000
R
R
2
M. B. Patil, IIT Bombay
VA
C6
C5
C4
C3
D2
C2
C1
C0
R
2
LOGIC
D1
D0
VA
C6
C5
C4
C3
D2
C2
C1
C0
LOGIC
D1
D0
R
2
* Practical difficulty: As the input changes, the comparator outputs (C0 , C1 , etc.) may not
settle to their new values at the same time.
ADC output will depend on when we sample it.
VA
C6
C5
C4
C3
D2
C2
C1
C0
LOGIC
D1
D0
R
2
* Practical difficulty: As the input changes, the comparator outputs (C0 , C1 , etc.) may not
settle to their new values at the same time.
ADC output will depend on when we sample it.
* Add D flip-flops. Allow sifficient time (between the change in VA and the active clock edge)
so that the comprator outputs have already settled to their new values before they get
latched in.
VR
R
2
VA
C6
R
C5
R
C4
D2
R
R
R
2
C3
C2
LOGIC
VA
C6
C5
C4
C3
D1
D0
R
C1
R
C0
R
2
C2
C1
C0
Q6
Q5
Q4
D2
D
Q3
Q2
LOGIC
D1
D0
Q1
Q0
Clock
* Practical difficulty: As the input changes, the comparator outputs (C0 , C1 , etc.) may not
settle to their new values at the same time.
ADC output will depend on when we sample it.
* Add D flip-flops. Allow sifficient time (between the change in VA and the active clock edge)
so that the comprator outputs have already settled to their new values before they get
latched in.
M. B. Patil, IIT Bombay
* In the parallel (flash) ADC, the conversion gets done in parallel, since all
comparators operate on the same input voltage.
* In the parallel (flash) ADC, the conversion gets done in parallel, since all
comparators operate on the same input voltage.
* Conversion time is governed only by the comparator response time fast
conversion (hence the name flash converter).
* In the parallel (flash) ADC, the conversion gets done in parallel, since all
comparators operate on the same input voltage.
* Conversion time is governed only by the comparator response time fast
conversion (hence the name flash converter).
* Flash ADCs to handle 500 million analog samples per second are commercially
available.
* In the parallel (flash) ADC, the conversion gets done in parallel, since all
comparators operate on the same input voltage.
* Conversion time is governed only by the comparator response time fast
conversion (hence the name flash converter).
* Flash ADCs to handle 500 million analog samples per second are commercially
available.
* 2N comparators are required for N-bit ADC generally limited to 8 bits.
S
C Vs to ADC
Va
t
Va
Vs
clock
buffer
S
Va
buffer
Vs
Tc
t
S
C Vs to ADC
Va
t
Va
Vs
clock
buffer
S
Va
buffer
Vs
Tc
* An ADC typically operates on a sampled input signal (Vs (t) in the figure) which is
derived from the continuously varying input signal (Va (t) in the figure) with a
sample-and-hold (S/H) circuit.
S
C Vs to ADC
Va
t
Va
Vs
clock
buffer
S
Va
buffer
Vs
Tc
t
* An ADC typically operates on a sampled input signal (Vs (t) in the figure) which is
derived from the continuously varying input signal (Va (t) in the figure) with a
sample-and-hold (S/H) circuit.
* The S/H circuit samples the input signal Va (t) at uniform intervals of duration Tc , the
clock period.
S
C Vs to ADC
Va
t
Va
Vs
clock
buffer
S
Va
buffer
Vs
Tc
t
* An ADC typically operates on a sampled input signal (Vs (t) in the figure) which is
derived from the continuously varying input signal (Va (t) in the figure) with a
sample-and-hold (S/H) circuit.
* The S/H circuit samples the input signal Va (t) at uniform intervals of duration Tc , the
clock period.
* When the clock goes high, switch S (e.g., a FET or a CMOS pass gate) is closed, and the
capacitor C gets charged to the signal voltage at that time. When the clock goes low,
switch S is turned off, and C holds the voltage constant, as desired.
S
C Vs to ADC
Va
t
Va
Vs
clock
buffer
S
Va
buffer
Vs
Tc
t
* An ADC typically operates on a sampled input signal (Vs (t) in the figure) which is
derived from the continuously varying input signal (Va (t) in the figure) with a
sample-and-hold (S/H) circuit.
* The S/H circuit samples the input signal Va (t) at uniform intervals of duration Tc , the
clock period.
* When the clock goes high, switch S (e.g., a FET or a CMOS pass gate) is closed, and the
capacitor C gets charged to the signal voltage at that time. When the clock goes low,
switch S is turned off, and C holds the voltage constant, as desired.
* Op Amp buffers can be used to minimise loading effects.
M. B. Patil, IIT Bombay
4bit DAC
VDAC
o
VA
Comparator
4bit DAC
VDAC
o
VA
Comparator
4bit DAC
VDAC
o
VA
Comparator
4bit DAC
VDAC
o
VA
Comparator
4bit DAC
VDAC
o
VA
Comparator
4bit DAC
VDAC
o
VA
Comparator
4bit DAC
VDAC
o
VA
Comparator
24 k
D4 D3 D2 D1 D0
23 k
VA
22 k
20 k
VR
5bit DAC
16 k
VDAC
o
VA
(Note: k VR )
20 k
10 k
D4
D3
D2
D1
D0
=1
=0
=0
=0
=0
D4
D3
D2
D1
D0
C=1
=1
=1
=0
=0
=0
D4
D3
D2
D1
D0
D4
D3
D2
D1
D0
C=1
C=0
reset D3
=1
=0
=1
=0
=0
=1
=0
=1
=1
=0
D4
D3
D2
D1
D0
C=1
=1
=0
=1
=1
=1
C=0
reset D0
step
24 k
D4 D3 D2 D1 D0
23 k
VA
22 k
20 k
VR
5bit DAC
16 k
VDAC
o
VA
20 k
10 k
(Note: k VR )
D4
D3
D2
D1
D0
=1
=0
=0
=0
=0
D4
D3
D2
D1
D0
C=1
D4
D3
D2
D1
D0
=1
=0
=1
=0
=0
D4
D3
D2
D1
D0
C=1
C=0
reset D3
1
th
=1
=1
=0
=0
=0
=1
=0
=1
=1
=0
D4
D3
D2
D1
D0
C=1
=1
=0
=1
=1
=1
C=0
reset D0
step
24 k
D4 D3 D2 D1 D0
23 k
VA
22 k
20 k
VR
5bit DAC
16 k
VDAC
o
VA
20 k
10 k
(Note: k VR )
D4
D3
D2
D1
D0
=1
=0
=0
=0
=0
D4
D3
D2
D1
D0
C=1
=1
=1
=0
=0
=0
D4
D3
D2
D1
D0
D4
D3
D2
D1
D0
C=1
C=0
reset D3
=1
=0
=1
=0
=0
=1
=0
=1
=1
=0
D4
D3
D2
D1
D0
C=1
=1
=0
=1
=1
=1
C=0
reset D0
step
th
* At the end of the 5 step, we know that the input voltage corresponds to 10110.
* For the digital representation to be accurate up to 12 LSB, V corresponding to
added to VA (see [Taub]).
1
2
LSB is
VA
S/H
Control
logic
VDAC
o
Nbit SAR
Successive
Approximation
Register
Comparator
digital
output
VR
Nbit DAC
VA
S/H
Control
logic
VDAC
o
Nbit SAR
Successive
Approximation
Register
Comparator
digital
output
VR
Nbit DAC
* Each step (setting SAR bits, comparison of VA and VoDAC ) is performed in one clock cycle
conversion time is N cycles, irrespective of the input voltage value VA .
VA
S/H
Control
logic
VDAC
o
Nbit SAR
Successive
Approximation
Register
Comparator
digital
output
VR
Nbit DAC
* Each step (setting SAR bits, comparison of VA and VoDAC ) is performed in one clock cycle
conversion time is N cycles, irrespective of the input voltage value VA .
* S. A. ADCs with built-in or external S/H (sample-and-hold) are available for 8- to 16-bit
resolution and conversion times of a few sec to tens of sec.
VA
S/H
Control
logic
VDAC
o
Nbit SAR
Successive
Approximation
Register
Comparator
digital
output
VR
Nbit DAC
* Each step (setting SAR bits, comparison of VA and VoDAC ) is performed in one clock cycle
conversion time is N cycles, irrespective of the input voltage value VA .
* S. A. ADCs with built-in or external S/H (sample-and-hold) are available for 8- to 16-bit
resolution and conversion times of a few sec to tens of sec.
* Useful for medium-speed applications such as speech transmission with PCM.
Counting ADC
start
conversion
Nbit Counter
reset
VDAC
o
clock
digital
output
VR
VA
clock
Nbit DAC
Tc
Comparator
VDAC
o
VA
S/H
C
Tc
Counting ADC
start
conversion
Nbit Counter
reset
VDAC
o
clock
digital
output
VR
VA
clock
Nbit DAC
Tc
Comparator
VDAC
o
VA
S/H
C
Tc
* The start conversion signal clears the counter; counting begins, and VoDAC increases with
each clock cycle.
Counting ADC
start
conversion
Nbit Counter
reset
VDAC
o
clock
digital
output
VR
VA
clock
Nbit DAC
Tc
Comparator
VDAC
o
VA
S/H
C
Tc
* The start conversion signal clears the counter; counting begins, and VoDAC increases with
each clock cycle.
* When VoDAC exceeds VA , C becomes 0, and counting stops.
Counting ADC
start
conversion
Nbit Counter
reset
VDAC
o
clock
digital
output
VR
VA
clock
Nbit DAC
Tc
Comparator
VDAC
o
VA
S/H
C
Tc
* The start conversion signal clears the counter; counting begins, and VoDAC increases with
each clock cycle.
* When VoDAC exceeds VA , C becomes 0, and counting stops.
* Simple scheme, but (a) conversion time depends on VA , (b) slow (takes 2N clock cycles in
the worst case) tracking ADC (next slide)
Tracking ADC
Up/Down
clock
VDAC
o
Nbit Counter
VA
Tc
digital
output
VR
Nbit DAC
Comparator
VA
S/H
C
Tc
VDAC
o
Tracking ADC
Up/Down
clock
VDAC
o
Nbit Counter
VA
Tc
digital
output
VR
Nbit DAC
Comparator
VA
S/H
C
Tc
VDAC
o
Tracking ADC
Up/Down
clock
VDAC
o
Nbit Counter
VA
Tc
digital
output
VR
Nbit DAC
Comparator
VA
S/H
C
Tc
VDAC
o
Tracking ADC
Up/Down
clock
VDAC
o
Nbit Counter
VA
Tc
digital
output
VR
Nbit DAC
Comparator
VA
S/H
C
Tc
VDAC
o
Dual-slope ADC
S
0
T2
t
VA
VR
T1
Vi
1
Vo =
RC
Vi dt
slope =
V1
slope =
VR
RC
VA
RC
Dual-slope ADC
S
0
T2
t
VA
VR
T1
Vi
1
Vo =
RC
Vi dt
slope =
V1
slope =
VR
RC
VA
RC
Dual-slope ADC
S
0
T2
t
VA
VR
T1
Vi
1
Vo =
RC
Vi dt
slope =
V1
slope =
VR
RC
VA
RC
Dual-slope ADC
S
0
T2
t
VA
VR
T1
Vi
1
Vo =
RC
Vi dt
slope =
V1
slope =
VR
RC
VA
RC
Dual-slope ADC
S
0
T2
t
VA
VR
T1
Vi
1
Vo =
RC
Vi dt
slope =
V1
slope =
VR
RC
VA
RC
Dual-slope ADC
S
0
T2
t
VA
VR
T1
Vi
1
Vo =
RC
Vi dt
slope =
V1
slope =
VR
RC
VA
RC
Dual-slope ADC
S
0
T2
t
VA
VR
T1
Vi
1
Vo =
RC
Vi dt
slope =
V1
slope =
VR
RC
VA
RC
* In the dual-slope ADC, a counter output which is proportional to T2 provides the desired
digital output.
Dual-slope ADC
reset
SPDT
VA
VR
comparator
T1 = 2N Tc
T2
t
Vo
integrator
slope =
Nbit Counter
overflow
slope =
V1
VR
RC
VA
RC
clock
clock
digital output
Tc
Dual-slope ADC
reset
SPDT
VA
VR
comparator
T1 = 2N Tc
T2
t
Vo
integrator
slope =
Nbit Counter
overflow
slope =
V1
VR
RC
VA
RC
clock
clock
digital output
Tc
Dual-slope ADC
reset
SPDT
VA
VR
comparator
T1 = 2N Tc
T2
t
Vo
integrator
slope =
Nbit Counter
overflow
slope =
V1
VR
RC
VA
RC
clock
clock
digital output
Tc
* Counter counts up to 2N at which point the overflow flag becomes 1, and SPDT switches to
position B T1 = 2N Tc where Tc is the clock period.
Dual-slope ADC
reset
SPDT
VA
VR
comparator
T1 = 2N Tc
T2
t
Vo
integrator
slope =
Nbit Counter
overflow
slope =
V1
VR
RC
VA
RC
clock
clock
digital output
Tc
* Counter counts up to 2N at which point the overflow flag becomes 1, and SPDT switches to
position B T1 = 2N Tc where Tc is the clock period.
* The counter starts counting again from 000 0, and stops counting when Vo crosses 0 V.
The counter output gives T2 in binary format.
References