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Fault Tolerance & Reliability CDA 5140 Chapter 2 - Cyclic Polynomial Codes
Fault Tolerance & Reliability CDA 5140 Chapter 2 - Cyclic Polynomial Codes
Fault Tolerance & Reliability CDA 5140 Chapter 2 - Cyclic Polynomial Codes
CDA 5140
Chapter 2 Cyclic Polynomial Codes
cylic code: special type of parity check code such that every cyclic shift
of codeword is a codeword
for example, if (cn-1, cn-2, . . . c0) is a codeword so is (cn-2, cn-3, . . . c0, cn-1)
cyclic property best captured using polynomial algebra over a finite field, in
particular binary finite field
two most important concepts are use of polynomial division and the
operation of modulo a polynomial
for f(X) and g(X) two polynomials with the latter of at least degree 1, then
the Euclid division algorithm states that there are two polynomials q(x), the
quotient, and r(x), the remainder such that
f(X) = q(X)g(X) + r(X)
and degree of r(x) is less than degree of g(X)
and further state that r(x) is congruent to f(X) modulo g(x), i.e.
r(X) = f(X) [mod g(X)]
- thus
- just as can generate any (n,m) parity-check code using the generator matrix G,
can also generate the code words for (n,m) cyclic code by the generator
polynomial g(X) with the following properties:
- g(X) is unique lowest-degree nonzero code polynomial with coefficient 1
in highest-degree term
- degree of g(X) is n m
- each of the 2m code words of binary cyclic code is multiple of g(X) of
form
i Xi g(X), 0 < i < m-1
- set of code polynomials g(X), Xg(X), . . . Xm-1g(X) is a linearly
independent set and all 2m code words can be generated from these m
code words
- g(X) must be a factor of Xn 1
Example:
-
7-tuples
X3 + X + 1
X4 + X2 + X
X5 + X3 + X2
X6 + X4 + X3
0001011
0010110
0101100
1011000
d(X)
g2
gn-m
g1
g0
c(X)
digit dm-1 is fed in first, then dm-2 and so on until d0 followed by (n-m)
zeroes
and
d(X) = X2 + 1
use the above circuit to generate c(X) and verify using polynomial
multiplication that the resulting c(X) is g(X) times d(X)
can generate a systematic code by applying the following and creating the
corresponding circuit
then need to design a feedback shift register to divide Xn-m d(X) by g(X) to
determine r(X)
the following circuit does so, where the register is initialized to all zeroes,
and with dm-1 fed in first, and then dm-2, . . . d0 sequentially in that order
until dm-1 reaches the furthest right position
then perform m right shifts which then leaves the digits of r(X) in the
register with pn-m-1 in the furthest right position
note in the following figure, since the coefficient of Xn-m must be 1 there is
no corresponding multiplication needed as for the other positions; and,
the first cell simply holds the bit before the clock pulse, while the
remaining cells hold the results
d(X)
g0
g1
+
+
+
+
g2
g n-m-2
gn-m-1
for the original d(X) = X2 + 1 and g(X) = X3 + X + 1, draw the FSR and
perform the division, give the resulting r(X) and c(X), and show, using
polynomial division that c(X) is a multiple of g(X)
-
of interest is that this same feedback shift register can be used for
encoding and error detection
if the received polynomial is y(X) and the error polynomial is e(X), then
if y(X) is not a code word, then dividing by g(X) will give a remainder
which is referred to as a syndrome (polynomial) s(X) and indicates an
error