CS 354 - Machine Organization

Wednesday, October 12, 2016

Project p3 (6%) due 10 pm Monday, October 24th (exam week)

Homework hw4 (1.5%) due 10 pm Friday, October 14th
Last Time
Three Faces of Memory
Locality
Today
Locality (from last time)
Memory Hierarchies (from last time)
Processor Layout
Cache Idea & Terms
Next Time
Read: B&O 6.4.1 - 6.4.2
Cache Memory Organization

Copyright 2016 Jim Skrentny

CS 354 (F16): L16 - 1

Simplified Processor Layout

QUAD CORE PROCESSOR

Core 0

Core 1

Core 2

Core 3

REGISTER 0
REGISTER 1
...
REGISTER N

REGISTER 0
REGISTER 1
...
REGISTER N

REGISTER 0
REGISTER 1
...
REGISTER N

REGISTER 0
REGISTER 1
...
REGISTER N

ALU

ALU

ALU

ALU

Bus Interface

Bus Interface

Bus Interface

Bus Interface

L1

L1

L1

L1

L2

L2

L2

L2

Processor Bus Interface

L3 Unified Cache

System Bus
I/O BRIDGE
Memory Bus
MAIN MEMORY

Copyright 2016 Jim Skrentny

CS 354 (F16): L16 - 2

Cache Idea & Terms

Cache
4 byte (word) block
L1

64 byte (16 words) block

Cache Miss
L2
cold miss:

conflict miss:

capacity miss:

blk#
MM

64 byte (16 words) block

Cache Hit
0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

Placement Policy

Replacement Policy

Victim Block

Working Set

Copyright 2016 Jim Skrentny

CS 354 (F16): L16 - 3