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Unit 4
Unit 4
Clock period The logic circuitry in each stage Si has a time delay denoted by i .
Let l be the time delay of each interface latch. The clock period of a linear
pipeline is defined by
It should be noted that the maximum speedup isS k k ,for n >> k. In other
words, the maximum speedup that a linear pipeline can provide us is k ,
where k is the number of stages in the pipe. The maximum speedup is never
fully achievable because of data dependencies between instructions,
interrupts, and other factors.
Efficiency :The efficiency of a linear pipeline is measured by the percentage
of busy time-space spans over the total time-space span, which equals the sum
of all busy and idle time-space spans. Let n, k, be the number of tasks
(instructions), the number of pipeline stages, and the clock period of a linear
pipeline, respectively. The pipeline efficiency is defined by
Note that 1as n . This implies that the larger the number of
tasks flowing through the pipeline, the better is its efficiency. Moreover, we
realize that = Sk /k . This provides another view of efficiency of a linear
pipeline as the ratio of its actual speedup to the ideal speedup k . In the steady
state of a pipeline, we have n >> k, the efficiency should approach 1.
However, this ideal case may not hold all the time because of program
branches and interrupts, data dependency, and other reasons.
Throughput :The number of results (tasks) that can be completed by a
pipeline per unit time is called its throughput. This rate reflects the computing
power of a pipeline. In terms of efficiency and clock period of a linear
pipeline, we define the throughput as follows:
Processing sequence
S1 S2 S1 S2 S3 S1 S3 S1
Reservation table for function X
Latency Analysis:
Optimization technique:
Insertion of Delay stages
Modification of reservation table
New CV
Improved state diagram
To yield an optimal latency cycle
Bounds on MAL
MAL is lower-bounded by the maximum number of
checkmarks in any row of the reservation table.
MAL is lower than or equal to the average latency of
any greedy cycle in the state diagram.
Average latency of any greedy cycle is upperbounded
by the number of 1s in the initial CV plus 1.
Optimal latency cycle is selected from one of the lowest
greedy cycles.
output
to resource conflicts
before date Y and Z are located in.
the store of sum to memory location X must wait three cycles for the add to
finish due to flow dependence.