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Chapter 2 Solutions PDF
Chapter 2 Solutions PDF
CHAPTER 2
2.1
(a)
xyz
x+y+z
000
001
010
011
100
101
110
111
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
xyz
(xy + z)
(b)
(c)
(d)
(x + y + z)' x'
1
1
1
1
0
0
0
0
y'
z'
xyz
(xyz)
(xyz)'
x'
y'
z'
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
000
001
010
011
100
101
110
111
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
0
(x + z)
000
001
010
011
100
101
110
111
1 1
0
1
0
1
0
1
1
1
1
xyz
x(y + z)
xy
xz
xy + xz
000
001
010
011
100
101
110
111
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
(y + z)
0
1
0
1
1
1
1
1
1
(x + z)(y + z)
0
1
1
1
0
1
1
1
0
1
0
1
0
1
1
1
xyz
y+z
x + (y +z)
(x + y)
(x + y) + z
000
001
010
011
100
101
110
111
0
0
0
0
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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12
(e)
2.2
xyz
yz
x(yz)
xy
(xy)z
000
001
010
011
100
101
110
111
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
2.3
2.4
(c) A'B(D' + C'D) + B(A + A'CD) = B(A'D' + A'C'D + A + A'CD) = B(A'D' + A + A'D(C + C')
= B(A + A'(D' + D)) = B(A + A') = B
(d) (A' + C)(A' + C')(A + B + C'D)
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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13
2.5
(d)
A
0
Fsimplified
(e)
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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14
z
Fsimplified
2.6
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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15
(c)
x
Fsimplified
(e)
A
D
Fsimplified = 0
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16
2.7
(b)
w
Fsimplified
(c)
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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17
Fsimplified
(d)
A
Fsimplified
2.8
F
F'
F.F'
= AC + BD
= (AC + BD)' = (AC)'(BD)' = (A' + C')(B' + D')
= (AC + BD)(AC)'(BD)'
= (AC) (AC)' + (BD) (BD)'
= ((AC) + (AC)')' + ((BD) + (BD)')'
= (1)' + (1)'
because,
(AC) + (AC) = 1 and
=0
F + F' = (AC + BD) + (A' + C')(B' + D')
(BD) + (BD) = 1
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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= ((AC)'(BD)')' + (AC)'(BD)'
= X' + X
= (X.X')' = (0)'
=1
2.9
2.10
(a)
F = x'y' + xy
F' = (x'y' + xy)' = (x'y')'(xy)' = (x + y) (x' + y') = xy' + x'y
(b)
F
F'
= ac + ab' + a'bc'
= (ac + ab' + a'bc')'
= (ac)'(ab')'(a'bc')'
= (a' + c')(a' + b)(a + b' + c)
= (a' + a'b + a'c' + bc')(a + b' + c)
= (a' (1 + b + c') + bc')(a + b' + c)
= (a' + bc')(a + b' + c)
= (a' + bc')(a + (bc')')
= (a' + x)(a + x')
assume: bc' = x
= a'x' + ax
= (a xnor x) = (a xnor bc')
(c)
(d)
2.11
(a) F
j and mi mj = 1 if
i=j
(b) F
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
F
1
1
0
1
1
1
0
1
F
0
0
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19
0
0
1
1
1
1
2.12
(a)
(b)
(c)
(d)
(e)
(f)
(g)
2.13
1
1
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
A = 10110001
B = 00001110
A AND B = 00000000
A OR B
= 10111111
A XOR B
= 10111111
NOT B
= 11110001
NOT A
= 01001110
A NAND B = 11111111
A NOR B
= 01000000
(a) F = (u + x)(y + z)
(b)
u x y
x
Y = (u xor y)' + x
(u xor y)'
(c)
u
y z
(u'+ x')
Y = (u'+ x')(y + z')
(y + z')
(d)
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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20
u x y
u(x xor z)
Y = u(x xor z) + y'
y'
(e) F = u + (yz + uxy)
(f) F = u +x +x (u + y) + xy
2.14
(a) F = xy + xz + xy
(b)
F = xy + xz + xy = (x + y) + (x + z) + (x + y)
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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21
(c) F = xy + xz + xy = [(xy)(xz)(xy)]
(d) F = xy + xz + xy = [(xy)(xz)(xy)]
(e) F = xy + xz + xy = (x + y) + (x + z) + (x + y)
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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22
2.15
2.16
(a) Logical product of all the 3 variable maxterms can be written as,
F(a, b, c)
= M7.M6.M5.M4.M3.M2.M1.M0
= m7.m6.m5.m4.m3.m2.m1.m0
= (m7 + m6 + m4 + m3 + m2 + m1 + m0)
= ((a + a) (bc + bc + bc + bc))
= ((b + b) (c + c))
= (1)
=0
because; mi = Mi
because; a + a = 1
OR
= M7.M6.M5.M4.M3.M2.M1.M0
= (a + b + cc) (a + b + cc) (a + b + cc) (a + b + cc)
= (a + bb) (a + bb)
because; cc = 0 & (a + b) (a + b) = a + bb
= aa
=0
(b) Logical product of all n variable maxterms can be written as,
= (Mi Mi)
for,
i = 0, 1, . . . , (2n 1)
= M0 M0 + M1 M1 + M2 M2 + . . . . . . + M2n-1 M2n1
=0+0+....+0
because,
X.X = 0
=0
2.17
2.18
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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(a)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
(b)
(c)
(d)
y z
(a)
(d)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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24
2.20
2.21
(a) F(w, x, y, z) = (1, 3, 5, 7, 9) = (0, 2, 4, 6, 8, 10, 11, 12, 13, 14, 15)
(b) F(A, B, C, D) = (3, 5, 8, 11, 13, 15) = (0, 1, 2, 4, 6, 7, 9, 10, 12, 14)
2.22
2.23
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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25
2.24
x y = x'y + xy'
and (x
y)'
= (x + y')(x' + y)
2.25
2.26
y)'
Not commutative
Not associative
Commutative
Associative
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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0
0
1
1
0
1
0
1
1
0
0
0
In positive logic
In negative logic
0
0
1
1
0
1
0
1
1
1
1
0
LOW = 0 HIGH = 1
LOW = 1 HIGH = 0
2.27
f1 = (0, 2, 3, 5, 6)
f1(a, b, c) = a'b'c' + a'bc' + a'bc + ab'c + abc'
2.28
a bcde
0 0000
0 0001
0 0010
0 0011
0 0100
0 0101
0 0110
0 0111
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
0 1111
1 1000
1 1001
1 1010
1 1011
1 1100
1 1101
1 1110
1 1111
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27
(b) y1 = a (c + d + e)= a'(c + d +e) + a(c'd'e') = a'c + a'd + a'e + ac'd'e'
y2 = b'(c + d + e)f = b'cf + b'df + b'ef
a'--d-000100 = 8
000101 = 9
000110 = 10
000111 = 11
a'---e000010 = 2
000011 = 3
000110 = 6
000111 = 7
001100 = 12
001101 = 13
001110 = 14
001111 = 15
001100 = 12
001101 = 13
001110 = 14
001111 = 15
001010 = 10
001011 = 11
001110 = 14
001111 = 15
011000 = 24
011001 = 25
011010 = 26
011011 = 27
010100 = 20
010101 = 21
010110 = 22
010111 = 23
010010 = 18
010011 = 19
010110 = 22
010111 = 23
011100 = 28
011101 = 29
011110 = 30
011111 = 31
011100 = 28
011101 = 29
011110 = 30
011111 = 31
011010 = 26
011001 = 27
011110 = 30
011111 = 31
a-c'd'e'100000 = 32
100001 = 33
110000 = 34
110001 = 35
-b' c--f
-b' -d-f
-b' --ef
001001 = 9
001011 = 11
001101 = 13
001111 = 15
101001 = 41
101011 = 43
101101 = 45
101111 = 47
001001 = 9
001011 = 11
001101 = 13
001111 = 15
101001 = 41
101011 = 43
101101 = 45
101111 = 47
000011 = 3
000111 = 7
001011 = 11
001111 = 15
100011 = 35
100111 = 39
101011 = 51
101111 = 55
y1 = (2, 3, 6, 7, 8, 9, 10 ,11, 12, 13, 14, 15, 18, 19, 22, 23, 24, 25, 26, 27, 28,
29, 30, 31, 32, 33, 34, 35 )
y2 = (3, 7, 9, 13, 15, 35, 39, 41, 43, 45, 47, 51, 55)
2.29
ab cdef
y1 y2
ab cdef
y1 y2
ab cdef
y1 y 2
ab cdef
y1 y2
00 0000
00 0001
00 0010
00 0011
00 0100
00 0101
00 0110
00 0111
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
1
01 0000
01 0001
01 0010
01 0011
01 0100
01 0101
01 0110
01 0111
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
10 0000
10 0001
10 0010
10 0011
10 0100
10 0101
10 0110
10 0111
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
1
11 0000
11 0001
11 0010
11 0011
11 0100
11 0101
11 0110
11 0111
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
00 1000
00 1001
00 1010
00 1011
00 1100
00 1101
00 1110
00 1111
1
1
1
1
1
1
1
1
0
1
0
0
0
1
0
1
01 1000
01 1001
01 1010
01 1011
01 1100
01 1101
01 1110
01 1111
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
10 1000
10 1001
10 1010
10 1011
10 1100
10 1101
10 1110
10 1111
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
11 1000
11 1001
11 1010
11 1011
11 1100
11 1101
11 1110
11 1111
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(a)
True.
(b)
False.
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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28
2.30
2.31
Digital Design With An Introduction to the Verilog HDL Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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