CSE 31L Lecture 1 Notes

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Course Administration
a. Midterm Project: 30%
b. Final Project: 40%
c. Final Exam: 30%
Abstraction
a. Architecture Micro Architecture Logic Digital Circuits
Introduction to SystemVerilog
a. Verilog/SystemVerilog syntax is similar to C/C++
b. One purpose is to use it to program FPGA boards
c. Has a goal of simulation, verification and synthesis
i. Simulation behavior prediction of a design (functional simulation assumes all output
changes at the same time) (timing simulation trys to predict the exact behavior of the
design)
ii. Synthesis Is the process of converting a design into absolute gate-level netlist
d. Lexical Conventions Model 1
e. Numbers (binary, octal, hexidecimal, decimal) Model 2
f. SystemVerilog is case sensitive
2-to-1 Multiplexer Model 3
Week 2 and 3 design objectives (can be found on GitHub)
a. Multiplexer
b. Decoder
c. Encoder
d. Comparator
e. Half Adder
f. Full Adder
g. Adder/Subtractor
h. Sign Extender
i. Shifter
j. Complementer

CSE 31L Lecture 2 Notes

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SystemVerilog Basics
a. Designs in SystemVerilog consists of I/O ports
b. Data Types
i. 0 (False), 1 (True), x (Unknown), z (High Impedance)
ii. wire (net) connects different elements
iii. reg stands for registers
iv. logic
c. Data Objects
i. Vectors Multi-bit data objects with a specified range (Model 4)
ii. Packed vs. Unpacked (Model 5)
1. Packed array refers to dimensions declared before the object name
2. Unpacked array refers to dimensions declared after the object name
3. You can store any data type in an unpacked array
4. Packed dimensions can only be used with packable types
iii. Constant
1. Has a single value of a given type
2. Constant value cannot change during the simulation
3. Constant definitions can be done using `define, localparam, parameter and
specparam (Model 6)
iv. Combinational Full Adder Model 7
1. Reordering the code does not affect the outcome because it runs in parallel
d. Modeling Styles
i. Data flow Model 8
ii. Structural Model 9
iii. Behavorial (Sequenial and uses the always_comb key) Model 10
e. Operators
i. Nonblocking versus blocking Model 11
ii. Operators
1. not (~)
2. and (&)
3. or (|)
4. nand (~&)
5. nor (~|)
6. xor (^)
7. xnor (~^)
iii. Logical and Arithmetic Shift
1. Logic shift: 4b1111 << 3 = 4b1000
2. Logic shift: 4b1111 >> 3 = 4b0001
3. Arithmetic Shift: 4b1000 >>> 2 = 4b1110

CSE 31L Lecture 3 Notes

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Generate construct, always_comb, 128-bit ALU Midterm Project (ommitted from this outline)
Review

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a. Concatenation Model 12
b. Concatenation with comma and replication Model 13
Concurrent statements
a. These are statements that happen at the same time Model 14
Generate Model 15
a. Generate is a loop statement that runs at compile time
b. It repeats a part of code a number of times
c. There are two kinds of generate statements
i. Loops, which allow a single generate block to be instantiated into a model multiple times
(Model 16).
ii. Conditionals that include if and case
iii. XOR Tree Model 17
iv. Vertical Shifter Model 18
v. Gray to Binary Converer Model 19
Concurrent Statements
a. We can model combinational circuits by using sequential coding
b. We do this by using the always_comb procedure
c. The always_comb feature provides functionality that is different than the always procedure.
i. There is an inferred sensitivity list
ii. Automatically executes once at time zero
iii. Model 20
Implicit instantiation versus explicit instantiation
a. Implicit instantiation is in order. The parameters are not restated, so no .a(). The parameters
must be in order though.
b. Explicit instantiation requires the user to state the parameter being used.
c. Model 21